SR Flip Flop
SR Flip Flop
in/online-study-material/fet/cs/diploma/iiisemester/digitalelectronics/
lecture-5.pdf
https://mrajacse.wordpress.com/wp-content/uploads/2013/09/unit-3-flip-flop-notes.pdf
https://www.idc-online.com/technical_references/pdfs/electronic_engineering/Flip_Flops.pdf
S-R Flip Flop
The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates.
These flip flops are also called S-R Latch.
The SR Flip Flop has two inputs, SET (S) and RESET (R).
The SR Flip Flop has two outputs, Q and Q̅
The Q output is considered the normal output and is the one most used.
The other output Q̅ is simply the compliment of output Q.
The NAND gate version has two inputs, SET (S) and RESET (R).
Two outputs, Q as normal output and Q̅ as inverted output and feedback
mechanism.
The feedback mechanism is required to form a sequential circuit by
connecting the output of NAND-1 to the input of NAND-2 and vice
versa.
The circuit outputs depends on the inputs and also on the outputs.
S=1, R=0—Q=0, Q’=1 This state is also called the SET state.
S=0, R=1—Q=1, Q’=0 This state is known as the RESET state. In
both the states you can see that the outputs are just compliments of each
other and that the value of Q follows the compliment value of S.
S=0, R=0—Q=1, & Q’ =1 [Invalid] If both the values of S and R are
switched to 0 it is an invalid state because the values of both Q and Q’
are 1. They are supposed to be compliments of each other. Normally, this
state must be avoided.
S=1, R=1—Q & Q’= Remember If both the values of S and R are
switched to 1, then the circuit remembers the value of S and R in their
previous state.
[SR Flip Flop - NOR GATE]
The latch circuit can also be constructed using two NOR gates latch.
The construction is similar to the NAND latch except that the normal
output Q and inverted output Q̅ have reversed positions.
S=0, R=0—Q & Q’ = Remember If both the values of S and R are switched to 0, then the circuit
remembers the value of S and R in their previous state.
S=0, R=1—Q=0, Q’=1 This state is known as the RESET state. In both the
states you can see that the outputs are just compliments of each other and
that the value of Q follows the value of S.
S=1, R=0—Q=1, Q’=0 This state is also SET called the state.
S=1, R=1—Q=0, Q’=0 [Invalid] This is an invalid state because the values
of both Q and Q’ are 0. They are supposed to be compliments of each other.
Normally, this state must be avoided.
REFERENCE:
https://www.ramauniversity.ac.in/online-study-material/fet/cs/diploma/iiisemester/digitalelectronics/
lecture-5.pdf
https://mrajacse.wordpress.com/wp-content/uploads/2013/09/unit-3-flip-flop-notes.pdf
https://www.idc-online.com/technical_references/pdfs/electronic_engineering/Flip_Flops.pdf