Applications of Flip-flops

By Nilesh Patidar and Shiraz Husain

Shift Register
One flip-flop can store one-bit of information.
In order to store multiple bits of information, we require multiple flip-flops.
The group of flip-flops, which are used to hold store the binary data is
known as register.
If the register is capable of shifting bits either towards right hand side or
towards left hand side is known as shift register.
There are the four types of shift registers-
Serial In − Serial Out shift register
Serial In − Parallel Out shift register
Parallel In − Serial Out shift register
Nilesh
Parallel In − Parallel Out shift Patidar
register and Shiraz
Husain
Serial In − Serial Out (SISO)

0110
011
01
0 0
1 0
1 0

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Serial In − Parallel Out (SIPO)

0
0110
011
01
0 0
1 0
1

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Parallel In Serial Out

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Parallel In − Serial Out (PISO)

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Parallel In − Serial Out (PISO)

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Parallel In − Parallel Out (PIPO)

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 Bidirectional Shift Register

M=0 then Shift Left

M=1then Shift Right

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Applications of Shift Register
Shift register is used as Parallel to serial converter, which converts
the parallel data into serial data. It is utilized at the transmitter
section after Analog to Digital Converter ADC block.
Shift register is used as Serial to parallel converter, which converts
the serial data into parallel data. It is utilized at the receiver section
before Digital to Analog Converter DAC block.
Shift register along with some additional gates generate the
sequence of zeros and ones. Hence, it is used as sequence generator.
Shift registers are also used as counters.
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Ring Counter
No. of states in Ring counter = No. of flip-flop used
Init Clk Q0 Q1 Q2 Q3

L X 1 0 0 0

H 0 1 0 0

H 0 0 1 0

H 0 0 0 1

H 1 0 0 0
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Johnson Ring Counter
No. of states in counter = 2* No. of flip-flop used
Clk Q1 Q2 Q3 Q4
X 0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
0 0 0 0
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Binary Counters
An ‘N’ bit binary counter consists of ‘N’ flip-flops and it can count
the numbers up to 2 − 1 (2 States)
If the counter counts from 0 to 2 − 1, then it is called as binary up
counter.
Similarly, if the counter counts down from 2 − 1 to 0, then it is called
as binary down counter.
There are two types of counters based on the flip-flops that are
connected in synchronous or not.
Asynchronous counters
Synchronous counters
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Asynchronous or Ripple Counters
Asynchronous counters are those whose output is free from the
clock signal.
The first flip-flop is triggered by the clock signal and others
successive flip-flops are driven by output of previous flip flops in
asynchronous counters.

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Synchronous Counters
Synchronous counters are sometimes called parallel counters as the
clock is fed in parallel to all flip-flops.
The output of all flip-flops are triggered by a single source of clock.

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Synchronous v/s Asynchronous
Synchronous Asynchronous
All flip flops are triggered with same clock Different flip flops are triggered with different
simultaneously. clock, not simultaneously.
It is faster in operation It is slower in operation.
It does not produce any decoding errors. It produces decoding error.
It is also called Parallel Counter. It is also called Serial Counter.
The designing as well implementation are The designing as well as implementation is
complex due to increasing the number of very easy.
states. It will operate only in fixed count sequence
It will operate in any desired count sequence (UP/DOWN).
Examples are: Ring counter, Johnson counter. Examples are: Ripple UP counter, Ripple
Propagation delay is less. DOWN counter.
High propagation delay.
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Asynchronous Up Counters (4-bit)
(LSB) (MSB)

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Asynchronous Up Counters (Alternate Configuration)
(LSB) (MSB)

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Asynchronous Down Counters (4-bit)

(LSB) (MSB)

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Asynchronous Up-Down Counters (4-bit)

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MOD-N Counters
The number of flip flops used in a ripple counter is depends on the
number of states of counter.
The number of output states of counter is called “Modulus” or
“MOD” of the counter. (ex: Mod 4, Mod 2 etc).
For example, if we have 2 flip flops, the maximum number of
2
outputs of the counter is 4 i.e. 2 . So it is called as “MOD-4 counter”
or “Modulus 4 counter”.
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple
counter is called as MOD-8 counter. So, an n-bit ripple counter is called as
n
modulo-N counter. W here, MOD number N = 2
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Nilesh Patidar and Shiraz
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Mod-6 counter (Ripple)
(LSB) (MSB)
Here N=6
So number flip-flops will be
n-1 n
2 ≤ N ≤ 2 (so, n=3)

For N=6
Q2 Q1 Q0
1 1 0 (Binary of 6)

So Q1and Q2 are inputs of

NAND Gate because Q1=Q2=1

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Synchronous Up Counters (4-bit)
(LSB) (MSB)

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Synchronous Down Counters (4-bit)
(LSB) (MSB)

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Husain
Synchronous Up-Down Counters (4-
bit)
(LSB) (MSB)

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Husain
Synchronous Up-Down Counters (4-
bit)
(LSB) (MSB)

W henNilesh
it is acting asand
Patidar Up counter
Shiraz
Husain
Synchronous Up-Down Counters (4-
bit)
(LSB) (MSB)

W henNilesh
it is acting as and
Patidar Down counter
Shiraz
Husain
Design of Synchronous Counter
1. Determine the number (n) of FFs needed to support the counting
sequence’s highest number.
2n -1 ≥ Highest number
2. Build a State Transition Diagram. Be sure to include all states.
3. Build a State Table & Excitation Table.
4. Simplify expressions for all inputs for each F/F on K-Maps.
5. Implement the Synchronous Counter/State Machine Circuit.
6. Draw the Timing Diagram (If Needed).

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Decade Counter (Synchronous)
Determine the number (n) of FFs needed to support the counting
sequence’s highest number. (Count from 0 to 9)
n
2 -1 ≥ Highest number
n
2 -1 ≥ 9
n
2 ≥ 10
So, n = 4
It means, there are 4 FFs are required to design Decade Counter
(MOD-10 counter that counts from 0 to 9)

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Decade Counter (Synchronous)
Build a State Transition Diagram

0 0000

9 1 1001 0001

8 2 1000 0010

7 3 0111 0011

6 4 0110 0100

5 Nilesh Patidar and Shiraz

0101

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 PS NS SR-FF D-FF
PS NS
JK-FF JK-FF
T-FF

Qt Q t+1 S R QDt JQ t+1 K J TK

Decade Counter
0 0 0 X 00 00 X0 0X

0 1 1 0 01 11 X 1 1X

1 0 0 1 10 X0 1X 11

State Table & Excitation Table 1 1 X 0 11 X1 0 X 00

Present State Next State Excitation Inputs (For JK FF)

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 10 0 X 0 X 1 X X 1
0 0 10 0 0 11 0 X 0 X X 0 1 X
0 0 11 0 10 0 0 X 1 X X 1 X 1

0 10 0 0 10 1 0 X X 0 0 X 1 X

0 10 1 0 110 0 X X 0 1 X X 1
0 110 0 111 0 X X 0 X 0 1 X
0 111 10 0 0 1 X X 1 X 1 X 1

10 0 0 10 0 1 X 0 0 X 0 X 1 X

10 0 1 0 0 0 0 X 1 0 X 0 X X 1
 Decade Counter
Simplify expressions for all inputs for each F/F on K-Maps.
J3 Q1Q0 K3 Q1Q0
Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’
Q3Q2 (00) (01) (11) (10) Q3Q2 (00) (01) (11) (10)
Q3’Q2’ Q3’Q2’
0 0 0 0 X X X X
(00) 0 1 3 2 (00) 0 1 3 2

Q3’Q2 Q3’Q2
0 0 1 0 X X X X
(01) 4 5 7 6 (01) 4 5 7 6

Q3Q2 Q3Q2
X X X X X X X X
(11) 12 13 15 14
(11) 12 13 15 14

Q3Q2’ Q3Q2’
X X X X 0 1 X X
(10) 8 9 11 10 (10) 8 9 11 10

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J3 = Q 2Q 1Q 0 Husain K3 = Q 0
 Decade Counter
Simplify expressions for all inputs for each F/F on K-Maps.
J2 Q1Q0 K2 Q1Q0
Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’
Q3Q2 (00) (01) (11) (10) Q3Q2 (00) (01) (11) (10)
Q3’Q2’ Q3’Q2’
0 0 1 0 X X X X
(00) 0 1 3 2 (00) 0 1 3 2

Q3’Q2 Q3’Q2
X X X X 0 0 1 0
(01) 4 5 7 6 (01) 4 5 7 6

Q3Q2 Q3Q2
X X X X X X X X
(11) 12 13 15 14
(11) 12 13 15 14

Q3Q2’ Q3Q2’
0 0 X X X X X X
(10) 8 9 11 10 (10) 8 9 11 10

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J2 = Q 1Q 0 Husain K2 = Q 1Q 0
 Decade Counter
Simplify expressions for all inputs for each F/F on K-Maps.
J1 Q1Q0 K1 Q1Q0
Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’
Q3Q2 (00) (01) (11) (10) Q3Q2 (00) (01) (11) (10)
Q3’Q2’ Q3’Q2’
0 1 X X X X 1 0
(00) 0 1 3 2 (00) 0 1 3 2

Q3’Q2 Q3’Q2
0 1 X X X X 1 0
(01) 4 5 7 6 (01) 4 5 7 6

Q3Q2 Q3Q2
X X X X X X X X
(11) 12 13 15 14
(11) 12 13 15 14

Q3Q2’ Q3Q2’
0 0 X X X X X X
(10) 8 9 11 10 (10) 8 9 11 10

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J1 = Q 3’Q 0 Husain K1 = Q 0
 Decade Counter
Simplify expressions for all inputs for each F/F on K-Maps.
J0 Q1Q0 K0 Q1Q0
Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’
Q3Q2 (00) (01) (11) (10) Q3Q2 (00) (01) (11) (10)
Q3’Q2’ Q3’Q2’
1 X X 1 X 1 1 X
(00) 0 1 3 2 (00) 0 1 3 2

Q3’Q2 Q3’Q2
1 X X 1 X 1 1 X
(01) 4 5 7 6 (01) 4 5 7 6

Q3Q2 Q3Q2
X X X X X X X X
(11) 12 13 15 14
(11) 12 13 15 14

Q3Q2’ Q3Q2’
1 X X X X 1 X X
(10) 8 9 11 10 (10) 8 9 11 10

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J0 = 1 Husain K0 = 1
Decade Counter (Synchronous)
Implement the Synchronous Counter/State Machine Circuit.
J3 = Q 2Q 1Q 0
K3 = Q 0
J2 = Q 1Q 0
K2 = Q 1Q 0
J1 = Q 3’Q 0
K1 = Q 0
J0 = 1
K0 = 1
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Applications of counters
Frequency counters
Digital clock
Time measurement
A to D converter
Frequency divider circuits
Digital triangular wave generator
Ramp signal generator

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Thank You

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