Objectives

Discussion on Virtualization

Resource
virtualization
Partitioning and
Multiprocessor
Virtual machine virtualization
types
Virtualization,
para-
Why virtualization, virtualization,
and virtualization virtual machines
properties and hypervisors

Last Session
 Background: Computer System
Architectures
1
Application Programs
Instruction Set
Architecture (ISA): 7 & 8 2
3 3 Software
Application Binary Libraries
OS
Interface (ABI): 3 & 7
4 5 6
Memory
Application Drivers Manager Scheduler
Programming ISA
Interface (API): 2 & 7 8 8 8 8 7 7

9
Execution Hardware
Memory Translation
10 10
System Interconnect (bus)
11 11 12 Hardware

Controllers Controllers
13 14
I/O Devices &
Main Memory
Networking
 Types of Virtual Machines
 As there is a process perspective and a system perspective of machines,
there are also process-level and system-level VMs

 Virtual machines can be of two types:

1. Process VM

• Capable of supporting an individual process

2. System VM

• Provides a complete system environment

• Supports an OS with potentially many types of processes
 Process Virtual Machine
Guest Application Process Application Process

Virtualizing Software
Runtime

OS Virtual Machine

Host
Hardware

 Runtime is placed at the ABI interface

 Runtime emulates both user-level instructions and OS system calls
 System Virtual Machine
Applications Applications

Guest OS OS

Virtualizing Software
VMM Virtual Machine

Host Hardware

 VMM emulates the ISA used by one hardware platform to another, forming
a system VM
 A system VM is capable of executing a system software environment
developed for a different set of hardware
Native and Hosted VM Systems

Guest Guest
Applications Applications
Guest
Applications Guest OS Guest OS

Applications
Nonprivileged
Guest OS VMM VMM modes

Privileged
OS VMM modes
Host OS Host OS

Hardware Hardware Hardware Hardware

Traditional Native User-mode Dual-mode

Uniprocessor VM System Hosted Hosted
System VM System VM System
 A Taxonomy
Process VMs System VMs

Same Different Same Different

ISA ISA ISA ISA

Multiprogrammed Dynamic Classic-System Whole-System

Systems Translators VMs VMs

Dynamic HLL VMs Hosted Co-designed

Binary VMs VMs
Optimizers
The Versatility of VMs
Java Application
JVM

Linux IA-32

VMWare

Windows IA-32

Code Morphing

Crusoe VLIW
 Objectives
Discussion on Virtualization

Resource
virtualization
Partitioning and
Multiprocessor
Virtual machine virtualization
types
Virtualization,
para-
Why virtualization, virtualization,
and virtualization virtual machines
properties and hypervisors
 Multiprocessor Systems
 Multiprocessor systems might have 1000s of processors connected to TBs
of memory and PBs of disk capacity

 Often there is a mismatch between the ideal number of processors an

application needs and the actual number of physical processors available

 It is more often the case that applications cannot exploit more than a
fraction of the processors available. The is mainly because of:

 Limitations in the parallelism available in the programs

 Limitations in the scalability of applications due to the overhead of

communication between processors
 Partitioning
 The increasing availability of multiprocessor systems has led to the
examination of techniques that can help utilize them more effectively

 Techniques have been developed in which the multiprocessor system can

be partitioned into multiple partitions

 A partition is given a subset of the resources available on the system

 Hence, using partitioning, multiple applications can simultaneously exploit

the available resources of the system

 Partitioning can be achieved:

 Either in-space (referred to as physical partitioning)
 Or in-time (referred to as logical partitioning)
 Physical Partitioning
 With physical partitioning, each partition is assigned resources that are
physically distinct from the resources used by the other partitions

Partition 1 Partition 2 Partition 3

P P P P P P P P P P P P

P P P P P P P P P P P P

M M M M M M
I/O I/O I/O I/O I/O I/O

D D D D D D D D D D D D
 Physical Partitioning
 Physical partitioning allows a partition to own its
resources physically

 It is not permissible for two partitions to share the resources of a

single system board

 Partitions are configured by a central control unit that receives

commands from the console of the system admin and provisions
hardware resources accordingly

 The number of partitions that can be supported in physically

partitioned systems is limited to the number of available
physical processors
 Physical Partitioning- Advantages
 Physical partitioning provides:

 Failure Isolation: it ensures that in the event of a failure, only the part of
the physical system that houses the failing partition will be affected

 Better security isolation: Each partition is protected from the possibility

of intentional or unintentional denial-of-service attacks by
other partitions

 Better ability to meet system-level objectives (these result from

contracts between system owners and users of the system)

 Easier management of resources: no need of sophisticated algorithms

for scheduling and management of resources
Physical Partitioning- Disadvantages
 While physical partitioning has a number of attractive features, it has
some major disadvantages:

 System utilization: Physical partitioning is probably not the ideal

solution if system utilization is to be optimized

 It is often the case that each of the physical partitions

is underutilized

 Load balancing: with physical partitioning, dynamic workload

balancing becomes difficult to implement
 Logical Partitioning
 With logical partitioning, partitions share some of the physical resources,
usually in a time-multiplexed manner

P P P P P P P P P P P P

P P P P P P P P P P P P

M M M M M M
I/O I/O I/O I/O I/O I/O

D D D D D D D D D D D D
 Logical Partitioning
 With logical partitioning it is permissible for two partitions to share
the resources of a single system board

 Logical partitioning makes it possible to partition an n-way system

into a system with more than n partitions, if so desired

 Logical partitioning is more flexible than physical partitioning but

needs additional mechanisms to provide safe and efficient way
of sharing resources

 Logical partitioning is usually done through a VMM or a hypervisor

and provides what is referred to as multiprocessor virtualization
 Multiprocessor Virtualization
 A virtualized multiprocessor gives the appearance of a system that may or
may not reflect the exact configuration of the underlying physical system

P P P P P P P P P P P P

M I/O M I/O M I/O M I/O

Virtual Machine Monitor

Processor Processor Processor Processor

Cache Cache Cache Cache

Bus or Crossbar Switch

Memory
I/O
 Objectives
Discussion on Virtualization

Resource
virtualization
Partitioning and
Multiprocessor
Virtual machine virtualization
types
Virtualization,
para-
Why virtualization, virtualization,
and virtualization virtual machines
properties and hypervisors
 Resource Virtualization

Resource Virtualization

CPU Virtualization Memory Virtualization I/O Virtualization

22
 CPU Virtualization
 Interpretation and Binary Translation
 Virtualizable ISAs
 CPU Virtualization
 Interpretation and Binary Translation
 Virtualizable ISAs
 Instruction Set Architecture
 Typically, the architecture of a processor defines:

1. A set of storage resources (e.g., registers and memory)

2. A set of instructions that manipulate data held in storage resources

 The definition of the storage resources and the instructions that

manipulate data are documented in what is referred to as
Instruction Set Architecture (ISA)

 Two parts in the ISA are important in the definition of VMs:

1. User ISA: visible to user programs

2. System ISA: visible to supervisor software (e.g., OS)
 Ways to Virtualize CPUs
 The key to virtualize a CPU lies in the execution of the guest
instructions, including both system-level and user-level instructions

 Virtualizing a CPU can be achieved in one of two ways:

1. Emulation: the only processor virtualization mechanism available

when the ISA of the guest is different from the ISA of the host

2. Direct native execution: possible only if the ISA of the host is

identical to the ISA of the guest
 Emulation
 Emulation is the process of implementing the interface and
functionality of one system (or subsystem) on a system (or
subsystem) having different interface and functionality

 In other words, emulation allows a machine implementing one ISA

(the target), to reproduce the behavior of a software compiled for
another ISA (the source)
Guest

Source ISA
 Emulation can be carried out using:

Emulated by
1. Interpretation
Host
2. Binary translation
Target ISA
 Basic Interpretation
Source Memory State Source Context Block
 Interpretation involves a
4-step cycle (all in software): Code
Program Counter

Condition Codes

1. Fetching a source instruction Reg 0

Data Reg 1
2. Analyzing it •
•
•
3. Performing the required operation Reg n-1
•
•
4. Then fetching the next
source instruction Stack Interpreter Code
 Decode-And-Dispatch
 A simple interpreter, referred to as decode-and-dispatch, operates by stepping
through the source program (instruction by instruction) reading and modifying
the source state
Source Code Source Code Interpreter
Routines

 Decode-and-dispatch is structured
around a central loop that decodes an
Dispatch
instruction and then dispatches it to an Loop

interpretation routine

 It uses a switch statement to call a

number of routines that emulate
individual instructions

Decode-And-
Native
Dispatch
Execution
Interpretation
 Decode-And-Dispatch- Drawbacks
Source Code Interpreter
 The central dispatch loop of a decode-and- Routines

dispatch interpreter contains a number of

branch instructions Dispatch
Loop

 Indirect branch for the switch statement

 A branch to the interpreter routine
 A second register indirect branch to return from the
interpreter routine
 And a branch that terminates the loop

 These branches tend to degrade performance

Decode-And-
Dispatch
Interpretation
Indirect Threaded Interpretation
 To avoid some of the branches, a portion of the dispatch code can be
appended (threaded) to the end of each of the interpreter routines

Interpreter Source Code Interpreter

 To locate interpreter routines, Source Code
Routines Routines
a dispatch table and a jump
instruction can be used when
stepping through the Dispatch
Loop
source program

 This scheme is referred to as

indirect threaded interpretation

Decode-And- Indirect
Dispatch Threaded
Interpretation Interpretation
 Indirect Threaded Interpretation-
Drawbacks Interpreter
Source Code
Routines
 The dispatch table causes an overhead when
looked up:

 It requires a memory access and a register

indirect branch

 An interpreter routine is invoked every time the same

instruction is encountered

 Thus, the process of examining the instruction and

extracting its various fields is always repeated
Indirect
Threaded
Interpretation
 Predecoding (1)
 It would be more efficient to perform a repeated operation only once
PowerPC source code
 We can save away the Lwz r1, 8(r2) //load word and zero
extracted information of an instruction Add r3, r3, r1 //r3 = r3 +r1
in an intermediate form Stw r3, 0(r4) //store word

PowerPC program in
 The intermediate form can then be predecoded intermediate form
simply reused whenever an instruction
is re-encountered for emulation 07 (load word
1 2 08 and zero)

08
 However, a Target Program Counter 3 1 03
(add)
(TPC) will be needed to step
through the intermediate code 37 (store word)
3 4 00
 Predecoding (2)
 To avoid a memory lookup whenever the dispatch table is accessed,
the opcode in the intermediate form can be replaced with the address
of the interpreter routine

07 (load word 001048d0 (load word

1 2 08 and zero) 1 2 08 and zero)

08 (add) 00104800 (add)

3 1 03 3 1 03

37 (store word) 00104910 (store word)

3 4 00 3 4 00

 This leads to a scheme referred to as direct threaded interpretation

Direct Threaded Interpretation
Interpreter Source Code Intermediate Code Interpreter
Source Code
Routines Routines

Predecoder

Indirect
Direct Threaded
Threaded
Interpretation
Interpretation
 Direct Threaded Interpretation-
Drawbacks
 Direct threaded interpretation still suffers Interpreter
Source Code Intermediate Code
from major drawbacks: Routines

1. It limits portability because the

intermediate form is dependent on the
exact locations of the interpreter routines
Predecoder
2. The size of predecoded memory image is
proportional to the original source
memory image

3. All source instructions of the same type

are emulated with the same
interpretation routine
 Binary Translation
 Performance can be significantly enhanced by mapping each
individual source binary instruction to its own customized target code

 This process of converting the source binary program into a target

binary program is referred to as binary translation

 Binary translation attempts to amortize the fetch and analysis

costs by:

1. Translating a block of source instructions to a block of target instructions

2. Caching the translated code for repeated use
 Binary Translation
Source Code Intermediate Code Interpreter Source Code Binary Translated Target
Routines Code

Binary
Predecoder Translator

Direct Threaded
Interpretation Binary
Translation
 Static Binary Translation
 It is possible to binary translate a program in its entirety before
executing the program

 This approach is referred to as static binary translation

 However, in real code using conventional ISAs, especially CISC

ISAs, such a static approach can cause problems due to:

Data in instruction
 Variable-length instructions Inst. 1 Inst. 2
stream
Inst. 3 jump
 Data interspersed with instructions
Reg. Data
 Pads to align instructions Inst. 5 Inst. 6
Pad for instruction
 Register indirect jumps Uncond. Branch Pad
alignment
Inst. 8

Jim indirect to ???

 Dynamic Binary Translation
 A general solution is to translate the binary while the program is
operating on actual input data (i.e., dynamically) and interpret new
sections of code incrementally as the program reaches them

 This scheme is referred to as dynamic binary translation

Source Program
Counter (SPC) to
Target Program
Counter (TPC)
Map Table
Interpreter Translator
Miss

Hit

Emulation
Manager

Code Cache
Dynamic Binary Translation
Start
with
SPC

Look Up
SPCTPC
in Map Table

No Use SPC to
Hit in
Table Read Instructions
from Source
Memory Image
Yes -----------------------
Interpret,
Branch to TPC
Translate, and
and Execute
Place into Code
Translated
Cache
Block

Write New
Get SPC for SPCTPC
Next Block Mapping into
Map Table
 Next Class
Discussion on Virtualization

Resource
virtualization
Partitioning and
Multiprocessor
Virtual machine virtualization
types
Virtualization,
para-
Why virtualization, virtualization,
and virtualization virtual machines
properties and hypervisors