Q.1 What is the minimum feature size or technology in VLSI?

A. The minimum feature size, often referred to as the technology node, is the smallest
dimension in a semiconductor manufacturing process. It is typically measured in nanometers
(nm) and represents the size of the smallest features that can be reliably fabricated on a
semiconductor chip. Smaller feature sizes generally result in higher transistor density and
improved performance.

Q.2 What do you understand by monolithography in VLSI?

A. Monolithography in VLSI refers to the process of creating integrated circuits on a single

semiconductor substrate using a series of photolithographic steps. This involves the use of
masks and light exposure to define patterns on the silicon wafer. Monolithic integration allows
for the integration of various components, such as transistors, resistors, and capacitors, on a
single chip.

Q.3 State advantages of monolithic integration.

A. Advantages of monolithic integration include:

 Reduced size and weight of electronic devices.

 Lower power consumption due to shorter interconnections.
 Improved performance and speed.
 Enhanced reliability and durability.
 Reduced manufacturing cost per chip.
 Simplified packaging and assembly.

Q.4 What is the difference between die and chip?

A. In semiconductor manufacturing:

 "Die" refers to an individual, unpackaged piece of silicon containing the active

components like transistors and logic gates.
 "Chip" refers to the same die after it has been packaged, often encapsulated in plastic or
ceramic with pins or pads for external connections.

Q.5 What is Moore’s law?

A. Moore's Law is an empirical observation made by Gordon Moore, co-founder of Intel. It states
that the number of transistors on a semiconductor chip doubles approximately every two years
while the cost per transistor decreases. This observation has driven the rapid advancement of
semiconductor technology and the increase in computational power over time.

Q.6 What is the primary difference between planar MOSFET and FinFET?

. The primary difference between planar MOSFETs and FinFETs lies in their transistor structures:

 Planar MOSFETs have a flat, two-dimensional structure with the gate controlling the flow
of current on the silicon surface.
 FinFETs have a three-dimensional "fin" structure that extends vertically from the silicon
substrate. This design provides better control of current flow and reduces leakage
 current, improving energy efficiency and performance.

Q.7 What is a GAA MOSFET?

A. A Gate-All-Around (GAA) MOSFET is a type of transistor where the gate material completely
surrounds the channel region on all sides. It is a three-dimensional transistor structure that
offers superior control of current and reduced leakage compared to traditional planar MOSFETs
or FinFETs.

Q.8 What are the performance parameters of any VLSI chip?

A. Performance parameters of a VLSI chip include:

 Speed (clock frequency).

 Power consumption.
 Area (chip size).
 Energy efficiency.
 Delay.
 Noise margins.
 Signal-to-noise ratio (SNR).
 Reliability.
 Yield.

Q.9 Draw the famous trade-off triangle of VLSI chip design.

A. The trade-off triangle in VLSI chip design typically represents the trade-offs between three key
parameters: Performance, Power, and Area. The triangle illustrates that improving one of these
parameters often comes at the expense of the other two. However, I can't draw diagrams, so
you'd need to refer to your textbook or find an image online for a visual representation.

Q.10 What is the difference between static and dynamic VLSI circuits?

A. Static and dynamic VLSI circuits differ in their operation:

 Static circuits use combinational logic gates to produce outputs that are stable and do
not change until new inputs are provided. They have low power consumption when idle
but high power during switching.
 Dynamic circuits use clocked logic gates and require a clock signal to operate. They
consume power continuously but only switch and dissipate significant power when the
clock transitions.

Q.11 What are the design abstraction levels in VLSI? Explain the top-down and down-top
designing approaches in a brief manner.

A. Design abstraction levels in VLSI include:

 System-level: Describes high-level functionality and requirements.

 Architectural-level: Defines the overall system architecture.
 RTL (Register-Transfer Level): Specifies how data flows between registers and
operations.
 Gate-level: Describes logic gates and interconnections.
 Layout-level: Specifies the physical layout and placement of components.
 Top-Down Design: It starts with a high-level system description and gradually refines it
 into lower-level components and details. This approach focuses on functionality before
implementation.
 Bottom-Up Design (or Down-Top): It starts with individual components and modules,
gradually building up to create higher-level system functionality. This approach focuses
on implementation details first.

Q.12 Draw a very basic design flow for VLSI.

A. A basic VLSI design flow involves the following steps:

1. Requirements and Specification

2. Architecture Design
3. RTL Design
4. Functional Verification
5. Logic Synthesis
6. Gate-Level Simulation
7. Floorplanning
8. Placement
9. Clock Tree Synthesis (CTS)
10. Routing
11. Physical Verification (DRC, LVS)
12. Post-Synthesis Simulation
13. Tape-Out (Final Chip Fabrication)

Front-End designing related questions:

Q.13 List the steps in Front-end VLSI design.

A. Front-end VLSI design steps include:

1. System Requirements and Specifications

2. Architectural Design
3. RTL (Register-Transfer Level) Design
4. Functional Verification
5. Logic Synthesis
6. Pre-Synthesis Functional Verification

Q.14 Explain system requirements or design specifications.

A. System requirements or design specifications define the functionality, performance, and

constraints of the desired VLSI system. They include details like input/output behavior, power
consumption limits, timing constraints, and more.

Q.15 Briefly explain the importance of defining architecture at the front-end.

A. Defining the architecture at the front-end is crucial as it determines the high-level structure of
the design. It helps in achieving the desired functionality, performance, and resource allocation
before delving into detailed implementation, saving time and effort.

Q.16 What do you understand by RTL?

A. RTL stands for Register-Transfer Level. It's a level of abstraction in VLSI design where digital
circuits are described in terms of registers, logical operations, and data transfers between
registers. RTL is closer to the hardware implementation than higher-level abstractions but still
abstracts away lower-level details.

Q.17 Explain the typical meaning of RTL coding.

A. RTL coding involves describing digital circuits using high-level constructs such as registers
and data transfers. It focuses on the flow of data between registers and the logic operations
performed on that data. RTL code is used to design the behavior of a digital circuit at a level
closer to hardware than software.

Q.18 Briefly explain the pre-synthesis functional verification step during front-end designing.

A. Pre-synthesis functional verification involves checking the correctness of the RTL code before
it is synthesized into gates. It ensures that the design behaves as expected, meets specifications,
and does not contain logical errors. This step helps catch and fix issues early in the design
process.

Back-End designing related questions:

Q.20 Enlist the steps in Back-end VLSI design.

A. Back-end VLSI design steps include:

1. Floorplanning
2. Placement
3. Clock Tree Synthesis (CTS)
4. Routing
5. Physical Verification (DRC, LVS)
6. Post-Synthesis Simulation
7. Tape-Out (Final Chip Fabrication)

Q.21 Briefly explain the need for the design-for-testability (DFT) step in Back-end VLSI design.

A. Design-for-Testability (DFT) is essential in back-end VLSI design to ensure that manufactured

chips can be effectively and efficiently tested for defects and faults. DFT techniques include
adding test structures, scan chains, and built-in self-test (BIST) features to facilitate fault
detection and diagnosis during manufacturing testing and throughout the chip's life.

Q.22 Differentiate between Floorplan and Placement processes..

 Floorplanning: It defines the high-level allocation of space on the chip for various
functional blocks, cores, and I/O pads. It determines their approximate locations, sizes,
and relationships, considering power and signal integrity constraints.
 Placement: Placement is the process of precisely positioning and orienting cells (logic
gates) within the predefined areas allocated during floorplanning. It optimizes the
placement to minimize wirelength, delay, and power consumption.

Q.23 Describe the importance of clock-tree-synthesis (CTS) step.

A. The clock tree synthesis (CTS) step is crucial for ensuring reliable and efficient clock
distribution within an integrated circuit. It involves creating a hierarchical tree-like structure to
distribute clock signals to all sequential elements (flip-flops) with minimal skew and power
consumption. A well-designed clock tree is vital for meeting timing requirements and preventing
clock domain crossing issues.

Q.24 What do you understand by interconnect and which material is preferable for it?

A. Interconnect refers to the wiring or metal layers that connect various components (transistors,
gates, etc.) on an integrated circuit. The preferable material for interconnect is typically copper.
Copper has lower resistivity than aluminum, making it more suitable for achieving lower
resistance and better performance in modern VLSI designs.

Q.25 Explain the significance of Routing in VLSI.

A. Routing in VLSI is the process of establishing physical connections between logic gates and
other components through interconnects. The significance of routing lies in ensuring that all
connections meet timing constraints, avoiding congestion (overlapping routes), and minimizing
wirelength and parasitic capacitance. Effective routing is crucial for achieving optimal chip
performance.

Q.26 What do you understand by physical verification in VLSI?

A. Physical verification in VLSI involves checking the physical layout of the chip for compliance
with design rules and manufacturing constraints. It includes Design Rule Checking (DRC) to
ensure the layout adheres to process-specific rules and Layout vs. Schematic (LVS) verification
to verify that the layout matches the intended schematic.

Q.27 What is the design-rule-check (DRC) tool in back-end design?

A. The Design Rule Checking (DRC) tool is a software tool used in back-end VLSI design to verify
whether the physical layout of the chip adheres to the design rules specified by the
semiconductor fabrication process. DRC ensures that there are no violations of minimum feature
sizes, spacing, and other constraints defined by the process technology.

Q.28 What is parameter extraction (PEX) in VLSI layout design?

A. Parameter extraction (PEX) is the process of extracting and modeling the electrical
parameters of interconnects and devices in an integrated circuit layout. This information is used
for simulating and analyzing the circuit's electrical performance, including signal delays, parasitic
capacitance, and resistance.

Q.29 Differentiate between "tap-out" and "sign-off" in VLSI. A.

 "Tap-out": Tap-out refers to the stage in the design process when the finalized design
data, including the layout and other necessary files, is sent to the semiconductor foundry
for manufacturing. It is the point of no return in the design process.
 "Sign-off": Sign-off refers to the stage in the design process when the design team
formally approves and verifies that the design meets all the required specifications,
constraints, and quality criteria. It involves thorough validation and ensures that the
design is ready for fabrication.

Q.30 Draw and briefly explain D. Gajski’s 'Y'-chart.

A. D. Gajski's 'Y'-chart is a graphical representation used in VLSI design to illustrate the trade-offs
between three key design parameters: Cost, Performance, and Flexibility. It resembles a Y shape,
with each arm representing one of these parameters. Designers make trade-offs between these
parameters based on project requirements and constraints.

Q.31 List the differences between two VLSI design methodologies.

A. Two commonly used VLSI design methodologies are ASIC (Application-Specific Integrated
Circuit) and FPGA (Field-Programmable Gate Array).

 ASIC Design:
 Customized for a specific application.
 Optimized for performance, power, or area.
 Requires a dedicated manufacturing process.
 Higher non-recurring engineering (NRE) costs.
 Longer design and fabrication times.
 FPGA Design:
 Programmable and reconfigurable.
 Suitable for prototyping and quick iterations.
 Uses a pre-defined FPGA architecture.
 Lower NRE costs compared to ASICs.
 Shorter time-to-market.

Q.32 List the steps involved in ASIC design.

A. ASIC (Application-Specific Integrated Circuit) design steps typically include:

1. Specification and Requirements

2. Architecture Design
3. RTL Design
4. Functional Verification
5. Logic Synthesis
6. Gate-Level Simulation
7. Floorplanning
8. Placement
9. Clock Tree Synthesis (CTS)
10. Routing
11. Physical Verification (DRC, LVS)
12. Post-Synthesis Simulation
13. Tape-Out (Final Chip Fabrication)

Q.33 Explain the FPGA design flow.

A. The FPGA (Field-Programmable Gate Array) design flow involves the following steps:

1. Specification: Define the functionality and requirements.

2. High-Level Synthesis (optional): Convert high-level code into RTL.
3. RTL Design: Create the design at the Register-Transfer Level.
4. Functional Verification: Verify design behavior.
5. Synthesis: Convert RTL into FPGA-specific logic.
6. Place and Route: Place logic elements and create routing connections.
7. Bitstream Generation: Generate the configuration bitstream.
8. Configuration: Load the bitstream onto the FPGA.
9. Testing and Debugging: Test the design on the FPGA.
10. Iteration: Modify and retest as needed.
Q.34 What is the meaning of TTM?

A. TTM stands for "Time-to-Market" in VLSI design. It represents the duration it takes to develop
a semiconductor product (e.g., an integrated circuit) and bring it to market. Reducing TTM is
crucial for staying competitive and meeting market demands.

Q.35 What do you understand by the maturity time of the VLSI design?

A. The maturity time of a VLSI design refers to the phase in the design process when the design
has been thoroughly validated, and all issues, including bugs and performance optimizations,
have been addressed. It's the point at which the design is considered mature and ready for
manufacturing or deployment.

Q.36 What do you understand by design hierarchy? Explain the concept of design reuse in VLSI.

A. Design hierarchy in VLSI refers to organizing a complex design into a structured hierarchy of
modules, sub-modules, and components. Each level of the hierarchy abstracts and encapsulates
functionality. Design reuse involves creating modular components that can be used in multiple
designs. Reusable components simplify design, reduce errors, and improve productivity.

Q.37 Define the terms: Regularity, locality, modularity.

A.

 Regularity: Regularity in VLSI design refers to the use of uniform or repetitive structures,
such as identical cells, to simplify layout and reduce complexity.
 Locality: Locality refers to the concept of grouping related components or functions
close to each other in the layout or architecture to minimize interconnect length and
improve performance.
 Modularity: Modularity involves dividing a design into well-defined, independent modules
that can be developed, tested, and maintained separately. It promotes reusability and
simplifies design and verification.

Q.38 What are the types of VLSI chip packages?

A. VLSI chip packages include various types:

 Dual In-Line Package (DIP)

 Surface Mount Device (SMD) packages like QFP, BGA, and LGA
 Chip-on-Board (COB)
 Chip-on-Flex (COF)
 Chip-on-Glass (COG)
 Chip-on-Chip (COC)
 System-on-Chip (SoC) packages

Q.39 What is the yield of an IC?

A. The yield of an Integrated Circuit (IC) is the percentage of working or defect-free chips
produced during the manufacturing process. It represents the ratio of good chips to the total
number of chips fabricated. High yield is desirable as it reduces production costs.

Q.40 What are the VLSI design quality metrics? A. VLSI design quality metrics include:
  Performance (speed, power, area)
 Reliability (fault tolerance, MTBF)
 Power consumption
 Area utilization
 Timing constraints (setup and hold times)
 Signal integrity
 Design reusability
 Testability (DFT features)
 Yield
 Cost

Q.41 Explain the PAL and PLA structure in PLDs.

A.

 PAL (Programmable Array Logic): PAL is a type of Programmable Logic Device (PLD)
that uses fixed OR gates and programmable AND gates. It provides a more flexible
solution than fixed logic gates.
 PLA (Programmable Logic Array): PLA is another type of PLD that has both
programmable AND and OR arrays. It offers greater flexibility in terms of logic functions
and input connections.

Q.42 Explain the role of macrocell structure in CPLD.

A. Macrocells in Complex Programmable Logic Devices (CPLDs) are configurable logic blocks
that include flip-flops and combinatorial logic. They provide the ability to implement custom logic
functions, state machines, or other complex logic operations within the CPLD. Macrocells can be
programmed to perform specific tasks, making them highly versatile.

Q.43 Draw the implementation of the following functions using PAL structure.

 𝑓 = 𝑥 1'𝑥 2 + 𝑥 1𝑥 2'
 𝑓 = 𝑥 1'𝑥 2𝑥 3 + 𝑥 1𝑥 2'𝑥 3' A. I can't provide visual diagrams, but I can describe the
general structure of PAL implementation:
 For 𝑓 = 𝑥 1'𝑥 2 + 𝑥 1𝑥 2':
 You would configure the PAL to have two inputs, 𝑥 1 and 𝑥 2.
 Use one programmable OR gate to combine the complement (𝑥 1') and non-
complement (𝑥 2) inputs.
 Use another programmable OR gate to combine the non-complement (𝑥 1) and
complement (𝑥 2') inputs.
 The outputs of these OR gates would then be fed into a programmable AND gate
to implement the logic function 𝑓 .
 For 𝑓 = 𝑥 1'𝑥 2𝑥 3 + 𝑥 1𝑥 2
 For 𝑓 = 𝑥 1'𝑥 2𝑥 3 + 𝑥 1𝑥 2'𝑥 3':
 You would configure the PAL to have three inputs, 𝑥 1, 𝑥 2, and 𝑥 3.
 Use one programmable OR gate to combine the complement (𝑥 1'), non-
complement (𝑥 2), and non-complement (𝑥 3) inputs.
 Use another programmable OR gate to combine the non-complement (𝑥 1),
complement (𝑥 2'), and non-complement (𝑥 3) inputs.
 The outputs of these OR gates would then be fed into a programmable AND gate
to implement the logic function 𝑓 .

In both cases, the PAL structure allows you to configure the specific connections and logic
operations to implement the desired Boolean functions.

Q.44 Compare CPLD and FPGA.

A.

 CPLD (Complex Programmable Logic Device):

 Contains macrocells with flip-flops and combinatorial logic.
 Suitable for relatively small to medium-scale logic designs.
 Provides predictable and low propagation delays.
 Typically used for control logic and glue logic.
 Configuration is static and doesn't change during operation.
 FPGA (Field-Programmable Gate Array):
 Contains configurable logic blocks (CLBs) with Look-Up Tables (LUTs) and flip-
flops.
 Suitable for a wide range of logic designs, including complex ones.
 Offers flexibility for reprogramming and adapting to various applications.
 Configuration is dynamic and can be changed during operation (reconfigurable).
 Generally used for high-performance and complex digital designs.

Q.45 Explain logic configuration in FPGA with the help of an example.

A. In an FPGA, logic configuration involves defining the functionality of the logic cells within the
device. This is done by programming the Look-Up Tables (LUTs) and interconnections. Here's an
example:

Suppose you want to implement a simple 2-input AND gate using an FPGA:

1. In the configuration process, you define that LUT entries for inputs (00, 01, 10, 11) should
output 00, 00, 00, and 01, respectively, to implement the AND function.
2. You also specify that the inputs are sourced from the external pins or internal signals.
3. The FPGA's interconnect resources are programmed to route signals appropriately,
connecting the inputs to the LUTs and routing the output to the desired output pin.

Once programmed, the FPGA effectively becomes a 2-input AND gate, and you can use it as a
building block in your larger design.

Q.46 Implement the following designs using an FPGA and calculate the total number of LUTs
required for the designs. You can choose any best suitable input LUT (i.e., 2, 3, 4, 5, or 6 input
LUT). Provide the reason for selecting the type of LUT.

1. 16-to-1 MUX
2. 256-to-1 MUX
3. 1-bit Full Adder A. Implementing these designs in an FPGA:
4. 16-to-1 MUX:
 To implement a 16-to-1 MUX, you would need a 4-input LUT. Each 4-input LUT
can represent one of the 16 input combinations and select one of the data inputs.
You would need 16 such LUTs for a 16-to-1 MUX.
5. 256-to-1 MUX:
 To implement a 256-to-1 MUX, you would need an 8-input LUT. Each 8-input LUT
can represent one of the 256 input combinations and select one of the data
inputs. You would need 256 such LUTs for a 256-to-1 MUX.
6. 1-bit Full Adder:
  A 1-bit Full Adder typically requires a combination of logic gates such as AND,
XOR, and OR gates. The exact number of LUTs needed depends on how you
optimize the design, but it can usually be implemented using a few 2-input or 4-
input LUTs for each bit.

The total number of LUTs required for each design is determined by the number of input
combinations that need to be represented and the size of the LUT (2-input, 3-input, etc.) used for
implementation.