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HW2 2024-2

The document is a practice midterm for a Digital Logic Design course, outlining various problems for students to solve, including truth tables, Karnaugh maps, and Boolean function simplifications. It requires students to show their work for each problem and includes tasks such as circuit design and implementation using different types of gates. Additionally, it emphasizes the importance of understanding duality and circuit modifications.

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Lý Khải Minh
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12 views2 pages

HW2 2024-2

The document is a practice midterm for a Digital Logic Design course, outlining various problems for students to solve, including truth tables, Karnaugh maps, and Boolean function simplifications. It requires students to show their work for each problem and includes tasks such as circuit design and implementation using different types of gates. Additionally, it emphasizes the importance of understanding duality and circuit modifications.

Uploaded by

Lý Khải Minh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DLD Homework

DIGITAL 2
LOGIC DESIGN
Term I – 2024-2025
PRACTICE MIDTERM
Student 1’s Name: ________________ Student 1’s code____________________
Student 2’s Name: ________________ Student 2’s code____________________

Please attach this page to the front of your work. Show your work for each problem.

1. Use the truth table to prove that x+(yz)=(x+y)(x+z)


2. Suppose that you have proven a’c+a’b+ab’c+bc+g+ce+ef+ce’+ag=c+a’b+ef+g. What is the
dual of it? Give the reason why the dual is valid given that
a’c+a’b+ab’c+bc+g+ce+ef+ce’+ag=c+a’b+ef+g is valid. Note that you cannot simply say that it
is due to duality theorem and you should try to avoid using truth table method in the proof.
3. Use Karnaugh map to simplify the Boolean function a’c’d+ab’+cd’+a’bc’
4. Simplify the function of F(A,B,C,D)=∑ m(0,1,2,4,5,7,8,9,10,12,13)
5. Simplify the function of F(A,B,C,D)=∑ m(0,1,2,3,7,14,15) + d(4,5).
6. Use Karnaugh map to simplify the Boolean function a’b’c’+acd+a’bc’+c’d’, implement the
circuit using AND, OR and NOT gates, and use NAND gates and NOT gates to implement it.
7. Simplify and Implement the Boolean function A’B(CD+E’+G’)+F’H using AND, OR, NOT
gates. Implement it using NAND, NOT gates.
8. Write the Boolean expression for output x in the following figure. Determine the value of x for
all possible input conditions, and list the values in a truth table.

a.
b.

9. Convert the circuit of Figure 8a to one using only NOR gates. Then write the output expression
for the new circuit, simplify it using DeMorgan’s theorems, and compare it with the expression
for the original circuit
10. The circuit of Figure 8b is supposed to be a simple digital combination lock whose output will
generate an active-LOW signal for only one combination of inputs.
a. Modify the circuit diagram so that it represents more effectively the circuit operation.
b. Use the new circuit diagram to determine the input combination that will activate the
output.
11. For each of the following expressions, construct the corresponding logic circuit, using AND and
OR gates and INVERTERs
c. 𝑥 = 𝐴𝐵(𝐶 + 𝐷)
d. 𝑦 = (𝑀 + 𝑁 + 𝑃𝑄)
e. 𝑧 = 𝐴 + 𝐵 + 𝐶𝐷𝐸 + 𝐵𝐶𝐷
12. Implement y = ABCD using only two-input NAND gates.
13. Simplify the following expression using Boolean algebra
a. 𝑥 = 𝐴 𝐵 𝐶 + 𝐴 𝐵 𝐶 + 𝐴 𝐵 𝐶 + 𝐴 𝐵 𝐶 + 𝐴 𝐵 𝐶
b. 𝑦 = (𝐶 + 𝐷) + 𝐴 𝐶 𝐷 + 𝐴 𝐵 𝐶 + 𝐴 𝐵 𝐶 𝐷 + 𝐴 𝐶 𝐷
c. 𝑧 = (𝐵 + 𝐶)(𝐵 + 𝐶) + 𝐴 + 𝐵 + 𝐶
14. Design the logic circuit corresponding to the truth table and then implement the circuit using all
NAND gates.

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