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Agilex™ 5 FPGAs and SoCs Device Data Sheet

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 Contents

Contents

Agilex™ 5 FPGAs and SoCs Device Data Sheet............................................................................................................................ 3

Electrical Characteristics...................................................................................................................................................... 4
Operating Conditions.................................................................................................................................................. 4
Switching Characteristics....................................................................................................................................................56
Core Performance Specifications.................................................................................................................................56
Periphery Performance Specifications.......................................................................................................................... 73
GTS Transceiver Performance Specifications.................................................................................................................89
HPS Performance Specifications................................................................................................................................100
Configuration Specifications.............................................................................................................................................. 162
General Configuration Timing Specifications............................................................................................................... 162
POR Specifications..................................................................................................................................................163
External Configuration Clock Source Requirements......................................................................................................164
JTAG Configuration Timing.......................................................................................................................................164
AS Configuration Timing.......................................................................................................................................... 165
Avalon Streaming Configuration Timing..................................................................................................................... 168
Configuration Bit Stream Sizes................................................................................................................................. 169
I/O Timing......................................................................................................................................................................170
Programmable IOE Delay..................................................................................................................................................170
Glossary.........................................................................................................................................................................170
Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet....................................................................... 174

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Agilex™ 5 FPGAs and SoCs Device Data Sheet

This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing.

Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel's
discretion.

Table 1. Data Sheet Status for Agilex™ 5 FPGAs and SoCs

Devices Status

All devices Preliminary

The following descriptors designate the status level currently applicable to the relevant variant:
• Advance: These are target specifications based on simulation.
• Preliminary: These specifications are based on simulation, early validation, and/or early characterization data.
• Final: These are production specifications based on silicon validation and/or characterization.

Table 2. Device Grades, Core Speed Grades, and Power Options Supported
For specification status, see the Data Sheet Status table

Series Device Group Temperature Grade Speed Grade and Power Option
Supported

D A Extended / Industrial –1V (fastest)

–2V

–3V

E A Extended / Industrial –1V (fastest)

–2V
continued...

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera and Intel warrant performance of its

FPGA and semiconductor products to current specifications in accordance with Altera’s or Intel's standard warranty as applicable, but reserves the right to make
changes to any products and services at any time without notice. Altera and Intel assume no responsibility or liability arising out of the application or use of any ISO
information, product, or service described herein except as expressly agreed to inwriting by Altera or Intel. Altera and Intel customers are advised to obtain the 9001:2015
latest version of device specifications before relying on any published information and before placing orders for products or services. Registered
*Other names and brands may be claimed as the property of others.
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Series Device Group Temperature Grade Speed Grade and Power Option
Supported

–2E

–3V

B Extended / Industrial –4S (fastest)

–5S

–6S

–6X

The suffix after the speed grade denotes the power options offered.
• V—standard power (VID)
• E—low power (VID)
• S—standard power (fixed voltage)
• X—low power (fixed voltage)

Electrical Characteristics

Operating Conditions
The devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of
the devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these
conditions.

Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

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Table 3. D-Series FPGAs Absolute Maximum Ratings

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Maximum Unit

VCC Core voltage supply — –0.5 1.21 V

VCCP Periphery supply voltage — –0.5 1.21 V

for the I/O banks

VCCH_SDM SDM block transceiver — –0.5 1.332 V

supply voltage sense

VCCPT Power supply for I/O, DTS, — –0.5 2.08 V

SDM, and system PLL

VCCRCORE Power supply for — –0.5 1.64 V

programmable power
technology

VCCBAT Battery back-up power — –0.5 2.08 V

supply (for design security
volatile key register)

VCCIO_PIO_SDM SDM block I/O supply 1.2 V –0.5 1.6 V

voltage sense of bank 3A

VCC_IO_SDM I/O digital supply voltage — –0.5 1.21 V

sense in SDM block

VCCIO_SDM SDM block configuration — –0.5 2.08 V

pins power supply

VCCL_ADC_SDM Periphery digital supply — –0.5 1.21 V

voltage sense to ADC,
senses HPS digital supply
on HPS devices, core
supply on non-HPS devices

VCCL_SDM SDM digital power supply — –0.5 1.07 V

VCC_HSSI_[L1, R4] Transceiver, system PLL, — –0.5 1.07 V

and hard IP digital power
supply

VCCPLLDIG_SDM SDM block PLL digital — –0.5 1.07 V

power supply
continued...

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Symbol Description Condition Minimum Maximum Unit

VCCPLL_SDM SDM block PLL analog — –0.5 2.08 V

power supply

VCCFUSEWR_SDM Fuse block writing power — –0.5 2.08 V

supply

VCCADC ADC voltage sensor power — –0.5 2.08 V

supply

VCCL_HPS HPS DSU voltage and — –0.5 1.21 V

periphery circuitry power
supply

VCCL_HPS_CORE0_CORE1 HPS A55 cores power rail — –0.5 1.21 V

VCCL_HPS_CORE2 HPS A76 core power rail — –0.5 1.21 V

VCCL_HPS_CORE3 HPS A76 core power rail — –0.5 1.21 V

VCCPLLDIG1_HPS HPS PLL1 digital power — –0.5 1.21 V

supply

VCCPLLDIG2_HPS HPS PLL2 digital power — –0.5 1.21 V

supply

VCCPLL1_HPS HPS PLL1 analog power — –0.5 2.08 V

supply

VCCPLL2_HPS HPS PLL2 analog power — –0.5 2.08 V

supply

VCCIO_HPS HPS I/O buffers power — –0.5 2.08 V

supply

VCCEHT_GTS[L1, R4][A, B, C, D] Transceiver PMA, TX PLL, — –0.5 2.08 V

transceiver reference
clock, and global reference
clock high-voltage analog
power supply

VCCERT_GTS[L1, R4][A, B, C, D] Transceiver PMA, — –0.5 1.34 V

transceiver reference
clock, and global reference
clock low-voltage analog
power supply

VCCIO_PIO HSIO bank power supply VCCIO_PIO = 1.0 V –0.5 1.365 V

continued...

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Symbol Description Condition Minimum Maximum Unit

VCCIO_PIO = 1.05 V –0.5 1.43 V

VCCIO_PIO = 1.1 V –0.5 1.5 V

VCCIO_PIO = 1.2 V –0.5 1.64 V

VCCIO_PIO = 1.3 V –0.5 1.74 V

VCCIO_HVIO HVIO bank power supply VCCIO_HVIO = 3.3 V –0.5 3.74 V

VCCIO_HVIO = 2.5 V –0.5 2.83 V

VCCIO_HVIO = 1.8 V –0.5 2.04 V

VCCPT_HVIO Supply voltage for 1.8 V — –0.5 2.04 V

I/O

VI DC input voltage VCCIO_PIO = 1.0 V(1) (2) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.05 V(1) (2) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.1 V(1) (2) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.2 V(1) (2) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.3 V(1) (2) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_SDM = 1.8 V –0.3 VCCIO_SDM(MAX) + 0.3 V

VCCIO_HPS = 1.8 V –0.3 VCCIO_HPS(MAX) + 0.3 V

VCCIO_HVIO = 1.8 V, 2.5 V, –0.3 VCCIO_HVIO(MAX) + 0.3 V

3.3 V

IOUT (3) (4) DC output current per pin VCCIO_PIO = 1.0 V, 1.05 V, –7.5 7.5 mA
1.1 V, 1.2 V, 1.3 V (5) (6)
continued...

(1) Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
(2) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO(MAX)
+ 0.3 V.
(3) Total current per I/O bank must not exceed 100 mA.
(4) Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.

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Symbol Description Condition Minimum Maximum Unit

VCCIO_SDM, VCCIO_HPS = 1.8 –20 20 mA

V (7)

VCCIO_HVIO = 1.8 V, 2.5 V, –8 8 mA

3.3 V Current Strength
Setting = 12 mA(8) (9)

VCCIO_HVIO = 1.8 V, 2.5 V, –6 6 mA

3.3 V Current Strength
Setting = 9 mA(8) (9)

VCCIO_HVIO = 1.8 V, 2.5 V, –4 4 mA

3.3 V Current Strength
Setting = 6 mA(8) (9)

VCCIO_HVIO = 1.8 V, 2.5 V, –2 2 mA

3.3 V Current Strength
Setting = 3 mA(8) (9)

TJ (10) Absolute junction — –40 125 °C

temperature

TSTG Storage temperature — –55 150 °C

(5) The maximum current allowed through any HSIO pin during power-up/power-down conditions is 10 mA. Pin voltage during these
conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower
voltage. While this device is not turned on, the I/O pin should be tri-stated or not driven with any external voltages.
(6) The DC output current per pin may exceed 7.5 mA with a duration limit. For more details, refer to the related information.
(7) The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down
conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the
I/O pin resides in.
(8) The maximum current allowed through any HVIO pin when the device is not turned on or during power-up/power-down conditions is
10 mA. Pin voltage during these conditions should not exceed VCCIO_HVIO supply rail of the bank where the I/O pin resides in.
(9) The DC output current per pin may exceed specified values with a duration limit. For more details, refer to General Purpose I/O User
Guide.
(10) When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device
lifetime of 11.4 years.

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Table 4. E-Series FPGAs Absolute Maximum Ratings

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Maximum Unit

VCC Core voltage supply SmartVID: –1V, –2V, –2E, –0.5 1.21 V
–3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCP Periphery supply voltage SmartVID: –1V, –2V, –2E, –0.5 1.21 V
for the I/O banks –3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCH_SDM SDM block transceiver SmartVID: –1V, –2V, –2E, –0.5 1.07 V
supply voltage sense –3V

Without Transceiver: –4S –0.5 1.07 V

Without Transceiver: –5S, –0.5 1.043 V

Without Transceiver: –6S, –0.5 1.004 V

–6X

With Transceiver –0.5 1.332 V

VCCPT Power supply for I/O, DTS, — –0.5 2.08 V

SDM, and system PLL

VCCRCORE Power supply for — –0.5 1.64 V

programmable power
technology

VCCBAT Battery back-up power — –0.5 2.08 V

supply (for design security
volatile key register)

VCCIO_PIO_SDM SDM block I/O supply 1.2 V –0.5 1.6 V

voltage sense of bank 3A
continued...

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Symbol Description Condition Minimum Maximum Unit

VCC_IO_SDM I/O digital supply voltage SmartVID: –1V, –2V, –2E, –0.5 1.21 V
sense in SDM block –3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCIO_SDM SDM block configuration — –0.5 2.08 V

pins power supply

VCCL_ADC_SDM Periphery digital supply SmartVID: –1V, –2V, –2E, –0.5 1.21 V
voltage sense to ADC, –3V
senses HPS digital supply
on HPS devices, core Fixed voltage: –4S –0.5 1.07 V
supply on non-HPS devices
Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –5S, –6S, – –0.5 1.004 V

6X

VCCL_SDM SDM digital power supply SmartVID: –1V, –2V, –2E, –0.5 1.07 V
–3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –5S, –6S, – –0.5 1.004 V

6X

VCC_HSSI_[L1, R4] Transceiver, system PLL, SmartVID: –1V, –2V, –2E, –0.5 1.07 V
and hard IP digital power –3V
supply
Fixed voltage: –4S –0.5 1.07

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCPLLDIG_SDM SDM block PLL digital SmartVID: –1V, –2V, –2E, –0.5 1.07 V
power supply –3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

continued...

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Symbol Description Condition Minimum Maximum Unit

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCPLL_SDM SDM block PLL analog — –0.5 2.08 V

power supply

VCCFUSEWR_SDM Fuse block writing power — –0.5 2.08 V

supply

VCCADC ADC voltage sensor power — –0.5 2.08 V

supply

VCCL_HPS HPS DSU voltage and SmartVID: –1V, –2V, –2E, –0.5 1.21 V
periphery circuitry power –3V
supply
Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCL_HPS_CORE0_CORE1 HPS A55 cores power rail SmartVID: –1V, –2V, –2E, –0.5 1.21 V
–3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCL_HPS_CORE2 HPS A76 core power rail SmartVID: –1V, –2V, –2E, –0.5 1.21 V
–3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCL_HPS_CORE3 HPS A76 core power rail SmartVID: –1V, –2V, –2E, –0.5 1.21 V
–3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

continued...

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Symbol Description Condition Minimum Maximum Unit

VCCPLLDIG1_HPS HPS PLL1 digital power SmartVID: –1V, –2V, –2E, –0.5 1.21 V
supply –3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCPLLDIG2_HPS HPS PLL2 digital power SmartVID: –1V, –2V, –2E, –0.5 1.21 V
supply –3V

Fixed voltage: –4S –0.5 1.07 V

Fixed voltage: –5S –0.5 1.043 V

Fixed voltage: –6S, –6X –0.5 1.004 V

VCCPLL1_HPS HPS PLL1 analog power — –0.5 2.08 V

supply

VCCPLL2_HPS HPS PLL2 analog power — –0.5 2.08 V

supply

VCCIO_HPS HPS I/O buffers power — –0.5 2.08 V

supply

VCCEHT_GTS[L1, R4][A, B, C] Transceiver PMA, TX PLL, — –0.5 2.08 V

transceiver reference
clock, and global reference
clock high-voltage analog
power supply

VCCERT_GTS[L1, R4][A, B, C] Transceiver PMA, — –0.5 1.34 V

transceiver reference
clock, and global reference
clock low-voltage analog
power supply

VCCIO_PIO HSIO bank power supply VCCIO_PIO = 1.0 V –0.5 1.365 V

VCCIO_PIO = 1.05 V –0.5 1.43 V

VCCIO_PIO = 1.1 V –0.5 1.5 V

VCCIO_PIO = 1.2 V –0.5 1.64 V

VCCIO_PIO = 1.3 V –0.5 1.74 V

continued...

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Symbol Description Condition Minimum Maximum Unit

VCCIO_HVIO HVIO bank power supply VCCIO_HVIO = 3.3 V –0.5 3.74 V

VCCIO_HVIO = 2.5 V –0.5 2.83 V

VCCIO_HVIO = 1.8 V –0.5 2.04 V

VCCPT_HVIO Supply voltage for 1.8 V — –0.5 2.04 V

I/O

VI DC input voltage VCCIO_PIO = 1.0 V(11) (12) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.05 V(11) (12) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.1 V(11) (12) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.2 V(11) (12) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_PIO = 1.3 V(11) (12) –0.3 VCCIO_PIO(MAX) + 0.25 V

VCCIO_SDM = 1.8 V –0.3 VCCIO_SDM(MAX) + 0.3 V

VCCIO_HPS = 1.8 V –0.3 VCCIO_HPS(MAX) + 0.3 V

VCCIO_HVIO = 1.8 V, 2.5 V, –0.3 VCCIO_HVIO(MAX) + 0.3 V

3.3 V

IOUT (13) (14) DC output current per pin VCCIO_PIO = 1.0 V, 1.05 V, –7.5 7.5 mA
1.1 V, 1.2 V, 1.3 V (15) (16)
continued...

(11) Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
(12) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO(MAX)
+ 0.3 V.
(13) Total current per I/O bank must not exceed 100 mA.
(14) Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
(15) The maximum current allowed through any HSIO pin during power-up/power-down conditions is 10 mA. Pin voltage during these
conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower
voltage. While this device is not turned on, the I/O pin should be tri-stated or not driven with any external voltages.
(16) The DC output current per pin may exceed 7.5 mA with a duration limit. For more details, refer to the related information.

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Symbol Description Condition Minimum Maximum Unit

VCCIO_SDM, VCCIO_HPS = 1.8 –20 20 mA

V (17)

VCCIO_HVIO = 1.8 V, 2.5 V, –8 8 mA

3.3 V Current Strength
Setting = 12 mA(18) (19)

VCCIO_HVIO = 1.8 V, 2.5 V, –6 6 mA

3.3 V Current Strength
Setting = 9 mA(18) (19)

VCCIO_HVIO = 1.8 V, 2.5 V, –4 4 mA

3.3 V Current Strength
Setting = 6 mA(18) (19)

VCCIO_HVIO = 1.8 V, 2.5 V, –2 2 mA

3.3 V Current Strength
Setting = 3 mA(18) (19)

TJ (20) Absolute junction — –40 125 °C

temperature

TSTG Storage temperature — –55 150 °C

Related Information
• Recommended Operating Conditions on page 20
• I/O Standard Specifications on page 41
• General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

(17) The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down
conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the
I/O pin resides in.
(18) The maximum current allowed through any HVIO pin when the device is not turned on or during power-up/power-down conditions is
10 mA. Pin voltage during these conditions should not exceed VCCIO_HVIO supply rail of the bank where the I/O pin resides in.
(19) The DC output current per pin may exceed specified values with a duration limit. For more details, refer to General Purpose I/O User
Guide.
(20) When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device
lifetime of 11.4 years.

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Maximum Allowed Overshoot and Undershoot Voltage

During transitions, the toggling input data or clock signals may overshoot to the voltage listed in the following tables and
undershoot to the following limits for input currents less than 100 mA and periods shorter than 20 ns.
• Undershoot limit of –1.1 V when using VCCIO_HPS or VCCIO_SDM of 1.8 V.
• Undershoot limit of –0.3 V when using VCCIO_PIO of 1.3 V, 1.2 V, 1.1 V, 1.05 V, and 1.0 V.

No overshooting beyond 1.602 V and undershooting below 0.273 V is allowed when using True Differential Signaling I/O
standard at VCCIO_PIO = 1.3 V.

No overshooting beyond 1.177 V and undershooting below 0.573 V is allowed when using True Differential Signaling I/O
standard at VCCIO_PIO = 1.2 V, 1.1 V, and 1.05 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over
the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 5. Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %

VCCIO_PIO + 0.30(21) 30 %

VCCIO_PIO + 0.35 4 %

> VCCIO_PIO + 0.40 No overshoot allowed %

(21) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V at an overshoot duration of 100%.

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Table 6. Maximum Allowed Overshoot During Transitions for 1.05 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %

VCCIO_PIO + 0.30(22) 30 %

VCCIO_PIO + 0.35 4 %

> VCCIO_PIO + 0.40 No overshoot allowed %

Table 7. Maximum Allowed Overshoot During Transitions for 1.1 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %

VCCIO_PIO + 0.30(23) 30 %

VCCIO_PIO + 0.35 4 %

> VCCIO_PIO + 0.40 No overshoot allowed %

(22) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V at an overshoot duration of 100%.
(23) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V at an overshoot duration of 100%.

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Table 8. Maximum Allowed Overshoot During Transitions for 1.2 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %

VCCIO_PIO + 0.30(24) 30 %

VCCIO_PIO + 0.35 4 %

> VCCIO_PIO + 0.40 No overshoot allowed %

Table 9. Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %

VCCIO_PIO + 0.30(25) 65 %

VCCIO_PIO + 0.35 7 %

> VCCIO_PIO + 0.40 No overshoot allowed %

(24) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V at an overshoot duration of 100%.
(25) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V at an overshoot duration of 100%.

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Table 10. Maximum Allowed Overshoot During Transitions for 1.8 V I/O in HPS and SDM I/O Banks

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 100 %

0.30

VCCIO_SDM + 0.35, VCCIO_HPS + 60 %

0.35

VCCIO_SDM + 0.40, VCCIO_HPS + 30 %

0.40

VCCIO_SDM + 0.45, VCCIO_HPS + 20 %

0.45

VCCIO_SDM + 0.50, VCCIO_HPS + 10 %

0.50

VCCIO_SDM + 0.55, VCCIO_HPS + 6 %

0.55

> VCCIO_SDM + 0.55, > VCCIO_HPS No overshoot allowed %

+ 0.55

Table 11. Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5 V, and 3.3 V in HVIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) (26) AC input voltage VCCIO_HVIO + 0.30 100 %

VCCIO_HVIO + 0.35 42 %

VCCIO_HVIO + 0.40 18 %
continued...

(26) This value applies to both input and output configuration.

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Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

VCCIO_HVIO + 0.45 9 %

VCCIO_HVIO + 0.50 4 %

> VCCIO_HVIO + 0.55 No overshoot allow %

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.61 V can only be at 1.61 V
for ~4% over the lifetime of the device. For an overshoot of 1.51 V, the percentage of high time for the overshoot can be as
high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V HSIO Bank at VCCIO_PIO = 1.26 V)

1.61 V

1.51 V

1.2 V

DT
T

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters.

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Recommended Operating Conditions

Table 12. D-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum(27) Typical Maximum(27) Unit

VCC Core voltage supply SmartVID(28) : –1V, – (Typical) – 3% 0.70 – 0.90(29) (Typical) + 3% V
2V, –3V

VCCP Periphery supply SmartVID(28): –1V, – (Typical) – 3% 0.70 – 0.90(29) (Typical) + 3% V

voltage for the I/O 2V, –3V
banks

VCCH_SDM SDM block transceiver — 0.975 1 1.025 V

supply voltage sense

VCCPT (30) Power supply for I/O, — 1.746 1.8 1.854 V

DTS, SDM, and
system PLL

VCCRCORE Power supply for — 1.14 1.2 1.26 V

programmable power
technology

VCCBAT Battery back-up power — 1 1 – 1.80 1.8 V

supply (for design
security volatile key
register)
continued...

(27) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(28) The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.
(29) The typical value is based on the SmartVID programmed value.
(30) Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other
rails.

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Symbol Description Condition Minimum(27) Typical Maximum(27) Unit

IBAT Battery back-up power VCCBAT = 1.2 V — — 200 nA

supply (for design
security volatile key
register)

VCCIO_PIO_SDM (31) SDM block I/O supply 1.2 V 1.164 1.2 1.236 V
voltage sense of bank
3A

VCC_IO_SDM I/O digital supply SmartVID(28): –1V, – (Typical) – 3% 0.70 – 0.90(29) (Typical) + 3% V
voltage sense in SDM 2V, –3V
block

VCCIO_SDM SDM block — 1.71 1.8 1.89 V

configuration pins
power supply

VCCL_ADC_SDM Periphery digital SmartVID(28): –1V, – (Typical) – 3% 0.70 – 0.90(29) (Typical) + 3% V

supply voltage sense 2V, –3V
to ADC, senses HPS
digital supply on HPS
devices, core supply
on non-HPS devices

VCCL_SDM SDM digital power — 0.776 0.8 0.824 V

supply

VCCPLLDIG_SDM SDM block PLL digital — 0.776 0.8 0.824 V

power supply

VCCPLL_SDM SDM block PLL analog — 1.71 1.8 1.89 V

power supply

VCCFUSEWR_SDM Fuse block writing — 1.71 1.8 1.89 V

power supply

VCCADC ADC voltage sensor — 1.71 1.8 1.89 V

power supply
continued...

(27) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(31) Must be supplied at 1.2 V when using Avalon® Streaming ×16 configuration schemes. For more information, please refer to the
Agilex™ 5 Device Family Pin Connection Guidelines.

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Symbol Description Condition Minimum(27) Typical Maximum(27) Unit

VCCIO_PIO HSIO bank power 1.0 V 0.95 1 1.05 V

supply
1.05 V(32) 1.0185 1.05 1.0815 V

1.1 V(32) 1.067 1.1 1.133 V

1.2 V(32) 1.164 1.2 1.236 V

1.3 V 1.261 1.3 1.339 V

VCCIO_HVIO HVIO bank power 3.3 V 3.201 3.3 3.399 V

supply
2.5 V 2.425 2.5 2.575 V

1.8 V 1.746 1.8 1.854 V

VCCPT_HVIO Supply voltage for 1.8 — 1.746 1.8 1.854 V

V I/O

VI (33) DC input voltage VCCIO_PIO = 1.0 V(34) –0.3000 — VCCIO_PIO + 0.25 V

VCCIO_PIO = 1.05 V(35) –0.3000 — VCCIO_PIO + 0.25 V

(34)

continued...

(27) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(32) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes:
• LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
• PHYLITE mode
• GPIO mode
(33) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the
maximum value.
(34) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3
V.
(35) Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.

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Symbol Description Condition Minimum(27) Typical Maximum(27) Unit

VCCIO_PIO = 1.1 V(35) –0.3000 — VCCIO_PIO + 0.25 V

(34)

VCCIO_PIO = 1.2 V(35) –0.3000 — VCCIO_PIO + 0.25 V

(34)

VCCIO_PIO = 1.3 V(35) –0.3000 — VCCIO_PIO + 0.25 V

(34)

VCCIO_SDM = 1.8 V –0.3000 — VCCIO_SDM + 0.3 V

VCCIO_HPS = 1.8 V –0.3000 — VCCIO_HPS + 0.3 V

VCCIO_HVIO = 1.8 V, 2.5 –0.3000 — VCCIO_HVIO + 0.3 V

V, 3.3 V

VO Output voltage VCCIO_PIO = 1.0 V, 1.05 0 — VCCIO_PIO V

V, 1.1 V, 1.2 V, 1.3 V

VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V

VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V

VCCIO_HVIO = 1.8 V, 2.5 0 — VCCIO_HVIO V

V, 3.3 V

TJ Operating junction Extended 0 — 100(36) °C

temperature
Industrial –40 — 100(36) °C

tRAMP (37) (38) Power supply ramp Standard POR 200 μs — 100 ms —
time

(27) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(36) When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device
lifetime of 11.4 years.
(37) tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to
both the ramp-up and ramp-down of the power rails.
(38) To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating
conditions.

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Table 13. E-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum(39) Typical Maximum(39) Unit

VCC Core voltage supply SmartVID(40) : –1V, – (Typical) – 3% 0.70 – 0.90(41) (Typical) + 3% V
2V, –2E, –3V

Fixed voltage: –4S 0.776 0.8 0.824 V

Fixed voltage: –5S 0.756 0.78 0.803 V

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCP Periphery supply SmartVID(40): –1V, – (Typical) – 3% 0.70 – 0.90(41) (Typical) + 3% V

voltage for the I/O 2V, –2E, –3V
banks
Fixed voltage: –4S 0.776 0.8 0.824 V

Fixed voltage: –5S 0.756 0.78 0.803 V

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCH_SDM SDM block transceiver SmartVID(40): –1V, – 0.776 0.8 0.824 V

supply voltage sense 2V, –2E, –3V

Without transceiver: – 0.776 0.8 0.824 V

4S

Without transceiver: – 0.756 0.78 0.803 V

5S
continued...

(39) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(40) The use of Power Management Bus (PMBus) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.
(41) The typical value is based on the SmartVID programmed value.

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Symbol Description Condition Minimum(39) Typical Maximum(39) Unit

Without transceiver: – 0.7275 0.75 0.7725 V

6S, –6X

With transceiver 0.975 1 1.025 V

VCCPT (42) Power supply for I/O, — 1.746 1.8 1.854 V

DTS, SDM, and
system PLL

VCCRCORE Power supply for — 1.14 1.2 1.26 V

programmable power
technology

VCCBAT Battery back-up power — 1 1 – 1.80 1.8 V

supply (for design
security volatile key
register)

IBAT Battery back-up power VCCBAT = 1.2 V — — 200 nA

supply (For design
security volatile key
register)

VCCIO_PIO_SDM (43) SDM block I/O supply 1.2 V 1.164 1.2 1.236 V
voltage sense of bank
3A

VCC_IO_SDM I/O digital supply SmartVID(40): –1V, – (Typical) – 3% 0.70 – 0.90(41) (Typical) + 3% V
voltage sense in SDM 2V, –2E, –3V
block
Fixed voltage: –4S 0.776 0.8 0.824 V

Fixed voltage: –5S 0.756 0.78 0.803 V

continued...

(39) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(42) Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other
rails.
(43) Must be supplied at 1.2 V when using Avalon Streaming ×16 configuration schemes. For more information, please refer to the Agilex
5 Device Family Pin Connection Guidelines.

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Symbol Description Condition Minimum(39) Typical Maximum(39) Unit

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCIO_SDM SDM block — 1.71 1.8 1.89 V

configuration pins
power supply

VCCL_ADC_SDM Periphery digital SmartVID(40): –1V, – (Typical) – 3% 0.70 – 0.90(41) (Typical) + 3% V

supply voltage sense 2V, –2E, –3V
to ADC, senses HPS
digital supply on HPS Fixed voltage: –4S 0.776 0.8 0.824 V
devices, core supply
on non-HPS devices Fixed voltage: –5S 0.756 0.78 0.803 V

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCL_SDM SDM digital power SmartVID(40): –1V, – 0.776 0.8 0.824 V

supply 2V, –2E, –3V

Fixed voltage: –4S 0.776 0.8 0.824 V

Fixed voltage: –5S 0.756 0.78 0.803 V

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCPLLDIG_SDM SDM block PLL digital SmartVID(40): –1V, – 0.776 0.8 0.824 V
power supply 2V, –2E, –3V

Fixed voltage: –4S 0.776 0.8 0.824 V

Fixed voltage: –5S 0.756 0.78 0.803 V

Fixed voltage: –6S, – 0.7275 0.75 0.7725 V

6X

VCCPLL_SDM SDM block PLL analog — 1.71 1.8 1.89 V

power supply

VCCFUSEWR_SDM Fuse block writing — 1.71 1.8 1.89 V

power supply
continued...

(39) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.

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Symbol Description Condition Minimum(39) Typical Maximum(39) Unit

VCCADC ADC voltage sensor — 1.71 1.8 1.89 V

power supply

VCCIO_PIO HSIO bank power 1.0 V 0.95 1 1.05 V

supply
1.05 V(44) 1.0185 1.05 1.0815 V

1.1 V(44) 1.067 1.1 1.133 V

1.2 V(44) 1.164 1.2 1.236 V

1.3 V 1.261 1.3 1.339 V

VCCIO_HVIO HVIO bank power 3.3 V 3.201 3.3 3.399 V

supply
2.5 V 2.425 2.5 2.575 V

1.8 V 1.746 1.8 1.854 V

VCCPT_HVIO Supply voltage for 1.8 — 1.746 1.8 1.854 V

V I/O

VI (45) DC input voltage VCCIO_PIO = 1.0 V(46) –0.3000 — VCCIO_PIO + 0.25 V

VCCIO_PIO = 1.05 V(47) –0.3000 — VCCIO_PIO + 0.25 V

(46)

continued...

(39) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(44) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes:
• LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
• PHYLITE mode
• GPIO mode
(45) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the
maximum value.
(46) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3
V.

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Symbol Description Condition Minimum(39) Typical Maximum(39) Unit

VCCIO_PIO = 1.1 V(47) –0.3000 — VCCIO_PIO + 0.25 V

(46)

VCCIO_PIO = 1.2 V(47) –0.3000 — VCCIO_PIO + 0.25 V

(46)

VCCIO_PIO = 1.3 V(47) –0.3000 — VCCIO_PIO + 0.25 V

(46)

VCCIO_SDM = 1.8 V –0.3000 — VCCIO_SDM + 0.3 V

VCCIO_HPS = 1.8 V –0.3000 — VCCIO_HPS + 0.3 V

VCCIO_HVIO = 1.8 V, 2.5 –0.3000 — VCCIO_HVIO + 0.3 V

V, 3.3 V

VO Output voltage VCCIO_PIO = 1.0 V, 1.05 0 — VCCIO_PIO V

V, 1.1 V, 1.2 V, 1.3 V

VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V

VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V

VCCIO_HVIO = 1.8 V, 2.5 0 — VCCIO_HVIO V

V, 3.3 V

TJ Operating junction Extended 0 — 100(48) °C

temperature
Industrial –40 — 100(48) °C

tRAMP (49) (50) Power supply ramp Standard POR 200 μs — 100 ms —
time

(39) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(47) Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
(48) When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device
lifetime of 11.4 years.
(49) tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to
both the ramp-up and ramp-down of the power rails.

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Related Information
I/O Standard Specifications on page 41

GTS Transceiver Power Supply Operating Conditions

Table 14. D-Series FPGAs GTS Transceiver Power Supply Operating Conditions
For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level Recommended Recommended Recommended Maximum (VR Unit
(V) VR Accuracy (% VR Ripple (% of AC Transient Accuracy +
of Typical DC Typical DC (% of Typical Ripple + AC
Level) Level) DC Level) Transient) (%
of Typical DC
Level)(51)

VCC_HSSI_[L1, R4] Transceiver, system PLL, and hard IP 0.8 ±0.5 ±2.5 ±3 V
digital power supply

VCCEHT_GTS[L1, R4] Transceiver PMA, transceiver PLL, 1.8 ±0.5 ±2.0 ±2.5 V
(52) and transceiver reference clock high
[A, B, C, D]
voltage analog power supply

VCCERT_GTS[L1, R4] Transceiver PMA and transceiver 1 ±0.5 ±2.0 ±2.5 V

[A, B, C, D] reference clock low voltage analog
power supply

(50) To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating
conditions.
(51) For scope measurement, 20 MHz bandwidth is sufficient. During measurement, put the ground pin as close to the power rail pin as
possible.
(52) HF noise requires AC 30 mVpp above 1 MHz.

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Table 15. E-Series FPGAs GTS Transceiver Power Supply Operating Conditions
For specification status, see the Data Sheet Status table

Symbol Description Speed Grade Typical DC Level Recommended Recommended Recommended Maximum (VR Unit
(V) VR Accuracy (% VR Ripple (% of AC Transient Accuracy +
of Typical DC Typical DC (% of Typical Ripple + AC
Level) level) DC level) Transient) (%
of Typical DC
Level)(53)

VCC_HSSI_[L1, R4] Transceiver, –6S, –6X 0.75 ±0.5 ±2.5 ±3 V

system PLL, and
hard IP digital –5S 0.78 ±0.5 ±2.5 ±3 V
power supply
–1V, –2V, –2E, – 0.8 ±0.5 ±2.5 ±3 V
3V, –4S

VCCEHT_GTS[L1,R4] Transceiver PMA, — 1.8 ±0.5 ±2.0 ±2.5 V

(54) transceiver PLL,
[A, B, C]
and transceiver
reference clock
high voltage
analog power
supply

VCCERT_GTS[L1, R4] Transceiver PMA — 1 ±0.5 ±2.0 ±2.5 V

[A, B, C] and transceiver
reference clock
low voltage
analog power
supply

(53) For scope measurement, 20 MHz bandwidth is sufficient. During measurement, put the ground pin as close to the power rail pin as
possible.
(54) HF noise requires AC 30 mVpp above 1 MHz.

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HPS Power Supply Operating Conditions

Table 16. D-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected
from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit

VCCL_HPS HPS DSU voltage and SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
periphery circuitry 3V(55)
power supply

VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
0 and core 1 power 3V(55)
rail

VCCL_HPS_CORE2 HPS Cortex*-A76 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
2 power rail 3V(55)

VCCL_HPS_CORE3 HPS Cortex*-A76 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
3 power rail 3V(55)

VCCPLLDIG1_HPS HPS PLL1 digital SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
power supply (can be 3V(55)
connected to VCCL_HPS)

VCCPLLDIG2_HPS HPS PLL2 digital SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
power supply (can be 3V(55)
connected to VCCL_HPS)

VCCPLL1_HPS HPS PLL1 analog 1.8 V 1.71 1.8 1.89 V

power supply

VCCPLL2_HPS HPS PLL2 analog 1.8 V 1.71 1.8 1.89 V

power supply

VCCIO_HPS HPS I/O buffers power 1.8 V 1.71 1.8 1.89 V

supply

(55) The use of Power Management Bus (PMBus) voltage regulator dedicated to the SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.

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Table 17. E-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected
from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit

VCCL_HPS HPS DSU voltage and SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
periphery circuitry 2E, –3V(56)
power supply
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
0 and core 1 power 2E, –3V(56)
rail
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCL_HPS_CORE2 HPS Cortex*-A76 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
2 power rail 2E, –3V(56)

Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCL_HPS_CORE3 HPS Cortex*-A76 core SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
3 power rail 2E, –3V(56)

Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

continued...

(56) The use of Power Management Bus (PMBus) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.

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Symbol Description Condition Minimum Typical Maximum Unit

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCPLLDIG1_HPS HPS PLL1 digital SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
power supply (can be 2E, –3V(56)
connected to VCCL_HPS)
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCPLLDIG2_HPS HPS PLL2 digital SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
power supply (can be 2E, –3V(56)
connected to VCCL_HPS)
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V

Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V

Fixed voltage: –6S, – (Typical) – 3% 0.75 (Typical) + 3% V

6X

VCCPLL1_HPS HPS PLL1 analog 1.8 V 1.71 1.8 1.89 V

power supply

VCCPLL2_HPS HPS PLL2 analog 1.8 V 1.71 1.8 1.89 V

power supply

VCCIO_HPS HPS I/O buffers power 1.8 V 1.71 1.8 1.89 V

supply

Related Information
• Recommended Operating Conditions on page 20
Provides the steady-state voltage values for the FPGA portion of the device.
• HPS Clock Performance on page 100

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DC Characteristics

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Intel FPGA Power and Thermal Calculator (PTC) and the Intel
Quartus® Prime Power Analyzer feature.

Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude
estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

HSIO DC Characteristics

HSIO I/O Pin Leakage Current

Table 18. HSIO I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Max Unit

II Input pin VI = 0 V to VCCIO_PIO (MAX) –360 360 µA

IOZ Tri-stated I/O pin VO = 0 V to VCCIO_PIO (MAX) –360 360 µA

HSIO OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to
the calibration block.

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Table 19. HSIO OCT Calibration Accuracy Specifications

Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

These specifications require RZQ reference accuracy of 240 Ω ±1%.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Calibration Accuracy Unit

34-Ω and 40-Ω RS (57) Internal series termination with SSTL-12, HSTL-12, HSUL-12, 20 %
calibration (34-Ω and 40-Ω and POD12 I/O standards
setting)

34-Ω and 40-Ω RS (57) Internal series termination with POD11 and LVSTL11 I/O 20 %
calibration (34-Ω and 40-Ω standards
setting)

34-Ω and 40-Ω RS (57) Internal series termination with LVSTL105 I/O standard 20 %
calibration (34-Ω and 40-Ω
setting)

40-Ω RS (57) Internal series termination with LVSTL700 I/O standard 20 %

calibration (40-Ω setting)

45-Ω RS Internal series termination with DPHY and SLVS400 I/O –20 to +25 %
calibration (45-Ω setting) standards

50-Ω and 60-Ω RT (57) Internal parallel termination with SSTL-12 and HSTL-12 I/O 20 %
calibration (50-Ω and 60-Ω standards
setting)

40-Ω, 50-Ω, and 60-Ω RT (57) Internal parallel termination with POD11 and POD12 I/O 20 %
calibration (40-Ω, 50-Ω, and 60- standards
Ω setting)
LVSTL11, LVSTL105, and 20 %
LVSTL700 I/O standards

100-Ω RD Internal differential termination DPHY and SLVS400 I/O –20 to +25 %
with calibration (100-Ω setting) standards

(57) This specification applies to both single-ended and pseudo-differential I/O buffers.

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HSIO OCT Without Calibration Resistance Tolerance Specifications

Table 20. HSIO OCT Without Calibration Resistance Tolerance Specifications

This table lists the GPIO OCT without calibration resistance tolerance to PVT changes.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Calibration Accuracy Unit

34-Ω and 40-Ω RS Internal series termination 1.3 V LVCMOS I/O standard 30 %
without calibration (34-Ω and
40-Ω setting)

34-Ω and 40-Ω RS (58) Internal series termination 1.2 V LVCMOS, SSTL-12, 25 %
without calibration (34-Ω and HSTL-12, HSUL-12, and POD12
40-Ω setting) I/O standards

34-Ω and 40-Ω RS (58) Internal series termination 1.1 V LVCMOS, POD11, and 25 %
without calibration (34-Ω and LVSTL11 I/O standards
40-Ω setting)

34-Ω and 40-Ω RS (58) Internal series termination 1.05 V LVCMOS and LVSTL105 25 %
without calibration (34-Ω and I/O standards
40-Ω setting)

34-Ω and 40-Ω RS Internal series termination 1.0 V LVCMOS I/O standard 30 %
without calibration (34-Ω and
40-Ω setting)

50-Ω RT (58) Internal parallel termination SSTL-12 and HSTL-12 I/O 25 %

without calibration (50-Ω standards
setting)
POD11 and POD12 I/O 25 %
standards

LVSTL11 and LVSTL105 I/O 25 %

standards

100-Ω RD (59) Internal differential termination True differential signaling I/O 40 %

(100-Ω setting) standard at VCCIO_PIO = 1.05
continued...

(58) This specification applies to both single-ended and pseudo-differential I/O buffers.
(59) This specification applies to VICM(DC) ≤ 1.3V. For VICM(DC) > 1.3V, a specification range of -60% to +40% applies.

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Symbol Description Condition (V) Calibration Accuracy Unit

True differential signaling I/O 40 %

standard at VCCIO_PIO = 1.1

True differential signaling I/O 40 %

standard at VCCIO_PIO = 1.2

True differential signaling I/O 40 %

standard at VCCIO_PIO = 1.3

HSIO Pin Capacitance

Table 21. HSIO Pin Capacitance

For specification status, see the Data Sheet Status table

Symbol Description Maximum Unit

CIO Input/output capacitance of I/O pins 2.6(60) pF

HSIO Internal Weak Pull-Up Resistor

All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O
standards.

Table 22. HSIO Internal Weak Pull-Up Resistor

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Min Typ Max Unit

RPU Value of the I/O pin VCCIO_PIO = 1.3 ±3% 3 10 30 kΩ

pull-up resistor before
and during VCCIO_PIO = 1.2 ±5% 3 10 30 kΩ
configuration, as well
as user mode if you VCCIO_PIO = 1.1 ±5% 3 10 30 kΩ
have enabled the
programmable pull-up VCCIO_PIO = 1.05 ±5% 3 10 30 kΩ
resistor option.
VCCIO_PIO = 1.0 ±5% 3 10 30 kΩ

(60) This value refers to die-level pin capacitance without the device package.

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HVIO DC Characteristics

HVIO I/O Pin Leakage Current

Table 23. HVIO I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Max Unit

II Input pin VI = 0 V to VCCIO_HVIO (MAX) -10 10 μA

IOZ Tri-stated I/O pin VI = 0 V to VCCIO_HVIO (MAX) -10 10 μA

HVIO Pin Capacitance

Table 24. HVIO Pin Capacitance

For specification status, see the Data Sheet Status table

Symbol Description Maximum Unit

CIO Input/output capacitance of I/O pins 4(61) pF

HVIO Internal Weak Pull-Up and Pull-Down Resistor

Only input and bidirectional pins in HVIO bank have an option to enable weak pull-up and pull-down when using LVCMOS I/O
standard.

Table 25. HVIO Internal Weak Pull-Up and Pull-Down Resistor Values
For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Min Typ Max Unit

20 kΩ RPU, 20 kΩ RPD Value of the I/O pin VCCIO_HVIO = 1.8, 2.5, 15 20 30 kΩ

pull-up and pull-down 3.3 ±3%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

(61) This value refers to die-level pin capacitance without the device package.

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HVIO Hysteresis Specifications for Schmitt Trigger Input

Table 26. HVIO Hysteresis Specifications for Schmitt Trigger Input

This device supports built-in Schmitt trigger input that always enabled on HVIO I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for
improved noise immunity, especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typ Max Unit

VHYS Hysteresis for Schmitt VCCIO_HVIO = 1.8 V — 200 — mV

trigger input
VCCIO_HVIO = 2.5 V — 250 — mV

VCCIO_HVIO = 3.3 V — 250 — mV

HPS and SDM I/O DC Characteristics

HPS and SDM I/O Pin Leakage Current

Table 27. HPS and SDM I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Max Unit

II Input pin VI = 0 V to VCCIO_HPS (MAX) −15 15 µA

VI = 0 V to VCCIO_SDM (MAX)

Tri-stated I/O pin VO = 0 V to VCCIO_HPS (MAX) −15 15 µA

VO = 0 V to VCCIO_SDM (MAX)

HPS and SDM I/O Pin Capacitance

Table 28. HPS and SDM I/O Pin Capacitance

For specification status, see the Data Sheet Status table

Symbol Description Maximum Unit

CIO Input/output capacitance of I/O pins 5(62) pF

(62) This value refers to die-level pin capacitance without the device package.

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HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor

The I/O pins in SDM and HPS bank are supported with weak pull-up and weak pull-down options. For SDM I/O pins, the weak
pull-up and weak pull-down features are pre-configured according to the configuration mode.

Table 29. HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor
For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Min Typ Max Unit

20 kΩ RPU, 20 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 15 20 25 kΩ

pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

50 kΩ RPU, 50 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 37.5 50 62.5 kΩ
pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

80 kΩ RPU, 80 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 60 80 100 kΩ
pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

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HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input

Table 30. HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input

This device supports Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity,
especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typ Max Unit

VHYS Hysteresis for Schmitt VCCIO_HPS = 1.8 V 180 − − mV

trigger input

I/O Standard Specifications

HSIO I/O Standard Specifications

Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive
characteristics (IOH and IOL) for various I/O standards.

For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO
values.

You must perform timing closure analysis to determine the maximum achievable frequency for general-purpose I/O
standards.

Related Information
Recommended Operating Conditions on page 20

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HSIO Single-Ended I/O Standards Specifications

Table 31. HSIO Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VIL (V) VIH (V) VOL (V)(63) VOH (V)(63)

Min Typ Max Min Max Min Max(64) Max Min

1.3 V LVCMOS 1.261 1.3 1.339 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.25 × 0.75 ×
VCCIO_PIO VCCIO_PIO 0.25 VCCIO_PIO VCCIO_PIO

1.2 V LVCMOS 1.14 1.2 1.26 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.25 × 0.75 ×
VCCIO_PIO VCCIO_PIO 0.25 VCCIO_PIO VCCIO_PIO

1.1 V LVCMOS 1.045 1.1 1.155 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.25 × 0.75 ×
VCCIO_PIO VCCIO_PIO 0.25 VCCIO_PIO VCCIO_PIO

1.05 V 0.9975 1.05 1.1025 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.25 × 0.75 ×
LVCMOS VCCIO_PIO VCCIO_PIO 0.25 VCCIO_PIO VCCIO_PIO

1.0 V LVCMOS 0.95 1 1.05 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.25 × 0.75 ×
VCCIO_PIO VCCIO_PIO 0.25 VCCIO_PIO VCCIO_PIO

HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications

Table 32. HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications
For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) Internal VREF (V) VTT (V)

Min Typ Max Min Typ Max Min Typ Max

SSTL-12 1.14 1.2 1.26 0.49 × 0.5 × VCCIO_PIO 0.51 × 0.45 × 0.5 × VCCIO_PIO 0.55 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO

HSTL-12 1.14 1.2 1.26 0.47 × 0.5 × VCCIO_PIO 0.53 × 0.45 × 0.5 × VCCIO_PIO 0.55 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
continued...

(63) Applicable to test condition of IOH and IOL at 2 mA.

(64) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VIH(max) for the LVCMOS input can go up to VCCIO_PIO +
0.3 V.

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I/O Standard VCCIO_PIO (V) Internal VREF (V) VTT (V)

Min Typ Max Min Typ Max Min Typ Max

HSUL-12(65) 1.14 1.2 1.26 0.49 × 0.5 × VCCIO_PIO 0.51 × 0.45 × 0.5 × VCCIO_PIO 0.55 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO

POD12(66) 1.164 1.2 1.236 0.69 × 0.7 × VCCIO_PIO 0.71 × — VCCIO_PIO —

VCCIO_PIO VCCIO_PIO

POD11(66) 1.067 1.1 1.133 0.69 × 0.7 × VCCIO_PIO 0.71 × — VCCIO_PIO —

VCCIO_PIO VCCIO_PIO

LVSTL11(66) 1.067 1.1 1.133 0.24 × 0.25 × 0.26 × — GND —

VCCIO_PIO VCCIO_PIO VCCIO_PIO

LVSTL105(66) 1.0185 1.05 1.0815 0.24 × 0.25 × 0.26 × — GND —

VCCIO_PIO VCCIO_PIO VCCIO_PIO

LVSTL700 1.0185 1.05 1.0815 0.24 × 0.25 × 0.26 × — GND —

VCCIO_PIO VCCIO_PIO VCCIO_PIO

HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

Table 33. HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
For specification status, see the Data Sheet Status table

I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)

Max Min Max Min

SSTL-12 VREF – 0.075 VREF + 0.075 VREF – 0.100 VREF + 0.100

HSTL-12 VREF – 0.080 VREF + 0.080 VREF – 0.150 VREF + 0.150

continued...

(65) Usage of receiver termination is optional.

(66) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
• PHYLITE mode
• GPIO mode

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I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)

Max Min Max Min

HSUL-12 VREF – 0.100 VREF + 0.100 VREF – 0.135 VREF + 0.135

POD12 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

POD11 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

Note: For output voltage swing calculation example, refer to the General-Purpose I/O User Guide for this device. Differential voltage
referenced I/O standard uses two single-ended outputs with second output programmed as inverted.

Related Information
General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

HSIO Single-Ended LVSTL I/O Standards Specifications

Table 34. HSIO Single-Ended LVSTL I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)

Min Typ Max Max Min Max Min

LVSTL11(67) 1.067 1.1 1.133 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

LVSTL105(67) 1.0185 1.05 1.0815 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

LVSTL700 1.0185 1.05 1.0815 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

Note: For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential,
PDN) User Guide: Agilex™ 5 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines
(HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs takes precedence over specifications in
HSIO Single-Ended LVSTL I/O Standards Specifications table.

(67) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
• PHYLITE mode
• GPIO mode

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Related Information
PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications

Table 35. HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
For specification status, see the Data Sheet Status table

I/O VCCIO_PIO (V) VILdiff(DC) VIHdiff(DC) VILdiff(AC) VIHdiff(AC) VIX(AC) (V) VOX(AC) (V)
Standard (V) (V) (V) (V)

Min Typ Max Max Min Max Min Min Typ Max Min Typ Max

SSTL-12(6 1.14 1.2 1.26 –0.15 0.15 –0.2 0.2 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
8) VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

HSTL-12(6 1.14 1.2 1.26 –0.16 0.16 –0.3 0.3 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
8) VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

HSUL-12( 1.14 1.2 1.26 –0.2 0.2 –0.27 0.27 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
68) VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

(68) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
• PHYLITE mode
• GPIO mode

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HSIO Differential POD I/O Standards Specifications

Table 36. HSIO Differential POD I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)(69)

Min Typ Max Max Min Max Min Max

POD12(70) 1.164 1.2 1.236 –0.11 0.11 –0.14 0.14 25

POD11(70) 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25

HSIO Differential LVSTL I/O Standards Specifications

Table 37. HSIO Differential LVSTL I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)(71)

Min Typ Max Max Min Max Min Max

LVSTL11(72) 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25

LVSTL105(72) 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25

LVSTL700 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25

(69) Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
(70) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
• PHYLITE mode
• GPIO mode
(71) Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
(72) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-
bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
• PHYLITE mode
• GPIO mode

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Note: For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential,
PDN) User Guide: Agilex™ 5 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines
(HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs takes precedence over specifications in
HSIO Differential LVSTL I/O Standards Specifications table.

Related Information
PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs

HSIO Differential I/O Standards Specifications

Table 38. HSIO Differential I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (mV)(73) (74) VOCM (V)(73)
Standard
Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max

True 1.261 1.3 1.339 100 454 0.5 — 1.375(76) 247 — 454 0.9 1 1.1
Differenti
al
Signaling
-1.3 V
(Transmi
tter and
Receiver)
(75)

True 1.14 1.2 1.26 100 454 0.8 — 0.95 — — — — — —

Differenti
al
Signaling
continued...

(73) RL range: 90 ≤ RL ≤ 110 Ω.

(74) The specification is only applicable to default VOD and pre-emphasis setting.
(75) The True Differential Signaling input buffer is supported on 1.05 V, 1.1 V, 1.2 V, and 1.3 V VCCIO_PIO banks. The maximum input
voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
(76) The VICM(DC) voltage must not exceed 1.2 V when on-chip differential termination (RD OCT) is disabled with the use of external on-
board termination.

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I/O VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (mV)(73) (74) VOCM (V)(73)
Standard
Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max

-1.2 V
(Receiver
only)(75)

True 1.045 1.1 1.155 100 454 0.8 — 0.95 — — — — — —

Differenti
al
Signaling
-1.1 V
(Receiver
only)(75)

True 0.9975 1.05 1.1025 100 454 0.8 — 0.95 — — — — — —

Differenti
al
Signaling
-1.05 V
(Receiver
only)(75)

SLVS400 1.164 1.2 1.236 70 — 0.07 0.2 0.33 140 200 270 0.15 0.2 0.25

1.067 1.1 1.133

MIPI D-PHY I/O Standards Specifications

Table 39. D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications
For specification status, see the Data Sheet Status table

I/O Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standard
Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

DPHY Applicabl 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
e for low
power
when the
continued...

(73) RL range: 90 ≤ RL ≤ 110 Ω.

(74) The specification is only applicable to default VOD and pre-emphasis setting.

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I/O Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standard
Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

supporte
d High
Speed
data rate
≤ 1.5
Gbps

Applicabl 0.95 — 1.3

e for low
power
when the
supporte
d High
Speed
data rate
> 1.5
Gbps to
3.5 Gbps

Applicabl 1.067 1.1 1.133 1 1.1 1.2

e for low
power
when the
supporte
d High
Speed
data rate
≤ 1.5
Gbps

Applicabl 0.85 — 1.2

e for low
power
when the
supporte
d High
Speed
data rate
> 1.5
Gbps to
3.5 Gbps

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Table 40. D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications
For specification status, see the Data Sheet Status table

I/O Conditi VCCIO_PIO (V) VID (V) VICM(DC) (V) VOD(DC) (V) VOCM (V) VILHS VIHHS
Standa on (V) (V)
rd
Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max Min Max

DPHY Data 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
Gbps
to 3.5
Gbps

Data 1.067 1.1 1.133 0.07

rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
Gbps
to 3.5
Gbps

Table 41. E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications
For specification status, see the Data Sheet Status table

I/O Device Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standar Group
d Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

DPHY A Applicab 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
le for
low
power
when
the
support
ed High
continued...

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I/O Device Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standar Group
d Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

Speed
data
rate ≤
1.5
Gbps

Applicab 0.95 — 1.3

le for
low
power
when
the
support
ed High
Speed
data
rate >
1.5
Gbps to
3.5
Gbps

Applicab 1.067 1.1 1.133 1 1.1 1.2

le for
low
power
when
the
support
ed High
Speed
data
rate ≤
1.5
Gbps

Applicab 0.85 — 1.2

le for
low
power
when
the
support
ed High
continued...

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I/O Device Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standar Group
d Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

Speed
data
rate >
1.5
Gbps to
3.5
Gbps

B Applicab 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
le for
low
power
when
the
support
ed High
Speed
data
rate ≤
1.5
Gbps

Applicab 0.95 — 1.3

le for
low
power
when
the
support
ed High
Speed
data
rate >
1.5
Gbps to
2.5
Gbps

Applicab 1.067 1.1 1.133 1 1.1 1.2

le for
low
power
when
the
continued...

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I/O Device Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Standar Group
d Min Typ Max Min Max Min Max Min Typ Max Min Typ Max

support
ed High
Speed
data
rate ≤
1.5
Gbps

Applicab 0.85 — 1.2

le for
low
power
when
the
support
ed High
Speed
data
rate >
1.5
Gbps to
2.5
Gbps

Table 42. E-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications
For specification status, see the Data Sheet Status table

I/O Condition VCCIO_PIO (V) VID (V) VICM(DC) (V) VOD(DC) (V) VOCM (V) VILHS VIHHS
Standa (V) (V)
rd
Device Data Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max Min Max
Group Rate

DPHY A Data 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
continued...

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I/O Condition VCCIO_PIO (V) VID (V) VICM(DC) (V) VOD(DC) (V) VOCM (V) VILHS VIHHS
Standa (V) (V)
rd
Device Data Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max Min Max
Group Rate

Gbps
to 3.5
Gbps

Data 1.067 1.1 1.133 0.07

rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
Gbps
to 3.5
Gbps

B Data 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
Gbps
to 2.5
Gbps

Data 1.067 1.1 1.133 0.07

rate ≤
1.5
Gbps

Data 0.04
rate >
1.5
Gbps
to 2.5
Gbps

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HVIO I/O Standard Specifications

Related Information
Recommended Operating Conditions on page 20

HVIO Single-Ended I/O Standards Specifications

Table 43. HVIO Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_HVIO (V) VIL (V) VIH (V) VOL (V)(77) VOH (V)(77)

Min Typ Max Min Max Min Max Max Min

1.8 V LVCMOS 1.746 1.8 1.854 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO – 0.45
1.8 V LVTTL

2.5 V LVCMOS 2.425 2.5 2.575 — 0.7 1.7 — 0.4 2

2.5 V LVTTL

3.3 V LVCMOS 3.201 3.3 3.399 — 0.8 2 — 0.4 2.4

3.3 V LVTTL

HPS and SDM I/O Standard Specifications

Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive
characteristics (IOH and IOL) for various I/O standards.

For minimum voltage values, use the minimum VCCIO_HPS or VCCIO_SDM values. For maximum voltage values, use the
maximum VCCIO_HPS or VCCIO_SDM values.

You must perform timing closure analysis to determine the maximum achievable frequency for general-purpose I/O
standards.

(77) Applicable to test condition of IOH and IOL at 3 mA.

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Related Information
Recommended Operating Conditions on page 20

HPS and SDM Single-Ended I/O Standards Specifications

Table 44. HPS and SDM Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

I/O VCCIO_HPS, VCCIO_SDM (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL IOH
Standard (mA)(78) (mA)(78)

Min Typ Max Min Max Min Max Max Min Max Min

1.8 V 1.71 1.8 1.89 –0.3 0.35 × 0.65 × VCCIO_HPS + 0.4 VCCIO_HPS – 8 –8
LVCMOS VCCIO_HPS, VCCIO_HPS, 0.3, 0.4,
0.35 × 0.65 × VCCIO_SDM + VCCIO_SDM –
VCCIO_SDM VCCIO_SDM 0.3 0.4

Switching Characteristics
This section provides the performance characteristics of core and periphery blocks.

Core Performance Specifications

Clock Tree Specifications

Table 45. D-Series FPGAs Clock Tree Performance Specifications

For specification status, see the Data Sheet Status table

Parameter Performance Unit

–1V, –2V –3V

Programmable clock routing 1,000 780 MHz

(78) To meet the IOH and IOL specifications, you must set the current strength settings accordingly. For example, to meet the 1.8 V
LVCMOS specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet
the IOH and IOL specifications in the data sheet.

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Table 46. E-Series FPGAs Clock Tree Performance Specifications

For specification status, see the Data Sheet Status table

Parameter Performance Unit

–1V, –2V, –2E –3V –4S –5S –6S, –6X

Programmable clock 1,000 780 850 710 554 MHz

routing

I/O PLL Specifications

Table 47. D-Series FPGAs I/O PLL Specifications

For specification status, see the Data Sheet Status table

Symbol Parameter Condition Min Typ Max Unit

fIN Input clock frequency –1V 10 — 1,100(79) MHz

source from core clock
input and reference –2V 10 — 1,000(79) MHz
clock input
–3V 10 — 780(79) MHz

Input clock frequency –1V 10 — 800(79) MHz

source from I/O clock
input –2V 10 — 717(79) MHz

–3V 10 — 625(79) MHz

fINPFD Input clock frequency — 10 — 325 MHz

to the PFD

fVCO I/O PLL VCO operating –1V 600 — 3,200 MHz

range
–2V 600 — 3,200 MHz

–3V 600 — 2,400 MHz

fCLBW I/O PLL closed-loop — 0.5 — 20 MHz

bandwidth
continued...

(79) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

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Symbol Parameter Condition Min Typ Max Unit

fOUT Output frequency for –1V — — 1,100 MHz

internal clock (C
counter) –2V — — 1,000 MHz

–3V — — 780 MHz

fOUT_EXT Output frequency for –1V — — 800 MHz

external clock output
–2V — — 717 MHz

–3V — — 625 MHz

tOUTDUTY Duty cycle for fOUT_EXT < 300 MHz 45 50 55 %

dedicated external
fOUT_EXT ≥ 300 MHz 40/45 (80) 50 55 (80)/60 %
clock output (when set
to 50%)

tFCOMP (81) External feedback — — — 5 ns

clock compensation
time

fDYCONFIGCLK Dynamic configuration — — — 100 MHz

clock for mgmt_clk

tLOCK Time required to lock — — — 1 ms

from end-of-device
configuration or
deassertion of areset

tDLOCK Time required to lock — — — 1 ms

dynamically (after
switchover or
reconfiguring any non-
post-scale counters/
delays)

tPLL_PSERR (82) Accuracy of PLL phase — — — ±50 ps

shift
continued...

(80)
To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to
the Clocking and PLL User Guide for the detail design guidelines.
(81) Not applicable for fabric-feeding I/O PLL.
(82) PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.

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Symbol Parameter Condition Min Typ Max Unit

tARESET Minimum pulse width — 10 — — ns

on the areset signal

tINCCJ Input clock cycle-to- fREF < 100 MHz (83) — — ±750 ps (p-p)
cycle jitter
fREF ≥ 100 MHz (83) — — 0.15 UI (p-p)

tREFPJ Reference phase jitter Carrier frequency: 100 — — 1.42 ps

(rms)(84) MHz with integrated
bandwidth of 10 kHz
to 50 MHz

tREFPN Reference phase 10 Hz — — –90 dBc/Hz

noise(85) (84)
100 Hz — — –100 dBc/Hz

1 kHz — — –110 dBc/Hz

10 kHz — — –120 dBc/Hz

100 kHz — — –130 dBc/Hz

1 MHz — — –138 dBc/Hz

10 MHz — — –142 dBc/Hz

100 MHz — — –144 dBc/Hz

tOUTPJ_DC (81) (86) Period jitter for fOUT < 100 MHz (83) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (83) — — 175 ps (p-p)
continued...

(83) fREF is fIN/N, specification applies when N = 1.

(84) Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
(85) The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz.
To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase
noise at 100 MHz + (20 × log10 (f/100)).
(86) This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend
on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock
profile.

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Symbol Parameter Condition Min Typ Max Unit

tOUTCCJ_DC (81) (86) Cycle-to-cycle jitter fOUT < 100 MHz (83) — — 17.5 mUI (p-p)
for dedicated clock
fOUT ≥ 100 MHz (83) — — 175 ps (p-p)
output

tOUTPJ_IO (87) (86) Period jitter for clock fOUT < 100 MHz (83) — — 60 mUI (p-p)
output on the regular
fOUT ≥ 100 MHz (83) — — 600 ps (p-p)
I/O

tOUTCCJ_IO (87) (86) Cycle-to-cycle jitter fOUT < 100 MHz (83) — — 60 mUI (p-p)
for clock output on the
fOUT ≥ 100 MHz (83) — — 600 ps (p-p)
regular I/O

tCASC_OUTPJ_DC (81) Period jitter for fOUT < 100 MHz (83) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (83) — — 175 ps (p-p)
in cascaded PLLs

Table 48. E-Series FPGAs I/O PLL Specifications

For specification status, see the Data Sheet Status table

Symbol Parameter Condition Min Typ Max Unit

fIN Input clock frequency –1V, –4S 10 — 1,100(88) MHz

source from core clock
input and reference –2V, –2E, –5S 10 — 1,000(88) MHz
clock input
–3V, –6S, –6X 10 — 780(88) MHz

Input clock frequency –1V, –4S 10 — 800(88) MHz

source from I/O clock
input –2V, –2E, –5S 10 — 717(88) MHz

–3V, –6S, –6X 10 — 625(88) MHz

fINPFD Input clock frequency — 10 — 325 MHz

to the PFD
continued...

(87) External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory
Output clock Jitter Specifications table.
(88) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

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Symbol Parameter Condition Min Typ Max Unit

fVCO I/O PLL VCO operating –1V, –4S 600 — 3,200 MHz
range
–2V, –2E, –5S 600 — 3,200 MHz

–3V, –6S, –6X 600 — 2,400 MHz

fCLBW I/O PLL closed-loop — 0.5 — 20 MHz

bandwidth

fOUT Output frequency for –1V,–4S — — 1,100 MHz

internal clock (C
counter) –2V, –2E, –5S — — 1,000 MHz

–3V, –6S, –6X — — 780 MHz

fOUT_EXT Output frequency for –1V, –4S — — 800 MHz

external clock output
–2V, –2E, –5S — — 717 MHz

–3V, –6S, –6X — — 625 MHz

tOUTDUTY Duty cycle for fOUT_EXT < 300 MHz 45 50 55 %

dedicated external
fOUT_EXT ≥ 300 MHz 40/45 (89) 50 55 (89)/60 %
clock output (when set
to 50%)

tFCOMP (90) External feedback — — — 5 ns

clock compensation
time

fDYCONFIGCLK Dynamic configuration — — — 100 MHz

clock for mgmt_clk

tLOCK Time required to lock — — — 1 ms

from end-of-device
configuration or
deassertion of areset
continued...

(89)
To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to
the Clocking and PLL User Guide for the detail design guidelines.
(90) Not applicable for fabric-feeding I/O PLL.

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Symbol Parameter Condition Min Typ Max Unit

tDLOCK Time required to lock — — — 1 ms

dynamically (after
switchover or
reconfiguring any non-
post-scale counters/
delays)

tPLL_PSERR (91) Accuracy of PLL phase — — — ±50 ps

shift

tARESET Minimum pulse width — 10 — — ns

on the areset signal

tINCCJ Input clock cycle-to- fREF < 100 MHz (92) — — ±750 ps (p-p)
cycle jitter
fREF ≥ 100 MHz (92) — — 0.15 UI (p-p)

tREFPJ Reference phase jitter Carrier frequency: 100 — — 1.42 ps

(rms)(93) MHz with integrated
bandwidth of 10 kHz
to 50 MHz

tREFPN Reference phase 10 Hz — — –90 dBc/Hz

noise(94) (93)
100 Hz — — –100 dBc/Hz

1 kHz — — –110 dBc/Hz

10 kHz — — –120 dBc/Hz

100 kHz — — –130 dBc/Hz

1 MHz — — –138 dBc/Hz

continued...

(91) PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
(92) fREF is fIN/N, specification applies when N = 1.
(93) Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
(94) The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz.
To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase
noise at 100 MHz + (20 × log10 (f/100)).

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Symbol Parameter Condition Min Typ Max Unit

10 MHz — — –142 dBc/Hz

100 MHz — — –144 dBc/Hz

tOUTPJ_DC (90) (95) Period jitter for fOUT < 100 MHz (92) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (92) — — 175 ps (p-p)

tOUTCCJ_DC (90) (95) Cycle-to-cycle jitter fOUT < 100 MHz (92) — — 17.5 mUI (p-p)
for dedicated clock
fOUT ≥ 100 MHz (92) — — 175 ps (p-p)
output

tOUTPJ_IO (96) (95) Period jitter for clock fOUT < 100 MHz (92) — — 60 mUI (p-p)
output on the regular
fOUT ≥ 100 MHz (92) — — 600 ps (p-p)
I/O

tOUTCCJ_IO (96) (95) Cycle-to-cycle jitter fOUT < 100 MHz (92) — — 60 mUI (p-p)
for clock output on the
fOUT ≥ 100 MHz (92) — — 600 ps (p-p)
regular I/O

tCASC_OUTPJ_DC (90) Period jitter for fOUT < 100 MHz (92) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (92) — — 175 ps (p-p)
in cascaded PLLs

Related Information
Memory Output Clock Jitter Specifications on page 87
Provides more information about the external memory interface clock output jitter specifications.

(95) This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend
on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock
profile.
(96) External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory
Output clock Jitter Specifications table.

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DSP Block Specifications

Table 49. D-Series FPGAs DSP Block Performance Specifications for Single DSP Block
For specification status, see the Data Sheet Status table

Mode Performance Unit

–1V –2V –3V

Fixed-point 18 × 19 768 655 574 MHz

multiplication mode

Fixed-point 27 × 27 768 655 574 MHz

multiplication mode

Fixed-point 18 × 19 multiplier 768 655 574 MHz

adder mode

Fixed-point 18 × 19 multiplier 768 655 574 MHz

adder summed with 36-bit input
mode

Fixed-point six 9 × 9 multiplier 768 655 574 MHz

adder mode

FP32 floating-point 637 492 431 MHz

multiplication mode

FP32 floating-point adder or 637 492 431 MHz

subtract mode

FP32 floating-point multiplier 637 492 431 MHz

adder or subtract mode

FP32 floating-point multiplier 637 492 431 MHz

accumulate mode

Addition or subtraction of two 637 492 431 MHz

FP16 floating-point
multiplication mode

Sum/sub of two FP16 637 492 431 MHz

multiplications with FP32
(addition/subtraction)

Sum/sub of two FP16 637 492 431 MHz

multiplications with
accumulation (addition/
subtraction)
continued...

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Mode Performance Unit

–1V –2V –3V

Tensor floating-point mode 637 492 431 MHz

Tensor accumulation mode: fp32 637 492 431 MHz

Tensor fixed-point mode 768 655 574 MHz

INT16 complex multiplication 768 655 574 MHz

mode

Table 50. D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks
For specification status, see the Data Sheet Status table

Mode Performance Unit

–1V –2V –3V

Fixed-point 18 x 19 complex 768 655 574 MHz

multiplication mode

Fixed-point 18 × 19 FIR systolic 768 655 574 MHz

mode

Fixed-point 27 × 27 576 492 431 MHz

multiplication mode

Fixed-point 9 × 9 multiplication 576 492 431 MHz

mode

FP32 floating-point complex 637 492 431 MHz

multiplication

FP32 floating-point vector dot 637 492 431 MHz

product

FP16 floating-point complex 637 492 431 MHz

multiplication

FP16 floating-point vector dot 637 492 431 MHz

product

Tensor floating-point cascade 637 492 431 MHz

chain

Tensor fixed-point cascade chain 768 655 574 MHz

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Table 51. E-Series FPGAs DSP Block Performance Specifications for Single DSP Block
For specification status, see the Data Sheet Status table

Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

Fixed-point 18 × 768 655 574 558 489 408 MHz

19 multiplication
mode

Fixed-point 27 × 768 655 574 558 489 408 MHz

27 multiplication
mode

Fixed-point 18 × 768 655 574 558 489 408 MHz

19 multiplier adder
mode

Fixed-point 18 × 768 655 574 558 489 408 MHz

19 multiplier adder
summed with 36-
bit input mode

Fixed-point six 9 × 768 655 574 558 489 408 MHz

9 multiplier adder
mode

FP32 floating-point 637 492 431 418 367 306 MHz

multiplication mode

FP32 floating-point 637 492 431 418 367 306 MHz

adder or subtract
mode

FP32 floating-point 637 492 431 418 367 306 MHz

multiplier adder or
subtract mode

FP32 floating-point 637 492 431 418 367 306 MHz

multiplier
accumulate mode

Addition or 637 492 431 418 367 306 MHz

subtraction of two
FP16 floating-point
multiplication mode
continued...

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Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

Sum/sub of two 637 492 431 418 367 306 MHz

FP16
multiplications with
FP32 (addition/
subtraction)

Sum/sub of two 637 492 431 418 367 306 MHz

FP16
multiplications with
accumulation
(addition/
subtraction)

Tensor floating- 637 492 431 418 367 306 MHz

point mode

Tensor 637 492 431 418 367 306 MHz

accumulation
mode: fp32

Tensor fixed-point 768 655 574 558 489 408 MHz

mode

INT16 complex 768 655 574 558 489 408 MHz

multiplication mode

Table 52. E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks
For specification status, see the Data Sheet Status table

Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

Fixed-point 18 x 19 768 655 574 558 489 408 MHz

complex
multiplication mode

Fixed-point 18 × 768 655 574 558 489 408 MHz

19 FIR systolic
mode

Fixed-point 27 × 576 492 431 418 367 306 MHz

27 multiplication
mode
continued...

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Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

Fixed-point 9 × 9 576 492 431 418 367 306 MHz

multiplication mode

FP32 floating-point 637 492 431 418 367 306 MHz

complex
multiplication

FP32 floating-point 637 492 431 418 367 306 MHz

vector dot product

FP16 floating-point 637 492 431 418 367 306 MHz

complex
multiplication

FP16 floating-point 637 492 431 418 367 306 MHz

vector dot product

Tensor floating- 637 492 431 418 367 306 MHz

point cascade chain

Tensor fixed-point 768 655 574 558 489 408 MHz

cascade chain

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block
clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 53. D-Series FPGAs Memory Block Performance Specifications

For specification status, see the Data Sheet Status table

Memory Mode Performance Unit

–1V –2V –3V

MLAB Single-port RAM/ROM 1,000 782 667 MHz

continued...

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Memory Mode Performance Unit

–1V –2V –3V

Simple dual-port RAM

Simple dual-port RAM with 630 510 460 MHz

read-during-write option
set to New Data or Old
Data

M20K block(97) Single-port RAM/ROM 1,000 782 667 MHz

Simple dual-port RAM

Simple dual-port RAM, 1,000 782 667 MHz

coherent read enabled

Single-port RAM with the 800 640 560 MHz

read-during-write option
set to Old Data
Simple dual-port RAM with
the read-during-write
option set to Old Data

Simple dual-port RAM with 600 480 420 MHz

ECC enabled, 512 × 32

Simple dual-port RAM with 1,000 782 667 MHz

ECC, optional pipeline
registers enabled, 512 ×
32

Dual-port ROM 600 500 420 MHz

True dual-port RAM

Simple quad-port RAM 600 500 420 MHz

(97) For the M20K block, Quartus automatically optimizes timing and power based on design requirements.

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Table 54. E-Series FPGAs Memory Block Performance Specifications

For specification status, see the Data Sheet Status table

Memory Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

MLAB Single-port 850 750 510 600 469 400 MHz

RAM/ROM
Simple dual-port
RAM

Simple dual-port 530 450 380 400 310 280 MHz

RAM with read-
during-write
option set to
New Data or Old
Data

M20K block(98) Single-port 1,000 782 667 700 550 465 MHz
RAM/ROM
Simple dual-port
RAM

Simple dual-port 1,000 782 667 700 550 465 MHz

RAM, coherent
read enabled

Single-port RAM 800 640 560 560 440 370 MHz

with the read-
during-write
option set to Old
Data
Simple dual-port
RAM with the
read-during-
write option set
to Old Data

Simple dual-port 600 480 420 420 330 280 MHz

RAM with ECC
enabled, 512 ×
32
continued...

(98) For the M20K block, Quartus automatically optimizes timing and power based on design requirements.

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Memory Mode Performance Unit

–1V –2V, –2E –3V –4S –5S –6S, –6X

Simple dual-port 1,000 782 667 700 550 465 MHz

RAM with ECC,
optional pipeline
registers
enabled, 512 ×
32

Dual-port ROM 600 500 420 445 335 280 MHz

True dual-port
RAM

Simple quad- 600 500 420 445 335 280 MHz

port RAM

Local Temperature Sensor Specifications

Table 55. Local Temperature Sensor Specifications

For specification status, see the Data Sheet Status table

Description Temperature Range Accuracy Sampling Rate(99) Conversion Time

Local temperature sensor –40 to 125°C(100) ±5°C 1 KSPS < 1 ms

Related Information
Recommended Operating Conditions on page 20

Remote Temperature Diode Specifications

Note the following for the remote temperature diode specifications:

• The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation.
The characteristics can also apply to two-currents temperature sensing chip implementation.
• Absolute accuracy is dependent on third-party external diode ADC and integration specifics.

(99) The read out is subject to the SDM mailbox activity status.
(100) Temperature range refers to junction temperature.

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Table 56. Remote Temperature Diode Specifications (Core Fabric TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 30 — 170 μA

Vbias, voltage across diode 0.51 — 0.82 V

Series resistance — — <5 Ω

Diode ideality factor — 1.005(101) — —

Voltage Sensor Specifications

Table 57. Voltage Sensor Specifications

For specification status, see the Data Sheet Status table

Parameter Minimum Typical Maximum Unit

Resolution — 7 — Bit

Sampling rate(102) — — 1 KSPS

Input capacitance — — 40 pF

External reference voltage 1.125 1.25 1.375 V

Voltage sensor accuracy, Vin range: 0 V to 1.1 V(103) — — ±3.5 %

(104)

continued...

(101) When using lower injection current (two-currents) implementation, the ideality factor is 1.014.
(102) The read out is subject to the SDM mailbox activity status.
(103) For low voltage channels in channels 0, 1, 2, 6, and 7, the ±3.5% accuracy equals to ±43.75mV. For high voltage channels in
channels 3, 4, 5, and 9, the accuracy is ±4.5%. This equals to ±56.25mV.
(104) When Voltage Tamper Detection is enabled, the voltage sensor accuracy specifications are as follows:
• For low voltage channels in channels 0, 1, 2, 6, and 7, the accuracy is ±5.5%. This equals to ±68.75mV.
• For high voltage channels in channels 3, 4, 5, and 9, the accuracy is ±6.5%. This equals to ±81.25mV.

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Parameter Minimum Typical Maximum Unit

Unipolar input mode Input signal range for — — 1.35 V

Vsigp

Common mode voltage on — — 0.25 V

Vsign

Input signal range for — — 1.1 V

Vsigp – Vsign

Periphery Performance Specifications

This section describes the periphery performance, LVDS SERDES, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and
perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable
frequency in your system.

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LVDS SERDES Specifications

Table 58. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 and 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

Clock fHSCLK_in Clock 10 — 800 10 — 800 10 — 625 MHz

frequency (input boost
clock factor W =
frequency) 1 to
True 40(105)
Differential
Signaling
I/O
Standards

fHSCLK_in Clock 10 — 435.5 10 — 435.5 10 — 435.5 MHz

(input boost
clock factor W =
frequency) 1 to
SLVS400 40(105)
I/O
Standards

fHSCLK_in Clock 10 — 625 10 — 625 10 — 525 MHz

(input boost
clock factor W =
frequency) 1 to
Single- 40(105)
Ended I/O
Standards
continued...

(105) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

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Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

fHSCLK_OUT — — — 800 — — 800 — — 625 MHz

(output
clock
frequency)
True
Differential
Signaling
I/O
Standards

Transmitte True SERDES 600 — 1,600 600 — 1,600 600 — 1,250 Mbps
r Differential factor J =
Signaling 4 and
I/O 8(107) (108)
Standards
SERDES (109) — 500(110) (109) — 500(110) (109) — 500(110) Mbps
- fHSDR
(data factor J =
rate)(106) 2, uses
DDR
registers
continued...

(106) Requires package skew compensation with PCB trace length.

(107) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
(108) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
(109) The minimum specification depends on the following factors. The differential I/O buffer within the IOE does not have a minimum data
rate.
• The clock source, such as the PLL and clock pin
• The clock and data routing resource
(110) You must perform design timing analysis in Quartus Prime to achieve timing closure and run IBIS/HSPICE simulations to ensure that
the I/O buffer's electrical performance meets the interface requirements.

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Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

SERDES (109) — 250(110) (109) — 250(110) (109) — 250(110) Mbps

factor J =
1, uses
DDR
registers

tx Jitter - Total jitter ≤1,600 Mbps: 140 ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ps
True for data ≤1,250 Mbps: 160 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180
Differential rate, 600
≤1,000 Mbps: 180 ≤1,000 Mbps: 180 ≤800 Mbps: 210
Signaling Mbps – 1.6
I/O Gbps ≤800 Mbps: 210 ≤800 Mbps: 210 600 Mbps: 240
Standards 600 Mbps: 240 600 Mbps: 240

tDUTY (111) TX output 45 50 55 45 50 55 45 50 55 %

clock duty
cycle for
True
Differential
Signaling
I/O
Standards

tRISE and True — — 160 — — 160 — — 200 ps

tFALL (108) Differential
(112) Signaling
I/O
Standards

TCCS (106) True — — 202 — — 202 — — 202 ps

(111) Differential
Signaling
I/O
Standards

Receiver True SERDES 600 — 1600(113) 600 — 1600(113) 600 — 1250(113) Mbps
Differential factor J =
Signaling 4 and
I/O 8(107) (108)
continued...

(111) Not applicable for DIVCLK = 1.

(112) This applies to default pre-emphasis and VOD settings only.

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Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

Standards
- fHSDRDPA
(data rate)

SLVS400 SERDES 600 — 891 600 — 891 600 — 891 Mbps

I/O factor J =
Standards 4 and
- fHSDRDPA 8(107) (108)
(data rate)

fHSDR (data SERDES 150 — (114) 150 — (114) 150 — (114) Mbps
rate) factor J =
(without 4 and
DPA)(106) 8(107) (108)

SERDES (109) — 500(110) (109) — 500(110) (109) — 500(110) Mbps

factor J =
2, uses
DDR
registers

SERDES (109) — 250(110) (109) — 250(110) (109) — 250(110) Mbps

factor J =
1, uses
DDR
registers

DPA (FIFO DPA run — — — ≤10,000 — — ≤10,000 — — ≤10,000 UI

mode) length

DPA (soft DPA run SGMII/GbE — — 5 — — 5 — — 5 UI

CDR length protocol
mode)
continued...

(113) 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 1000 Mbps.
(114) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

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Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

All other — — 50 data — — 50 data — — 50 data —

protocols transition transition transition
per 208 UI per 208 UI per 208 UI

Soft CDR Soft-CDR — –300 — 300 –300 — 300 –300 — 300 ppm
mode ppm
tolerance

Non DPA Sampling — — — 330 — — 330 — — 330 ps

mode window

Table 59. E-Series Device Group B FPGAs LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 and 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

Parameter Symbol Condition –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

Clock fHSCLK_in Clock 10 — 625 10 — 625 10 — 500 MHz

frequency (input boost
clock factor W =
frequency) 1 to
True 40(115)
Differential
continued...

(115) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

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Parameter Symbol Condition –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

Signaling
I/O
Standards

fHSCLK_in Clock 10 — 435.5 10 — 435.5 10 — 435.5 MHz

(input boost
clock factor W =
frequency) 1 to
SLVS400 40(115)
I/O
Standards

fHSCLK_in Clock 10 — 625 10 — 625 10 — 525 MHz

(input boost
clock factor W =
frequency) 1 to
Single- 40(115)
Ended I/O
Standards

fHSCLK_OUT — — — 625 — — 625 — — 500 MHz

(output
clock
frequency)
True
Differential
Signaling
I/O
Standards

Transmitte True SERDES 600 — 1,250 600 — 1,250 600 — 1,000 Mbps
r Differential factor J =
Signaling 4 and
I/O 8(117) (118)
Standards
continued...

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Parameter Symbol Condition –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

- fHSDR SERDES (119) — 500(120) (119) — 500(120) (119) — 500(120) Mbps

(data factor J =
rate)(116) 2, uses
DDR
registers

SERDES (119) — 250(120) (119) — 250(120) (119) — 250(120) Mbps

factor J =
1, uses
DDR
registers

tx Jitter - Total jitter ≤1,250 Mbps: 160 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ps
True for data ≤1,000 Mbps: 180 ≤1,000 Mbps: 180 ≤800 Mbps: 210
Differential rate, 600
≤800 Mbps: 210 ≤800 Mbps: 210 600 Mbps: 240
Signaling Mbps –
I/O 1.25 Gbps 600 Mbps: 240 600 Mbps: 240
Standards

tDUTY (121) TX output 45 50 55 45 50 55 45 50 55 %

clock duty
cycle for
continued...

(116) Requires package skew compensation with PCB trace length.

(117) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
(118) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
(119) The minimum specification depends on the following factors. The differential I/O buffer within the IOE does not have a minimum data
rate.
• The clock source, such as the PLL and clock pin
• The clock and data routing resource
(120) You must perform design timing analysis in Quartus Prime to achieve timing closure and run IBIS/HSPICE simulations to ensure that
the I/O buffer's electrical performance meets the interface requirements.
(121) Not applicable for DIVCLK = 1.

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Parameter Symbol Condition –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

True
Differential
Signaling
I/O
Standards

tRISE and True — — 160 — — 160 — — 200 ps

tFALL (118) Differential
(122) Signaling
I/O
Standards

TCCS (116) True — — 202 — — 202 — — 202 ps

(121) Differential
Signaling
I/O
Standards

Receiver(12 True SERDES 600 — 1250(124) 600 — 1250(124) 600 — 1000(124) Mbps
3) Differential factor J =
Signaling 4 and
I/O 8(117) (118)
Standards
- fHSDRDPA
(data rate)

SLVS400 SERDES 600 — 891 600 — 891 600 — 891 Mbps

I/O factor J =
Standards 4 and
- fHSDRDPA 8(117) (118)
(data rate)
continued...

(122) This applies to default pre-emphasis and VOD settings only.

(123) When operating in DPA mode, you must enable the receiver equalization calibration feature of the input buffer.
(124) 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 1000 Mbps.

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Parameter Symbol Condition –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

fHSDR (data SERDES 150 — (125) 150 — (125) 150 — (125) Mbps
rate) factor J =
(without 4 and
DPA)(116) 8(117) (118)

SERDES (119) — 500(120) (119) — 500(120) (119) — 500(120) Mbps

factor J =
2, uses
DDR
registers

SERDES (119) — 250(120) (119) — 250(120) (119) — 250(120) Mbps

factor J =
1, uses
DDR
registers

DPA (FIFO DPA run — — — ≤10,000 — — ≤10,000 — — ≤10,000 UI

mode) length

DPA (soft DPA run SGMII/GbE — — 5 — — 5 — — 5 UI

CDR length protocol
mode)
All other — — 50 data — — 50 data — — 50 data —
protocols transition transition transition
per 208 UI per 208 UI per 208 UI

Soft CDR Soft-CDR — –300 — 300 –300 — 300 –300 — 300 ppm
mode ppm
tolerance

Non DPA Sampling — — — 330 — — 330 — — 330 ps

mode window

(125) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

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DPA Lock Time Specifications

Table 60. DPA Lock Time Specifications

The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.

For specification status, see the Data Sheet Status table

Standard Training Pattern Number of Data Transitions in Number of Repetitions per Maximum Data Transition
One Repetition of the Training 256 Data Transitions(126)
Pattern

SPI-4 00000000001111111111 2 128 768

Parallel Rapid I/O 00001111 2 128 768

10010000 4 64 768

Miscellaneous 10101010 8 32 768

01010101 8 32 768

(126) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

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LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications

Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

25

8.5

Jitter Amplitude(UI)
0.22

0.1

F1 F2 F3 F4
Jitter Frequency (Hz)

Table 61. LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
For specification status, see the Data Sheet Status table

Parameter Jitter Frequency (Hz) Sinusoidal Jitter (UI)

F1 10,000 25

F2 17,565 25

F3 1,493,000 0.22

F4 50,000,000 0.22

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Figure 3. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude

20db/dec

0.1 UI
P-P
Frequency
baud/1667 20 MHz

Memory Standards Supported

Table 62. D-Series FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by D-Series FPGAs. For specific details, refer to the External Memory Interface Spec
Estimator.

For specification status, see the Data Sheet Status table

Memory Standard Controller Type Maximum Frequency (MHz)

DDR4 SDRAM Hard memory controller 1,600

DDR5 SDRAM Hard memory controller 2,000

LPDDR4 SDRAM Hard memory controller 2,133

LPDDR5 SDRAM Hard memory controller 2,133

continued...

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Memory Standard Controller Type Maximum Frequency (MHz)

DDR4 SDRAM HPS hard memory controller 1,333

DDR5 SDRAM HPS hard memory controller 2,000

LPDDR4 SDRAM HPS hard memory controller 2,133

LPDDR5 SDRAM HPS hard memory controller 2,133

Table 63. E-Series Device Group A FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by E-Series Device Group A. For specific details, refer to the External Memory
Interface Spec Estimator.

For specification status, see the Data Sheet Status table

Memory Standard Controller Type Maximum Frequency (MHz)

DDR4 SDRAM Hard memory controller 1,333

DDR5 SDRAM Hard memory controller 1,800

LPDDR4 SDRAM Hard memory controller 1,866

LPDDR5 SDRAM Hard memory controller 1,866

DDR4 SDRAM HPS hard memory controller 1,333

DDR5 SDRAM HPS hard memory controller 1,800

LPDDR4 SDRAM HPS hard memory controller 1,866

LPDDR5 SDRAM HPS hard memory controller 1,866

Table 64. E-Series Device Group B FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by E-Series Device Group B. For specific details, refer to the External Memory
Interface Spec Estimator.

For specification status, see the Data Sheet Status table

Memory Standard Controller Type Maximum Frequency (MHz)

DDR4 SDRAM Hard memory controller 1,200

LPDDR4 SDRAM Hard memory controller 1,333

continued...

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Memory Standard Controller Type Maximum Frequency (MHz)

LPDDR5 SDRAM Hard memory controller 1,066

DDR4 SDRAM HPS hard memory controller 1,066

LPDDR4 SDRAM HPS hard memory controller 1,333

LPDDR5 SDRAM HPS hard memory controller 1,066

Related Information
External Memory Interface (EMIF) Spec Estimator

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using double data
I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks
for better jitter performance.

The memory clock output jitter is within the JEDEC* specifications when the phase jitter (integration bandwidth 10 kHz to 50
MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER and 1.22 ps at 1e-16 BER.

MIPI D-PHY Performance

Table 65. D-Series FPGAs MIPI D-PHY Performance

For specification status, see the Data Sheet Status table

Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

MIPI D- High- Long 150 — 2,500 150 — 2,500 150 — 2,500 Mbps
PHY speed reference(1
transmitter interface, 27)

or receiver Hs
Short 150 — 3,500 150 — 3,500 150 — 3,500 Mbps
reference
and
continued...

(127) The long reference/standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY
specifications.

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Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit

Min Typ Max Min Typ Max Min Typ Max

standard
reference(1
27)

Low-power — — — 20 — — 20 — — 20 MHz
interface,
Lp

Table 66. E-Series FPGAs MIPI D-PHY Performance

For specification status, see the Data Sheet Status table

Paramete Device Symbol Condition –1, –4 Speed Grade –2, –5 Speed Grade –3, –6 Speed Grade Unit
r Group
Min Typ Max Min Typ Max Min Typ Max

MIPI D- A High- Long 150 — 2,500 150 — 2,500 150 — 2,500 Mbps
PHY speed reference(
transmitt interface, 128)

er or Hs
receiver Short 150 — 3,500 150 — 3,500 150 — 3,500 Mbps
reference
and
standard
reference(
128)

Low- — — — 20 — — 20 — — 20 MHz
power
interface,
Lp

MIPI D- B High- Short 150 — 2,500 150 — 2,500 150 — 2,500 Mbps
PHY speed reference,
transmitt interface, standard
er or Hs reference,
receiver
continued...

(128) The long reference/standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY
specifications.

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Paramete Device Symbol Condition –1, –4 Speed Grade –2, –5 Speed Grade –3, –6 Speed Grade Unit
r Group
Min Typ Max Min Typ Max Min Typ Max

or long
reference
(128)

Low- — — — 20 — — 20 — — 20 MHz
power
interface,
Lp

GTS Transceiver Performance Specifications

GTS Transceiver Performance

Table 67. Transmitter and Receiver Data Rate Performance

For specification status, see the Data Sheet Status table

Symbol/Description Transceiver Speed Unit

Supported data rate for E-Series Device Group B (NRZ) 1 – 17.16 Gbps

Supported data rate for E-Series Device Group A (NRZ) 1 – 28.1 Gbps

Supported data rate for D-Series (NRZ) 1 – 28.1 Gbps

GTS Transceiver Reference Clock Specifications

Table 68. GTS Transceiver and System PLL Reference Clock Input Specifications
For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typical Max Unit

— Supported I/O Dedicated reference CML, HCSL

standards clock pin

FREF Reference clock — 100(129) — 380 MHz

operating frequency
continued...

(129) This value is 100 MHz for down spread spectrum clocking (SSC). This value can also be 25 MHz for HDMI rate of less than 1 Gbps.

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Symbol Description Condition Min Typical Max Unit

TREF-DUTY Duty cycle — 45 50 55 %

TREF-RISE/FALL Rise and fall time (as 20% – 80% — — 0.15 TREF
percentage of period)

SSC Spread-spectrum PCIe* — –5,000 to 0 — ppm

downspread

TREF-SINGLEEND-SKEW Skew between — — — 50 ps

REFCLKP and
REFCLKN

ZREF-DIFF-DC Reference clock — 80 100 120 Ω

differential input
impedance –
terminated mode

Vmin-ABS Absolute Vmin — –0.15 — — V

Vmax-ABS Absolute Vmax — — — 0.85 V

VREFIN-DIFF-AC Input reference clock — 0.6 1.2 1.7 V

differential peak-to-
peak voltage when
AC-coupled on board

VREFIN-IL-DC Input reference clock — –0.15 0 0.15 V

input low voltage
when DC-coupled on
board

VREFIN-IH-DC Input reference clock — 0.66 0.7 0.85 V

input high voltage
when DC-coupled on
board

VREFIN-CM-AC Input reference clock — Set on chip V

common-mode
voltage when AC-
coupled on board

VREFIN-CM-DC Input reference clock — 0.255 0.35 0.5 V

common-mode
voltage when DC-
coupled on board

PNREF Transmitter REFCLK 10 kHz — — –130 dBc/Hz

phase noise (156.25
continued...

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Symbol Description Condition Min Typical Max Unit

MHz)(130) (129) 100 kHz — — –138 dBc/Hz

500 kHz — — –138 dBc/Hz

3 MHz — — –140 dBc/Hz

10 MHz — — –144 dBc/Hz

20 MHz — — –146 dBc/Hz

1 GHz — — –146 dBc/Hz

VREFIN-RJ-RMS RMS jitter integrated — — — 522 fs

from 10 kHz – 20 MHz
including spurs

VREFIN-PPM-ERROR Reference clock — –350 + SSC — +350 + SSC ppm

frequency error

RCOMP External resistor for — — 499 ± 0.1% — Ω

calibration

Table 69. System PLL Reference Clock (Using HVIO) Specifications

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typical Max Unit

FREF Clock input frequency Powered by VCCIO_HVIO 25 — 125 MHz

TREF-DUTY Clock input duty cycle 45 50 55 %

Table 70. GTS Transceiver Reference Clock Output Driver Specifications

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typical Max Unit

FREF_OUT Reference clock — 25 — 380 MHz

operating frequency

TREF-DUTY_OUT Duty cycle — 45 50 55 %

continued...

(130)
To calculate the REFCLK phase noise requirement at frequencies other than 156.25 MHz, use the following formula: REFCLK phase
noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20 × log(f/156.25 MHz).

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Symbol Description Condition Min Typical Max Unit

TREF-RISE_OUT/FALL_OUT Rise and fall time (as 20% – 80% — — 0.15 TREF
percentage of period)

TREF-SINGLEEND-SKEW Skew between — — — 50 ps

REFCLKP and
REFCLKN

ZREF-DIFF-DC_OUT Reference clock — 80 100 120 Ω

differential output
impedance –
terminated mode

VREF-DIFF-AC_OUT Output reference clock — 0.9 1 1.1 V

differential peak to
peak voltage when
AC-coupled on board

VREF-CM-OUT Output reference clock — 0.45 0.5 0.55 V

common-mode

Transmitter Specifications

Table 71. Transmitter Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Condition Min Typical Max Unit

On-chip — Transmitter — 80 90 120 Ω

termination differential on-chip
termination
resistors

Transmitter output VTX-DIFF-PKPK Back-porch — 300 — 1,050 mV

eye specifications transmit amplitude

VTX-DEEMP_STEP Transmitter tap — — — 2 %

resolution

DTX-PRE_TAP_2 Pre-cursor tap 2 — 0 — 2.5 dB

de-emphasis

DTX-PRE_TAP_1 Pre-cursor tap 1 — 0 — 4.5 dB

de-emphasis
continued...

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Parameter Symbol Description Condition Min Typical Max Unit

DTX-POST_TAP_1 Post-cursor tap 1 — 0 — 6.5 dB

de-emphasis

TTX-SLEW Rise/fall time at — 10 — 20 ps

20%–80%

TTX-DJ Transmitter — — — 0.15 UIpkpk

deterministic jitter
at 25 Gbps

TTX-RJ Transmitter total At BER of 10-12 — — 0.15 UIpkpk

peak-peak random
jitter(131)

TTX-TJ Transmitter total At BER of 10-12 — — 0.28 UIpkpk

peak-peak jitter
(TTX-TJ = TTX-DDJ +
TTX-PJ + TTX-RJ)(131)
(132)

Transmitter DC ZTX-DIFF-DC Transmitter output — 80 90 120 Ω

impedance differential DC
impedance with
OCT 90 Ω mode
while
configured(133)

ZTX-CM-DC Transmitter output — 20 22.5 30 Ω

common-mode DC
impedance

Transmitter return ZRL-DIFF-DC Transmitter — — — –12 dB

loss differential DC
return loss
continued...

(131) Assume a 1st order high-pass jitter measurement filter with a cutoff of FBAUD/FGPLL = NGPLL, where NGPLL is the ratio of the 3 dB cutoff
frequency to the data rate, with typical value of 1,667.
(132) The maximum TJ value is slightly less than the sum of DDJ + PJ + RJ to take into consideration of the worst case probability, where
both deterministic and random jitter component might present at the same time.
(133) TX pins are driven to 0 V before configuration.

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Parameter Symbol Description Condition Min Typical Max Unit

ZRL-DIFF-NYQ Transmitter — — — –6 dB
differential return
loss at Nyquist
frequency
(FBAUD/2)

ZRL-CMN Transmitter — — — –6 dB
common-mode
return loss below
10 GHz

Electrical idle VTX-IDLE Electrical idle PCIe/ — — 20 mV

output voltage SATA/SAS/USB

VCM-DELTA-SQUELCH Maximum — — 100 mV

common-mode
step entering/
exiting squelch
mode

TTX-IDLE-LATENCY Latency entering/ — — 8 µs

exiting electrical
idle

Receiver detect VTX-RCV-DETECT Receiver detect PCIe/ — — 600 mV

voltage change SATA/SAS/USB
allowed during
receiver detection

Lane-to-lane — Lane-to-lane 4 < Lane count ≤ 8 — — 2 UI + 250 ps ps

output skew output skew
Lane count ≤ 4 — — 2 UI + 166 ps ps

Receiver Specifications

Table 72. Receiver Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Condition Min Typical Max Unit

On-chip — Receiver — 65 85 102 Ω

termination differential on-chip
termination 80 100 120 Ω
resistors
continued...

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Parameter Symbol Description Condition Min Typical Max Unit

Receiver input eye VRX-DIFF-PKPK Receiver input — — — 1,200 mV

specifications differential peak-
to-peak
voltage(134)

VRX-MAX Receiver input — — — 1 V

maximum
voltage(135)

VRX-MIN Receiver input — –0.3 — — V

minimum
voltage(135)

VRX-CM-DC Receiver input DC When squelch 0 — 700 mV

common-mode detector is not
voltage(136) enabled

When squelch 200 — 300 mV

detector is enabled

TRX-RJ Receiver input At BER of 10-12 — — 0.15 UIpkpk

random jitter

TRX-PJ Receiver input — — — 0.05 UIpkpk

periodic jitter (at
high
frequency(137) )

Insertion loss IINS-LOSS-28Gb/ Insertion loss at At BER of 10-15 — — –27 dB

specification s_BER10-15 Nyquist frequency
(FBAUD/2)(138)
continued...

(134) This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
(135) VRX_MAX and VRX_MIN are before and after configuration.
(136) The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or
unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode
voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
(137) High frequency is defined as frequencies beyond the CDR loop bandwidth (typically FBAUD/1,667).
(138) COM compliant package and channel.

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Parameter Symbol Description Condition Min Typical Max Unit

IINS-LOSS-28Gb/ At BER of 10-12 — — –30 dB

s_BER10-12

IINS-LOSS-17Gb/ Insertion loss at At BER of 10-12 — — –30 dB

s_BER10-12 Nyquist frequency
(FBAUD/2)(138)

Receiver return ZRL-DIFF-DC Receiver — — — –12 dB

loss differential DC
return loss

ZRL-DIFF-NYQ Receiver — — — –6 dB
differential return
loss at Nyquist
frequency
(FBAUD/2)

ZRL-CM Receiver common- — — — –6 dB

mode return loss
below 10 GHz

Receiver DC RDIFF-DC Receiver 85 Ω on-chip 65 85 102 Ω

impedance differential DC termination
impedance
100 Ω on-chip 80 100 120 Ω
termination

RCM-DC Receiver common- — 20 25 30 Ω

mode DC
impedance

Receiver signal VIDLE-THRESH Receiver signal — 75 120 175 mV

detection(139) detect input
voltage threshold

(139) Receiver signal detection values in this table are applicable to PCIe and similar standards, such as SATA, where a clock pattern like
PCIe EIEOS 500 MHz clock pattern is used.

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Electrical Compliance

Table 73. Electrical Compliance List

For specification status, see the Data Sheet Status table

Specification/Clause Protocol Lane Rate (Gbps)

E-Series Device Group B E-Series Device Group A, D-Series

XFP MSA XFI 10.3125 10.3125

IEEE 802.3ba-2010 XLPPI 10.3125 10.3125

Serial-GMII Specification V1.7 1GE SGMII 1.25 1.25

IEEE 802.3ba XLAUI 10.3125 10.3125

IEEE 802.3ba CAUI-10 10.3125 10.3125

IEEE 802.3by 25GAUI-C2C/C2M — 1x25.78125

IEEE 802.3ap 2007 10GBASE-KR 10.3125 10.3125

IEEE 802.3by 111/110 25GBASE-KR/CR — 25.78125

IEEE 803.3ap-2007 1000BASE-KX/CX 1.25 1.25

IEEE 802.3an-2006

CEI 4.0 CEI-11G SR/MR/LR 9.95 – 11.2 9.95 – 11.2

CEI-6G SR/LR 4.976 – 6.375 4.976 – 6.375

G.709 OTU1 — 1.327451, 2.666

G.sup56
OTU2 — 10.709, 11.049, 11.270
G.sup43
G.sup58 OTU2e — 11.095

OTU2f — 11.317, 11.846, 12.639

OTU4 OTL4.4 — 4x27.952493

OTU4 OTLC.4 — 4x28.076177

continued...

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Specification/Clause Protocol Lane Rate (Gbps)

E-Series Device Group B E-Series Device Group A, D-Series

PCIe BASE 4.0 PCIe 3.0 , PCIe 4.0 8, 16(140) 8, 16

PIPE 4.4.1

SMPTE 259M SDI SD 0.27 0.27

SMPTE 292M SDI HD 1.485/1.483 1.485/1.483

SMPTE ST 424 SDI 3G 2.97/2.967 2.97/2.967

SMPTE ST 2081 SDI 6G 5.94/5.934 5.94/5.934

SMPTE ST 2082 SDI 12G 11.88/11.868 11.88/11.868

CPRI V7.0 CPRI 1.2288 1.2288

2.4576 2.4576

3.072 3.072

4.9152 4.9152

6.144 6.144

8.1101 8.1101

9.8304 9.8304

10.1376 10.1376

— 24.33024

JESD204B JESD204B up to 17.16 up to 19.66

JESD204C JESD204C up to 17.16 up to 28.1

DP 2.0 DisplayPort 1.4 1.62 1.62

2.7 2.7

5.4 5.4

8.1 8.1
continued...

(140) PCIe 4.0 is supported for –4S (VCC = 0.8 V) devices only.

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Specification/Clause Protocol Lane Rate (Gbps)

E-Series Device Group B E-Series Device Group A, D-Series

DisplayPort 2.0 10 10

13.5 13.5

— 20

FC-PI-2 Fiber Channel 1.0625 1.0625

2.125 2.125

FC-PI-5 4.25 4.25

8.5 8.5

10GFC 10.518 10.518

FC-PI-5 14.025 14.025

FC-PI-6 — 28.05

— 4x28.05

Serial ATA revision 3.5a Sata Gen 3 1.5 – 6 1.5 – 6

T10/BSR INCITS 519
SAS 1.5 – 12.0 1.5 – 22.5

G.984 GPON/EPON — 1.244, 1.250, 2.488, 9.952, 10.313, 25

CEI-6G-SR Interlaken 6.25 6.25

CEI-11G-SR 10.3125 10.3125

CEI-11G-SR+ 12.5 12.5

OIF-28G MR (OIF-CEI3.0) — 25.78125

HDMI 1.4 HDMI 3.4 3.4

HDMI 2.0 6 6

HDMI 2.1 up to 12 up to 12

SLVS-EC Specification Version 1.0 SLVS-EC RX 2.376 2.376

SLVS-EC Specification Version 2.0 5 5

SFF-8402 SFP+ 9.95 – 11.2 9.95 – 11.2

continued...

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Specification/Clause Protocol Lane Rate (Gbps)

E-Series Device Group B E-Series Device Group A, D-Series

SFF-8431 4.1

SFF-8431 Rev 4.1

SFF-8418

USB 3.1, USB 3.2 USB 3.1 Gen 1 5 5

USB 3.2 Gen 2 (141) — 10 (141)

RapidIO™ Interconnect Specification SRIO 2 – 16 2 – 16

HPS Performance Specifications

This section provides hard processor system (HPS) specifications and timing.

HPS Clock Performance

Table 74. D-Series SoC Maximum HPS Clock Frequencies

For specification status, see the Data Sheet Status table

Performance VCCL_HPS (V)(142) Cortex-A55 Core Cortex-A76 Core DSU (DynamIQ L3 Frequency (MHz) DDR4/LPDDR4/
Frequency (MHz) Frequency (MHz) Shared Unit) (l3_main_free_clk) DDR5/LPDDR5 Clock
Frequency (MHz) (MHz)
(mpu_free_clk)

–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory
Standards Supported
–2 speed grade SmartVID 1,333 1,600 1,066 400 table.

–3 speed grade SmartVID 1,250 1,400 933 400

(141) Gen 2 is supported using transceiver PMA only, with soft PIPE PCS and USB 3.2 controller in core fabric.
(142) VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2
power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.

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Table 75. E-Series SoC Maximum HPS Clock Frequencies

For specification status, see the Data Sheet Status table

Performance VCCL_HPS (V)(143) Cortex-A55 Core Cortex-A76 Core DSU (DynamIQ L3 Frequency (MHz) DDR4/LPDDR4/
Frequency (MHz) Frequency (MHz) Shared Unit) (l3_main_free_clk) DDR5/LPDDR5 Clock
Frequency (MHz) (MHz)
(mpu_free_clk)

–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory
Standards Supported
–2 speed grade SmartVID 1,333 1,600 1,066 400 table.

–3 speed grade SmartVID 1,250 1,400 933 400

–4 speed grade Fixed: 0.8 1,250 1,400 933 400

–5 speed grade Fixed: 0.78 800 800 533 400

–6 speed grade Fixed: 0.75 800 800 533 400

Related Information
• HPS Power Supply Operating Conditions on page 31
• Memory Standards Supported on page 85

HPS Internal Oscillator Frequency

Table 76. HPS Internal Oscillator Frequency

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Internal oscillator frequency 150 300 400 MHz

(143) VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2
power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.

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HPS PLL Specifications

Table 77. HPS PLL Input Requirements

The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Pin Connection Guidelines of this device for information about assigning this
pin.

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Clock input range 25 — 125 MHz

Clock input accuracy — — 50 ppm

Clock input duty cycle 45 50 55 %

Table 78. HPS PLL Performance

For specification status, see the Data Sheet Status table

Description Min Max Unit

Main PLL VCO output — 4,000(144) MHz

Peripheral PLL VCO output — 4,000(144) MHz

h2f_user0_clk(145) — 500 MHz

h2f_user1_clk(145) — 500 MHz

HPS Cold Reset

Table 79. HPS Cold Reset

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit

tRST0 Minimum time for 3 — ms

HPS_COLD_nRESET
asserted(146)

(144) For E-Series SoC, the maximum VCO output is 3,500 MHz for -5 and -6 speed grade.
(145) The HPS PLL provides this clock to the FPGA fabric.

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HPS SPI Timing Characteristics

Table 80. SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tspi_ref_clk The period of the SPI 2.5 — — ns

internal reference clock,
sourced from
l4_main_clk

fclk SPIM_CLK clock frequency — — 60 MHz

Tclk SPIM_CLK clock period 16.67 — — ns

Tdutycycle SPIM_CLK duty cycle 45 50 55 %

Tck_jitter SPIM_CLK output jitter — — 2 %

Tdio Master-out slave-in –3 — 2 ns

(MOSI) output skew

Tdssfrst (147) SPI_SS_N asserted to first (1.5 × Tclk) – 2 — — ns

SPIM_CLK edge
continued...

(146)
HPS_COLD_nRESET may be ignored if HPS is not running or if the device is being configured.
(147) SPI_SS_N behavior differs depending on Motorola SPI protocols, Texas Instruments Synchronous Serial Protocols, or National
Semiconductor Microwire operational mode.

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Symbol Description Min Typ Max Unit

Tdsslst (147) Last SPIM_CLK edge to Tclk – 2 — — ns

SPI_SS_N deasserted

Tsu (148) SPIM_MISO setup time — — ns

5.0 – (rx_sample_dly x
with respect to SPIM_CLK Tspi_ref_clk)(149)
capture edge

Th (148) Input hold in respect to — — ns

1.3 + (rx_sample_dly x
SPIM_CLK capture edge Tspi_ref_clk)(149)

(148) The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge
depending on the scpol register bit; for Texas Instruments Synchronous Serial Protocols, the capture edge is the falling edge; for
National Semiconductor Microwire, the capture edge is the rising edge.
(149)
Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps).

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Figure 4. SPI Master Output Timing Diagram

scph* = 0
Tdssfrst
SPI_SS Tdio (max) Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI OUT0 OUT1 OUTn

SPI_MISO

scph* = 1
Tdssfrst
SPI_SS Tdio (max) Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI OUT0 OUT1 OUTn

SPI_MISO

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Figure 5. SPI Master Input Timing Diagram

scph* = 0

SPI_SS

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI
Tsu Th
SPI_MISO IN0 IN1 INn

scph* = 1

SPI_SS

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI
Tsu Th
SPI_MISO IN0 IN1 INn

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Table 81. SPI Slave Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tspi_ref_clk The period of the SPI 2.5 — — ns

internal reference clock,
sourced from
l4_main_clk

fclk SPIM_CLK clock frequency — — 33 MHz

Tclk SPIM_CLK clock period 30 — — ns

Tdutycycle SPIM_CLK duty cycle 45 50 55 %

Td Master-in slave-out (2 × Tspi_ref_clk) + 3 — (3 × Tspi_ref_clk) + 11 ns

(MISO) output skew

Tsu Master-out slave-in 4 — — ns

(MOSI) setup time

Th Master-out slave-in 9 — — ns
(MOSI) hold time

Tsuss SPI_SS_N asserted to first Tspi_ref_clk + 4.2 — — ns

SPIM_CLK edge

Thss Last SPIM_CLK edge to Tspi_ref_clk + 4.2 — — ns

SPI_SS_N deasserted

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Figure 6. SPI Slave Output Timing Diagram

scph* = 0

SPI_SS Td (max)
Td (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO OUT0 OUT1 OUTn

SPI_MOSI

scph* = 1

SPI_SS Td (max)
Td (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO OUT0 OUT1 OUTn

SPI_MOSI

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Figure 7. SPI Slave Input Timing Diagram

scph* = 0
Tsuss
SPI_SS Thss

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO
Th
Ts
SPI_MOSI
IN0 IN1 INn

scph* = 1
Tsuss
SPI_SS Thss

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO
Ts Th
SPI_MOSI IN0 IN1 INn

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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HPS SD/eMMC Timing Characteristics

Table 82. HPS Secure Digital (SD)/Embedded MultiMediaCard (eMMC) Timing Requirements

Supports SD devices up to V6.1. Supports SDIO devices up to V4.1. Supports SD/eMMC devices up to V5.1.

These timings apply to SD, MMC, and eMMC cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tsdmmc_cclk SD SDMMC_CCLK Identification mode, 2,500 — — ns

clock period 400 kHz

SDR12, 25 MHz 40 — — ns

SDR25, 50 MHz 20 — — ns

SDR50, 100 MHz 10 — — ns

SDR104, <200 MHz 5 — — ns

DDR50, 50 MHz 20 — — ns

eMMC SDMMC_CCLK Legacy, 25MB/s, 25 40 — — ns

clock period MHz

HS_SDR, 50MB/s, 50 20 — — ns
MHz

HS_DDR, 100MB/s, 50 20 — — ns
MHz

HS200, SDR, 5 — — ns
200MB/s, 200 MHz

HS400, DDR, 5 — — ns
400MB/s, 200 MHz

Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %

Tsdmmc_cclk_jitter SDMMC_CCLK output jitter — — 2 %

Tsdmmc_clk Internal reference clock before division by 4 5 — — ns

(200 MHz)

None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at
1.8 V at power on.

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Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC
interface.

Table 83. SD Input Timing (SDR104, SDR50, SDR25, SDR12)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tis SDMMC_CMD/ 1.4 — — ns

SDMMC_DATA[7:0] input
setup (SDR104)

SDMMC_CMD/ 3 — — ns
SDMMC_DATA[7:0] input
setup (SDR50)

SDMMC_CMD/ 6 — — ns
SDMMC_DATA[7:0] input
setup (SDR25)

SDMMC_CMD/ 5 — — ns
SDMMC_DATA[7:0] input
setup (SDR12)

Tih SDMMC_CMD/ 0.8 — — ns

SDMMC_DATA[7:0] input
hold (SDR104)

SDMMC_CMD/ 0.8 — — ns
SDMMC_DATA[7:0] input
hold (SDR50)

SDMMC_CMD/ 2 — — ns
SDMMC_DATA[7:0] input
hold (SDR25)

SDMMC_CMD/ 5 — — ns
SDMMC_DATA[7:0] input
hold (SDR12)

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Figure 8. SD Input (SDR104, SDR50, SDR25, SDR12) Timing Diagram

SDCLK Input 50%

Tis Tih
CMD Input
DAT[3:0] Input Not Valid Valid

Table 84. SD Output Timing (SDR50, SDR25, SDR12)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Todly SDMMC_CMD/ — — 7.5 ns

SDMMC_DATA[7:0] output
delay (SDR50)

SDMMC_CMD/ — — 14 ns
SDMMC_DATA[7:0] output
delay (SDR25, SDR12)

Tohld SDMMC_CMD/ 1.5 — — ns

SDMMC_DATA[7:0] output
hold

Figure 9. SD Output (SDR50, SDR25, SDR12) Timing Diagram

SDCLK Input 50% 50%

Todly

Tohld
CMD Output
DAT[3:0] Output Valid

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Table 85. SD Output Timing (SDR104)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Top SDMMC_CMD/ 0 — 10 ns
SDMMC_DATA[7:0] output
phase

∆Top SDMMC_CMD/ –350 — 1,550 ps

SDMMC_DATA[7:0] output
delay variation due to
temperature change after
tuning

Todw SDMMC_CMD/ 3 — — ns
SDMMC_DATA[7:0] output
hold

Figure 10. SD Output (SDR104) Timing Diagram

SDCLK Input 50% 50%

Top Todw

CMD Output
DAT[3:0] Output Valid

Table 86. SD Timing (DDR50)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tisu SDMMC_CMD input setup 6 — — ns

Tih SDMMC_CMD input hold 0.8 — — ns

Todly SDMMC_CMD output delay — — 13.7 ns

Toh SDMMC_CMD output hold 1.5 — — ns

continued...

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Symbol Description Min Typ Max Unit

Tisu2x SDMMC_DATA[7:0] input 3 — — ns

setup

Tih2x SDMMC_DATA[7:0] input 0.8 — — ns

hold

Todly2x SDMMC_DATA[7:0] output — — 7 ns

delay

Todly2x SDMMC_DATA[7:0] output 1.5 — — ns

hold

Figure 11. SD (DDR50) Timing Diagram

CLK
Tisu2x Tih2x Tisu2x Tih2x
DAT[3:0]
Invalid Data Invalid Data Invalid Data Invalid
Input
Todly2x (max) Todly2x (max)
Todly2x (min) Todly2x (min)
DAT[3:0]
Data Data Data
Output

In DDR50 mode, DAT[3:0] lines are sampled on both

edges of the clock (not applicable for CMD line)
Available timing window
for card output transition Available timing window for
host to sample data from card

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Table 87. eMMC Timing (Legacy, HS_SDR)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tisu EMMC_CMD_DATA input 3 — — ns

setup (Legacy)

EMMC_CMD_DATA input 3 — — ns
setup (HS_SDR)

Tih EMMC_CMD DATA_input 3 — — ns

hold (Legacy)

EMMC_CMD DATA_input 3 — — ns
hold (HS_SDR)

Todly EMMC_CMD_DATA output — — 13.7 ns

delay (Legacy)

EMMC_CMD_DATA output — — 13.7 ns

delay (HS_SDR)

Toh EMMC_CMD_DATA output 8.3 — — ns

hold (Legacy)

EMMC_CMD DATA_output 2.5 — — ns

hold (HS_SDR)

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Figure 12. eMMC (Legacy, HS_SDR) Timing Diagram

CLK 50% 50%

Tih
Tisu

Input Data Invalid Data

Todly Toh

Output Data Invalid Data

Data must always be sampled on the rising edge of the clock.

Table 88. eMMC Timing (HS_DDR)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tisu_ddr EMMC_CMD_DATA input 2.5 — — ns

setup

Tih_ddr EMMC_CMD DATA_input 2.5 — — ns

hold

Todly_ddr EMMC_CMD_DATA output 1.5 — 7 ns

delay (max=delay,
min=hold)

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Figure 13. eMMC (HS_DDR) Timing Diagram

CLK
Tih_ddr Tih_ddr
Tisu_ddr Tisu_ddr

Input
Data Data Data Invalid

Todly_ddr (max) Todly_ddr (max)

Todly_ddr (min) Todly_ddr (min)

Output Data Data Data

In DDR mode data on DAT[7:0] lines are sampled on both edges of the clock
(not applicable for CMD line)

Table 89. eMMC Timing (HS200)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tisu EMMC_CMD_DATA input 1.4 — — ns

setup

Tih EMMC_CMD DATA_input 0.8 — — ns

hold
continued...

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Symbol Description Min Typ Max Unit

Tph SDMMC_CMD/ 0 — 10 ns
SDMMC_DATA[7:0] output
phase

∆Tph SDMMC_CMD/ –350 — 1,550 ps

SDMMC_DATA[7:0] output
delay variation due to
temperature change after
tuning

Tvw SDMMC_CMD/ 3 — — ns
SDMMC_DATA[7:0] output
hold

Figure 14. eMMC Input (HS200) Timing Diagram

Clock Input 50%

Tisu Tih

CMD.DAT[7-0] Valid
Input Window

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Figure 15. eMMC Output (HS200) Timing Diagram

50%
Clock Input

Tph Tvw

CMD.DAT[7-0] Valid
Output Window

Table 90. eMMC Timing (HS400)

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tisu_ddr EMMC_CMD_DATA input 0.4 — — ns

setup

Tih_ddr EMMC_CMD DATA_input 0.4 — — ns

hold

Trq SDMMC_CMD/ 0 — 10 ns
SDMMC_DATA[7:0] output
phase

∆Trq SDMMC_CMD/ –350 — 200 ps

SDMMC_DATA[7:0] output
delay variation due to
temperature change after
tuning

Trqh SDMMC_CMD/ 2 — — ns
SDMMC_DATA[7:0] output
hold

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Figure 16. eMMC Input (HS400) Timing Diagram

Clock Input 50%

Tisu_ddr Tih_ddr Tisu_ddr Tih_ddr

DAT[7-0] Valid Valid

Input Window Window

Figure 17. eMMC Output (HS400) Timing Diagram

Data Strobe 50%

Trq Trqh

DAT[7-0] Valid Valid

Output Window Window

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HPS USB 2.0 Timing Characteristics

Table 91. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Fusb_clk USB_CLK clock frequency — 60 — MHz

Tusb_clk USB_CLK clock period — 16.667 — ns

Td Clock to USB_STP/ 2 — 7 ns
USB_DATA[7:0] output
delay

Tsu Setup time for USB_DIR/ 4 — — ns

USB_NXT/USB_DATA[7:0]

Th Hold time for USB_DIR/ 1 — — ns

USB_NXT/USB_DATA[7:0]

Figure 18. USB ULPI Timing Diagram

USB_CLK
Td
USB_STP

USB_DATA[7:0] To PHY From PHY

TSU Th
USB_DIR and USB_NXT

Note: The USB interface supports single data rate (SDR) timing only.

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Note: If you need to adjust the timings of certain signals, you can use the HPS registers Pin_Mux.io0_delay through
Pin_Mux.io47_delay to allow software to set the delay chains in each of the dedicated I/Os. For example, to add output
and input delay to the USB_DATA3 signal (HPS_IOA_8), program Pin_Mux.io7_delay.output_val_en = 1, and
Pin_Mux.io7_delay.output_val = 15 to add approximately 1.4 ns output delay from the HPS, and program
Pin_Mux.io7_delay.input_val_en = 3, and Pin_Mux.io7_delay.input_val = 30 to add approximately 2.8 ns input delay into the
HPS. See HPS Programmable I/O Timing Characteristics for more information.

HPS USB 3.1 Timing Characteristics

Table 92. HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Fusb_clk USB_CLK clock frequency — 60 — MHz

Tusb_clk USB_CLK clock period — 16.667 — ns

Td Clock to USB_STP/ 2 — 7 ns
USB_DATA[7:0] output
delay

Tsu Setup time for USB_DIR/ 4 — — ns

USB_NXT/USB_DATA[7:0]

Th Hold time for USB_DIR/ 1 — — ns

USB_NXT/USB_DATA[7:0]

Figure 19. USB ULPI Timing Diagram

USB_CLK
Td
USB_STP

USB_DATA[7:0] To PHY From PHY

TSU Th
USB_DIR and USB_NXT

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Note: The USB interface supports single data rate (SDR) timing only.

Note: If you need to adjust the timings of certain signals, you can use the HPS registers Pin_Mux.io0_delay through
Pin_Mux.io47_delay to allow software to set the delay chains in each of the dedicated I/Os. For example, to add output
and input delay to the USB_DATA3 signal (HPS_IOA_8), program Pin_Mux.io7_delay.output_val_en = 1, and
Pin_Mux.io7_delay.output_val = 15 to add approximately 1.4 ns output delay from the HPS, and program
Pin_Mux.io7_delay.input_val_en = 3, and Pin_Mux.io7_delay.input_val = 30 to add approximately 2.8 ns input delay into the
HPS. See HPS Programmable I/O Timing Characteristics for more information.

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 93. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk (1000Base-T) TX_CLK clock period (125 — 8 — ns

MHz)

Tclk (100Base-T) TX_CLK clock period (25 — 40 — ns

MHz)

Tclk (10Base-T) TX_CLK clock period (2.5 — 400 — ns

MHz)

Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %

Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 %

Td (150) (151) TXD/TX_CTL to TX_CLK –0.5 — 0.5 ns

output skew

(150) Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
(151) If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5–2.0 ns with the HPS I/O
programmable delay, to meet the PHY's 1 ns data-to-clock skew requirement.

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Figure 20. RGMII TX Timing Diagram

TX_CLK
TX_D[3:0] D0 D1

Td

TX_CTL

Table 94. RGMII RX Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk (1000Base-T) RX_CLK clock period (125 — 8 — ns

MHz)

Tclk (100Base-T) RX_CLK clock period (25 — 40 — ns

MHz)

Tclk (10Base-T) RX_CLK clock period (2.5 — 400 — ns

MHz)

Tdutycycle (1000Base-T) RX_CLK duty cycle 45 50 55 %

Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 50 60 %

Tsu RX_D/RX_CTL to RX_CLK 1 — — ns

setup time

Th (152) RX_CLK to RX_D/RX_CTL 1 — — ns

hold time

(152) If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK
by 1.5–2 ns, using the HPS I/O programmable delay.

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Figure 21. RGMII RX Timing Diagram

RX_CLK

TSU Th

RX_D[3:0] D0 D1

RX_CTL

Table 95. Management Data Input/Output (MDIO) Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Fclk MDC clock frequency — — 2.5 MHz

Tclk MDC clock period 400 — — ns

Td MDC to MDIO output data 10 — 300 ns

delay

Tsu Setup time for MDIO data 10 — — ns

Th Hold time for MDIO data 0 — — ns

Figure 22. MDIO Timing Diagram

MDC
Td
MDIO_OUT Dout0 Dout1

TSU Th

MDIO_IN Din0

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SGMII Timing Requirements

SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES IP. Refer to the LVDS
SERDES Specifications section for timing specifications.

SGMII+ operating mode is supported through FPGA fabric using SGMII+ PCS soft IP and serial transceiver interface. Refer to
the Transceiver Performance Specifications section for timing specifications.

Related Information
• LVDS SERDES Specifications on page 74
• GTS Transceiver Performance Specifications on page 89

HPS I2C Timing Characteristics

Table 96. HPS I2C Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Standard Mode Fast Mode Unit

Min Max Min Max

Fclk Serial clock (SCL) — 100 — 400 KHz

clock frequency

Tclk Serial clock (SCL) 10 — 2.5 — μs

clock period

Tclk_jitter I2C clock output jitter — 2 — 2 %

THIGH (153) SCL high period 4(154) — 0.6(155) — μs

TLOW (156) SCL low period 4.7(157) — 1.3(158) — μs

continued...

(153)
You can adjust THIGH using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
(154)
The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the SCL_High_time equation in the Hard Processor
System Technical Reference Manual.
(155)
The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the SCL_High_time equation in the Hard Processor System
Technical Reference Manual.

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Symbol Description Standard Mode Fast Mode Unit

Min Max Min Max

TSU_DAT Setup time for serial 0.25 — 0.1 — μs

data line (SDA) data
to SCL

THD_DAT (159) Hold time for SCL to 0 3.15 0 0.6 μs

SDA data

TVD_DAT and TVD_ACK SCL to SDA output — 3.45(161) — 0.9(162) μs

(160) data delay

TSU_STA Setup time for a 4.7 — 0.6 — μs

repeated start
condition

THD_STA Hold time for a 4 — 0.6 — μs

repeated start
condition

TSU_STO Setup time for a stop 4 — 0.6 — μs

condition

TBUF SDA high pulse 4.7 — 1.3 — μs

duration between
STOP and START
continued...

(156)
You can adjust TLOW using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
(157)
The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the SCL_Low_time equation in the Hard Processor System
Technical Reference Manual.
(158)
The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the SCL_Low_time equation in the Hard Processor System
Technical Reference Manual.
(159) THD_DAT is affected by the rise and fall time.
(160)
TVD_DAT and TVD_ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
(161)
Use maximum SDA_HOLD = 240 to be within the specification.
(162)
Use maximum SDA_HOLD = 60 to be within the specification.

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Symbol Description Standard Mode Fast Mode Unit

Min Max Min Max

Tscl_r (163) SCL rise time — 1,000 20 300 ns

Tscl_f (163) SCL fall time — 300 6.54 300 ns

Tsda_r (163) SDA rise time — 1,000 20 300 ns

Tsda_f (163) SDA fall time — 300 6.54 300 ns

(163) Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value,
and total capacitance on the transmission line.

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Figure 23. I2C Timing Diagram

TSU_DAT
Tf Tr
70%
SDA 30%

THIGH
Tf THD_DAT Tr TVD_DAT

SCL 70%
30%
THD_STA Tclk TLOW

TBUF

SDA 70%
30%

TSU_STA THD_STA TVD_ACK TSU_STO

SCL 70%
30%

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HPS I3C Timing Characteristics

Table 97. HPS I3C Timing Requirements When Communicating With I2C Legacy Devices
For specification status, see the Data Sheet Status table

Symbol Description Fast Mode Fast Mode Plus Unit

Min Max Min Max

fSCL Serial clock (SCL) 0 0.4 0 1 MHz

clock frequency

TSCL SCL clock period 2.5 — 1 — μs

Tclk_jitter I3C clock output jitter — 2 — 2 %

THIGH SCL high period 600 — 260 — ns

TDIG_H THIGH + Tscl_r — THIGH + Tscl_r — ns

TLOW SCL low period 1,300 — 500 — ns

TDIG_L TLOW + Tscl_r — TLOW + Tscl_r — ns

TSU_DAT Setup time for serial 100 — 50 — ns

data line (SDA) data
to SCL

THD_DAT Hold time for SCL to — — — — —

SDA data

TSU_STA Setup time for a 600 — 260 — ns

repeated start
condition

THD_STA Hold time for a 600 — 260 — ns

repeated start
condition

TSU_STO Setup time for a stop 600 — 260 — ns

condition

TBUF SDA high pulse 1.3 — 0.5 — μs

duration between
STOP and START

Tscl_r SCL rise time 20 300 — 120 ns

continued...

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Symbol Description Fast Mode Fast Mode Plus Unit

Min Max Min Max

Tscl_f SCL fall time 20 × (VCCIO_HPS / 5.5 300 20 × (VCCIO_HPS / 5.5 120 ns
V)(164) V)(164)

Tsda_r SDA rise time 20 300 — 120 ns

Tsda_f SDA fall time 20 × (VCCIO_HPS / 5.5 300 20 × (VCCIO_HPS / 5.5 120 ns
V)(164) V)(164)

TSPIKE Pulse width of spikes 0 50 0 50 ns

that the spike filter
must suppress

Table 98. HPS I3C Open Drain Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit

THIGH SCL high period — 41 ns

TDIG_H — THIGH + TCF ns

THIGH_INIT (165) SCL high period (for First 200 — ns

Broadcast Address)

TLOW_OD SCL low period 200 — ns

TLOW_OD_L TLOW_ODmin + TfDA_ODmin — ns

TfDA_OD SDA signal fall time TCF 12 ns

TSU_OD Setup time for serial data line 3 — ns

(SDA) data to SCL

TCAS (166) Clock after START Condition 38.4 ns For ENTAS0: 1 μs —

continued...

(164) Refer to the HPS Power Supply Operating Conditions section for VCCIO_HPS values.
(165) The controller uses this timing to send the first Broadcast Address after bus initialization, in order to disable the I2C spike filter for
applicable I3C target devices.
(166) Enter Activity State (ENTAS) is a Common Command Code (CCC) supported by all I3C master and slave devices.

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Symbol Description Min Max Unit

For ENTAS1: 100 μs —

For ENTAS2: 2 ms —

For ENTAS3: 50 ms —

TCBP Clock before STOP Condition TCASmin/2 — s

TMMOverlap Current master to secondary TDIG_OD_Lmin — ns

master overlap time during
handoff

TAVAL Bus available condition 1 — μs

TIDLE Bus IDLE condition 200 — μs

TMMLock Time internal where new master TAVALmin — μs

not driving SDA Low

Table 99. HPS I3C Push-Pull Timing Requirements for SDR Mode
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

fSCL Serial clock (SCL) clock 0.01 12.5 12.9 MHz

frequency

TCLK SCL clock period 77.5 ns 80 ns 100 μs —

THIGH SCL clock high period 24 — — ns

TDIG_H 32 — — ns

TLOW SCL clock low period 24 — — ns

TDIG_L 32 — — ns

THIGH_MIXED SCL clock high period for 24 — — ns

mixed bus(167)
TDIG_H_MIXED 32 — 45 ns
continued...

(167) During I3C communication on a mixed bus, to avoid I2C controllers from interpreting I3C signaling as valid I2C signaling, the TDIG_H
period must be constrained.

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Symbol Description Min Typ Max Unit

TSCO Clock in to data out for — — 12 ns

slave

TCR SCL rise time — — 150e6 × 1/fSCL (capped at ns

60 ns)

TCF SCL fall time — — 150e6 × 1/fSCL (capped at ns

60 ns)

THD_PP Hold time for SCL to SDA TCR + 3 and TCF + 3 — — ns

data (master)

Hold time for SCL to SDA 0 — — ns

data (slave)

TSU_PP SDA signal data setup 3 — — ns

time

TCASr Clock after repeated TCASmin — — ns

START (Sr)

TCBSr Clock before repeated TCASmin / 2 — — ns

START (Sr)

Cb Capacitive load per bus — — 50 pF

Line (SDA/SCL)

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Figure 24. I3C Legacy Mode Timing Diagram

Sr Sr P
TfDA TrDA THD_DAT

70%
SDA
30%
TSU_STA
THD_STA TSU_STO
TSU_DAT

TfCL TrCL

70%
SCL
30%

THIGH TLOW TLOW THIGH

= Open Drain with Weak Pullup = High Speed Active Push-Pull Drive

Figure 25. TDIG_H and TDIG_L

THIGH TCF TLOW

70%

30%

TCR TDIG_H TDIG_L

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Figure 26. I3C Start Condition Timing Diagram

TfDA_OD TDS_OD TSU_OD

70%
SDA
30%

TrDA_OD
70%
SCL
30%

TCAS TCF TLOW_OD TCR

Figure 27. I3C Stop Condition Timing Diagram

70%
SDA
30%

70%
SCL
30%

TCR TCBP

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Figure 28. I3C Start Master Out Timing Diagram

70%
SDA
30%

THD_PP TSU_PP

70%
SCL
30%

TCF TCR

Figure 29. I3C Slave Out Timing Diagram

70%
SDA
30%

TSCO TSU_PP

70%
SCL
30%

TCF TCR

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Figure 30. Master SDR Timing Diagram

70%
SDA
30%

70%
SCL
30%

TSU_PP THD_SDR

Related Information
HPS Power Supply Operating Conditions on page 31

HPS NAND Timing Characteristics

Table 100. HPS NAND SDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200
MT/s.

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit

TWP (168) Write enable pulse width 10 — ns

TWH (168) Write enable hold time 7 — ns

TRP (168) Read enable pulse width 10 — ns

continued...

(168) This timing is software programmable. Refer to the NAND Flash Controller chapter in the Hard Processor System Technical Reference
Manual for more information about software-programmable timing in the NAND flash controller.

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Symbol Description Min Max Unit

TREH (168) Read enable hold time 7 — ns

TCLS (168) Command latch enable to write 10 — ns

enable setup time

TCLH (168) Command latch enable to write 5 — ns

enable hold time

TCS (168) Chip enable to write enable 15 — ns

setup time

TCH (168) Chip enable to write enable hold 5 — ns

time

TALS (168) Address latch enable to write 10 — ns

enable setup time

TALH (168) Address latch enable to write 5 — ns

enable hold time

TDS (168) Data to write enable setup time 7 — ns

TDH (168) Data to write enable hold time 5 — ns

TWB (168) Write enable high to R/B low — 200 ns

TCEA Chip enable to data access time — 100 ns

TREA Read enable to data access time — 40 ns

TRHZ Read enable to data high — 200 ns

impedance

TRR Ready to read enable low 20 — ns

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Figure 31. NAND SDR Command Latch Timing Diagram

CLE tCLS tCLH

tCS tCH
CE
tWP

WE
tALS tALH
ALE
tDS tDH

IO0-7 Command

R/B tWB

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Figure 32. NAND SDR Address Latch Timing Diagram

tCLS
CLE

tCS
CE

tWP
WE
tWH

tALS tALH
ALE
tDS tDH

IO0-7 Address

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Figure 33. NAND SDR Data Output Cycle Timing Diagram

tCLH
CLE

tCH
CE

tWP tWP tWP

WE tWH

tALS
ALE
tDS tDH tDS tDH tDS tDH

IOx DOUT 0 DOUT 1 DOUT n

Figure 34. NAND SDR Data Input Cycle Timing Diagram

tCEA
CE
tRP tRP tRP
RE tREH
tRR

R/B
tREA tRHZ tREA tRHZ tREA tRHZ

IOx DIN 0 DIN 1 DIN n

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Figure 35. NAND SDR Data Input Timing Diagram for Extended Data Output (EDO) Cycle

CE

tRP
RE tREH
tRR

tREA tREA
R/B
tRHZ

IOx DIN 0 DIN 1 DIN n

tCEA

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Figure 36. NAND SDR Read Status Timing Diagram

CLE tCLS tCLH

tCS tCH tCEA

CE

tWP
WE

tRHZ
RE
tDS tDH

IO0-7 70h Status

tREA

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Figure 37. NAND SDR Read Status Enhanced Timing Diagram

CLE tCLS tCLH

tCS tCH tCEA
CE
tWP

WE tWP
tALH tALS tALH
tWH
ALE

RE
tDS tDH tREA tRHZ

IO0-7 78h R1 R2 R3 Status

Table 101. HPS NAND DDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200
MT/s.

For specification status, see the Data Sheet Status table

Symbol Description 100 MHz (200 MT/s)

Min Max Unit

tAC Access window of DQ[7:0] from 3 25 ns

CLK

tADL Address cycle to data loading 400 — ns

time

tCADf Command, address, data delay 25 — ns

(fast) (command to command,
address to address, command to
continued...

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Symbol Description 100 MHz (200 MT/s)

Min Max Unit

address, address to command,

command/address to start of
data)

tCADs Command, address, data delay 45 — ns

(slow) (command to command,
address to address, command to
address, address to command,
command/address to start of
data)

tCAH Command/address DQ hold time 2 — ns

tCALH W/R_n, CLE, and ALE hold time 2 — ns

tCALS W/R_n, CLE, and ALE setup time 2 — ns

tCAS Command/address DQ setup 2 — ns

time

tCEH CE_n high hold time 20 — ns

tCH CE_n hold time 2 — ns

tCK(avg) or tCK (169) Average clock cycle time 10 — ns

tCK(abs) Absolute clock period, measured tCK(avg) + tJIT(per) min tCK(avg) + tJIT(per) max ns
from rising edge to the next
consecutive rising edge

tCKH(abs) (170) Clock cycle high 0.43 0.57 tCK

tCKL(abs) (170) Clock cycle low 0.43 0.57 tCK

tCKWR Data output end to W/R_n high RoundUp{[tDQSCK(max) + tCK] / — tCK

tCK}

tCS3 CE_n setup time for data input 75 — ns

and data output after CE_n has
been high for greater than 1 µs
continued...

(169) tCK(avg) is the average clock period over any consecutive 200 cycles window.
(170) tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter.

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Symbol Description 100 MHz (200 MT/s)

Min Max Unit

tCS CE_n setup time 15 — ns

tDH Data hold time 0.9 — ns

tDPZ Data input pause setup time 1.5 — tDSC

tDQSCK Access window of DQS from CLK 3 25 ns

tDQSD W/R_n low to DQS/DQ driven by 0 18 ns

device

tDQSH (171) DQS input high pulse width 0.4 0.6 tCK or tDSC4

tDQSHZ (172) W/R_n high to DQS/DQ tri-state — 20 ns

by device

tDQSL (171) DQS input low pulse width 0.4 0.6 tCK or tDSC4

tDQSQ DQS-DQ skew, DQS to last DQ — 0.85 ns

valid, per access

tDQSS Data input to first DQS latching 0.75 1.25 tCK

transition

tDS Data setup time 0.9 — ns

tDSC DQS cycle time 10 — ns

tDSH DQS falling edge to CLK rising – 0.2 — tCK

hold time

tDSS DQS falling edge to CLK rising – 0.2 — tCK

setup time

tDVW Output data valid window tDVW = tQH – tDQSQ ns

tFEAT Busy time for Set Features and — 1 µs

Get Features

tHP Half-clock period tHP = min(tCKL, tCKH) ns

continued...

(171) tDQSL and tDQSH are relative to tCK when CLK is running. If CLK is stopped during data input, then tDQSL and tDQSH are relative to tDSC.
(172) tDQSHZ is not referenced to a specific voltage level, but specifies when the device output is no longer driving.

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Symbol Description 100 MHz (200 MT/s)

Min Max Unit

tITC Interface and Timing Mode — 1 µs

Change time

tJIT(per) The deviation of a given tCK(abs) –0.5 0.5 ns

from tCK(avg)

tQH DQ-DQS hold, DQS to first DQ to tQH = tHP – tQHS ns

go non-valid, per access

tQHS Data hold skew factor — 1 ns

tRHW Data output cycle to command, 100 — ns

address, or data input cycle

tRR Ready to data output cycle (data 20 — ns

only)

tRST (raw NAND) Device reset time, measured — 15/30/500 µs

from the falling edge of R/B_n to
the rising edge of R/B_n

tRST (EZ NAND)(173) Device reset time, measured — 150/150/500 µs

from the falling edge of R/B_n to
the rising edge of R/B_n

tWB (WE_n high or CLK rising edge) — 100 ns

to SR[6] low

tWHR Command, address, or data 80 — ns

input cycle to data output cycle

tWPRE DQS write preamble 1.5 — tCK

tWPST DQS write postamble 1.5 — tCK

tWRCK W/R_n low to data output cycle 20 — ns

tWW WP_n transition to command 100 — ns

cycle

(173) If the reset is invoked using a Reset (FFh) command then the EZ NAND device has 250 ms to complete the reset operation regardless
of the timing mode. If the reset is invoked using Synchronous Reset (FCh) or a Reset LUN (FAh) command then the values are as
shown.

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Figure 38. NAND DDR Command Cycle Timing Diagram

tCH
tCS
CE_n
tCALS
CLE tCALS tCALH
tCALS tCAD
ALE
tCKL tCKH
CLK
tCK tCAD starts for next
non-idle cycle
W/R_n tCALS tCALH
tDQSHZ

DQS
tCAS tCAH
DQ[7:0] Command

Figure 39. NAND DDR Address Cycle Timing Diagram

tCH
tCS
CE_n
tCALS
CLE
tCAD
tCALS
ALE tCALS tCALH
tCKL tCKH
CLK
tCK tCAD starts for next
non-idle cycle
W/R_n tCALS tCALH
tDQSHZ

DQS
tCAS tCAH
DQ[7:0] Address

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Figure 40. NAND DDR Data Input Cycle Timing Diagram

tCS tCH
CE_n

CLE tCALS tCALH

tCAD
ALE tCALS tCALH
tCKL tCKH
CLK
tCAD starts for next
tCK non-idle cycle
W/R_n
tDQSS tDSH tDSS tDSH tDSH tDSS tDSH tDSS

DQS
tWPRE tDQSH tDQSL tDQSH tDQSL tDQSH tWPST

DQ[7:0] D0 D1 D2 D3 DN-2 DN-1 DN

tDS tDS
tDH tDH

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Figure 41. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped)
A B

tCS tCH
CE_n
tCALS
CLE tCALS tCALH
tCAD
tCALS
ALE tCALS tCALH
tCKL tCKH
CLK
tCK tCAD starts for next
non-idle cycle
W/R_n tCALH tCALS

tDQSS tDSC tDSS tDSH tDSS

DQS
tWPRE tDQSH tDQSL tDQSH tDQSL tDQSH tWPST

DQ[7:0] Dn D1 D2 D3 DN-2 DN-1 DN

tDS tDS
tDH tDH

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Figure 42. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped with Data Pause)
A B

CE_n
tCALS
CLE tCALH
tCALS
ALE tCALH

CLK

W/R_n tCALH
tCALS

tDQSS tDSC tDPZ tDSC tDSS tDSH

DQS
tDQSH tDQSL tDQSH tDQSH tDQSL tDQSH tDQSL tDQSH

DQ[7:0] DM DM+1 DM+2 DM+3 DM+4 DM+5 DM+6 DM+7 DN-2 DN-1 DN
tDS tDS
tDH tDH

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Figure 43. NAND DDR Data Output Cycle Timing Diagram

tCH
tCS
CE_n
tCAD starts for next
non-idle cycle
CLE tCALS tCALH
tCAD

ALE tCALS tCALH

tCKH tCKL
tHP tHP tHP
CLK tHP tHP tHP
tDQSCK tCKWR
tCK
tDQSCK tDQSCK
tCALS tWRCK tDQSCK tDQSCK
W/R_n tDQSCK tCALS tDQSHZ
tDQSD

DQS
tAC tDVW tDVW tDVW tDVW tDVW

DQ[7:0] D0 D1 D2 DN-2 DN-1 DN

tDQSQ tDQSQ tDQSQ tDQSQ
tQH tQH tQH tQH

Don’t Care Data Transitioning Device Driving

Figure 44. NAND DDR W/R_n Timing Diagram

tCALS tCALS
CLK (WE_n)

W/R_n (RE_n)

DQ[7:0]
tDQSD tDQSHZ
DQS

Tri-state Device Driving

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Figure 45. NAND DDR Read Status Including tWHR and tCAD Timing Diagram

A
tCH
tCS
CE_n

tCALS
CLE tCALS tCALH tCALS
tWHR
tCALS tCAD tCAD
ALE tCALS
tCKL tCKH
tHP
CLK tHP
tCK
tCALS tDQSD tDQSCK
W/R_n tCALS tCALH tDQSCK tCALS tDQSHZ
tDQSHZ

DQS
tCAS tCAH tAC tDVW tDVW

DQ[7:0] 70h D0 D0
tDQSQ tDQSQ
tQH tQH

HPS Trace Timing Characteristics

Table 102. Trace Timing Requirements

To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface
offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed
possible. Refer to your trace module data sheet for termination recommendations.

Most trace modules implement programmable clock and data skew to improve trace data timing margins. Alternatively, you can change the clock-to-data timing
relationship with the HPS programmable I/O delay.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Fclk Trace clock frequency — — 200 MHz

Tclk Trace clock period 5 — — ns

continued...

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Symbol Description Min Typ Max Unit

Tclk_jitter Trace clock output jitter — — 2 %

Tdutycycle Trace clock maximum duty 45 50 55 %

cycle

Td Tclk to D0–D15 output data –0.5 — 1.3 ns

delay

Figure 46. Trace Timing Diagram

Clock (DDR)

Trace Data (DDR)

Td

HPS GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock
frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable
GPIO pulse width is 62.5 µs (at 32 kHz).

If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal
is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If
the external signal is more than two clock cycles, the external signal is not filtered.

The GPIO modules provided in the HPS include optional debounce capabilities. The external signal can be debounced to
remove any spurious glitches that are less than one period of the external debouncing clock, gpio_db_clk.

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HPS JTAG Timing Characteristics

Table 103. HPS JTAG Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

fJCP TCK clock frequency — — 24 MHz

tJCP TCK clock period 41.66 — — ns

tJCH TCK clock high time 20 — — ns

tJCL TCK clock low time 20 — — ns

tJPSU (TDI) TDI JTAG port setup time 5 — — ns

tJPSU (TMS) TMS JTAG port setup time 5 — — ns

tJPH JTAG port hold time 0.5 — — ns

tJPCO JTAG port clock to output 0 — 8 ns

tJPZX JTAG port high impedance — — 10 ns

to valid output

tJPXZ JTAG port valid output to — — 10 ns

high impedance

Figure 47. HPS JTAG Timing Diagram

TMS

TDI
tJCP
tJCH tJCL tJPSU tJPH

TCK
tJPZX tJPCO tJPXZ
TDO

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HPS Programmable I/O Timing Characteristics

Table 104. HPS Programmable I/O Delay (Output Path)

For specification status, see the Data Sheet Status table

Name output_val_en output_val Description Min Typ Max Unit

ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. — 0 — ps

AY Bypasses the delay
chain

CHAIN_DELAY 1 0 Intrinsic I/O delay — 0 — ps

+ Minimum + 0 ×
Chain Delay

ONE_CHAIN_DELA 1 1 Intrinsic I/O delay — 208 — ps

Y + Minimum + 1 ×
Chain Delay

TWO_CHAIN_DELA 1 2 Intrinsic I/O delay — 353 — ps

Y + Minimum + 2 ×
Chain Delay

THREE_CHAIN_DEL 1 3 Intrinsic I/O delay — 413 — ps

AY + Minimum + 3 ×
Chain Delay

FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay — 524 — ps

AY + Minimum + 4 ×
Chain Delay

FIVE_CHAIN_DELA 1 5 Intrinsic I/O delay — 623 — ps

Y + Minimum + 5 ×
Chain Delay

SIX_CHAIN_DELAY 1 6 Intrinsic I/O delay — 744 — ps

+ Minimum + 6 ×
Chain Delay

SEVEN_CHAIN_DEL 1 7 Intrinsic I/O delay — 878 — ps

AY + Minimum + 7 ×
Chain Delay

EIGHT_CHAIN_DEL 1 8 Intrinsic I/O delay — 977 — ps

AY + Minimum + 8 ×
Chain Delay
continued...

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Name output_val_en output_val Description Min Typ Max Unit

NINE_CHAIN_DELA 1 9 Intrinsic I/O delay — 1,067 — ps

Y + Minimum + 9 ×
Chain Delay

TEN_CHAIN_DELAY 1 10 Intrinsic I/O delay — 1,170 — ps

+ Minimum + 10 ×
Chain Delay

ELEVEN_CHAIN_DE 1 11 Intrinsic I/O delay — 1,309 — ps

LAY + Minimum + 11 ×
Chain Delay

TWELVE_CHAIN_D 1 12 Intrinsic I/O delay — 1,366 — ps

ELAY + Minimum + 12 ×
Chain Delay

THIRTEEN_CHAIN_ 1 13 Intrinsic I/O delay — 1,499 — ps

DELAY + Minimum + 13 ×
Chain Delay

FOURTEEN_CHAIN 1 14 Intrinsic I/O delay — 1,604 — ps

_DELAY + Minimum + 14 ×
Chain Delay

FIFTEEN_CHAIN_D 1 15 Intrinsic I/O delay — 1,760 — ps

ELAY + Minimum + 15 ×
Chain Delay

— 1 [16:30] INVALID — — — —

— 2 — INVALID — — — —

— 3 [0:15] INVALID — — — —

SIXTEEN_CHAIN_D 3 16 Intrinsic I/O delay — 1,994 — ps

ELAY + Minimum + 16 ×
Chain Delay

SEVENTEEN_CHAIN 3 17 Intrinsic I/O delay — 2,038 — ps

_DELAY + Minimum + 17 ×
Chain Delay

EIGHTEEN_CHAIN_ 3 18 Intrinsic I/O delay — 2,169 — ps

DELAY + Minimum + 18 ×
Chain Delay
continued...

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Name output_val_en output_val Description Min Typ Max Unit

NINETEEN_CHAIN_ 3 19 Intrinsic I/O delay — 2,260 — ps

DELAY + Minimum + 19 ×
Chain Delay

TWENTY_CHAIN_D 3 20 Intrinsic I/O delay — 2,433 — ps

ELAY + Minimum + 20 ×
Chain Delay

TWENTYONE_CHAI 3 21 Intrinsic I/O delay — 2,476 — ps

N_DELAY + Minimum + 21 ×
Chain Delay

TWENTYTWO_CHAI 3 22 Intrinsic I/O delay — 2,645 — ps

N_DELAY + Minimum + 22 ×
Chain Delay

TWENTYTHREE_CH 3 23 Intrinsic I/O delay — 2,684 — ps

AIN_DELAY + Minimum + 23 ×
Chain Delay

TWENTYFOUR_CHA 3 24 Intrinsic I/O delay — 2,858 — ps

IN_DELAY + Minimum + 24 ×
Chain Delay

TWENTYFIVE_CHAI 3 25 Intrinsic I/O delay — 2,907 — ps

N_DELAY + Minimum + 25 ×
Chain Delay

TWENTYSIX_CHAIN 3 26 Intrinsic I/O delay — 3,054 — ps

_DELAY + Minimum + 26 ×
Chain Delay

TWENTYSEVEN_CH 3 27 Intrinsic I/O delay — 3,123 — ps

AIN_DELAY + Minimum + 27 ×
Chain Delay

TWENTYEIGHT_CH 3 28 Intrinsic I/O delay — 3,259 — ps

AIN_DELAY + Minimum + 28 ×
Chain Delay

TWENTYNINE_CHA 3 29 Intrinsic I/O delay — 3,301 — ps

IN_DELAY + Minimum + 29 ×
Chain Delay

THIRTY_CHAIN_DE 3 30 Intrinsic I/O delay — 3,488 — ps

LAY + Minimum + 30 ×
Chain Delay

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Table 105. HPS Programmable I/O Delay (Input Path)

For specification status, see the Data Sheet Status table

Name input_val_en input_val Description Min Typ Max Unit

ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. — 0 — ps

AY Bypasses the delay
chain

CHAIN_DELAY 1 0 Intrinsic I/O delay — 0 — ps

+ Minimum + 0 ×
Chain Delay

ONE_CHAIN_DELA 1 1 Intrinsic I/O delay — 208 — ps

Y + Minimum + 1 ×
Chain Delay

TWO_CHAIN_DELA 1 2 Intrinsic I/O delay — 353 — ps

Y + Minimum + 2 ×
Chain Delay

THREE_CHAIN_DEL 1 3 Intrinsic I/O delay — 413 — ps

AY + Minimum + 3 ×
Chain Delay

FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay — 524 — ps

AY + Minimum + 4 ×
Chain Delay

FIVE_CHAIN_DELA 1 5 Intrinsic I/O delay — 623 — ps

Y + Minimum + 5 ×
Chain Delay

SIX_CHAIN_DELAY 1 6 Intrinsic I/O delay — 744 — ps

+ Minimum + 6 ×
Chain Delay

SEVEN_CHAIN_DEL 1 7 Intrinsic I/O delay — 878 — ps

AY + Minimum + 7 ×
Chain Delay

EIGHT_CHAIN_DEL 1 8 Intrinsic I/O delay — 977 — ps

AY + Minimum + 8 ×
Chain Delay

NINE_CHAIN_DELA 1 9 Intrinsic I/O delay — 1,067 — ps

Y + Minimum + 9 ×
Chain Delay
continued...

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Name input_val_en input_val Description Min Typ Max Unit

TEN_CHAIN_DELAY 1 10 Intrinsic I/O delay — 1,170 — ps

+ Minimum + 10 ×
Chain Delay

ELEVEN_CHAIN_DE 1 11 Intrinsic I/O delay — 1,309 — ps

LAY + Minimum + 11 ×
Chain Delay

TWELVE_CHAIN_D 1 12 Intrinsic I/O delay — 1,366 — ps

ELAY + Minimum + 12 ×
Chain Delay

THIRTEEN_CHAIN_ 1 13 Intrinsic I/O delay — 1,499 — ps

DELAY + Minimum + 13 ×
Chain Delay

FOURTEEN_CHAIN 1 14 Intrinsic I/O delay — 1,604 — ps

_DELAY + Minimum + 14 ×
Chain Delay

FIFTEEN_CHAIN_D 1 15 Intrinsic I/O delay — 1,760 — ps

ELAY + Minimum + 15 ×
Chain Delay

— 1 [16:30] INVALID — — — —

— 2 — INVALID — — — —

— 3 [0:15] INVALID — — — —

SIXTEEN_CHAIN_D 3 16 Intrinsic I/O delay — 1,994 — ps

ELAY + Minimum + 16 ×
Chain Delay

SEVENTEEN_CHAIN 3 17 Intrinsic I/O delay — 2,038 — ps

_DELAY + Minimum + 17 ×
Chain Delay

EIGHTEEN_CHAIN_ 3 18 Intrinsic I/O delay — 2,169 — ps

DELAY + Minimum + 18 ×
Chain Delay

NINETEEN_CHAIN_ 3 19 Intrinsic I/O delay — 2,260 — ps

DELAY + Minimum + 19 ×
Chain Delay
continued...

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Name input_val_en input_val Description Min Typ Max Unit

TWENTY_CHAIN_D 3 20 Intrinsic I/O delay — 2,433 — ps

ELAY + Minimum + 20 ×
Chain Delay

TWENTYONE_CHAI 3 21 Intrinsic I/O delay — 2,476 — ps

N_DELAY + Minimum + 21 ×
Chain Delay

TWENTYTWO_CHAI 3 22 Intrinsic I/O delay — 2,645 — ps

N_DELAY + Minimum + 22 ×
Chain Delay

TWENTYTHREE_CH 3 23 Intrinsic I/O delay — 2,684 — ps

AIN_DELAY + Minimum + 23 ×
Chain Delay

TWENTYFOUR_CHA 3 24 Intrinsic I/O delay — 2,858 — ps

IN_DELAY + Minimum + 24 ×
Chain Delay

TWENTYFIVE_CHAI 3 25 Intrinsic I/O delay — 2,907 — ps

N_DELAY + Minimum + 25 ×
Chain Delay

TWENTYSIX_CHAIN 3 26 Intrinsic I/O delay — 3,054 — ps

_DELAY + Minimum + 26 ×
Chain Delay

TWENTYSEVEN_CH 3 27 Intrinsic I/O delay — 3,123 — ps

AIN_DELAY + Minimum + 27 ×
Chain Delay

TWENTYEIGHT_CH 3 28 Intrinsic I/O delay — 3,259 — ps

AIN_DELAY + Minimum + 28 ×
Chain Delay

TWENTYNINE_CHA 3 29 Intrinsic I/O delay — 3,301 — ps

IN_DELAY + Minimum + 29 ×
Chain Delay

THIRTY_CHAIN_DE 3 30 Intrinsic I/O delay — 3,488 — ps

LAY + Minimum + 30 ×
Chain Delay

You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0
through 47).

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Configuration Specifications

General Configuration Timing Specifications

Table 106. General Configuration Timing Specifications
For specification status, see the Data Sheet Status table

Symbol Description Requirement Unit

Min Max

tCF12ST1 nCONFIG high to nSTATUS high — 20 ms

tCF02ST0 (174) — 400 ms

nCONFIG low to nSTATUS low

tST0 nSTATUS low pulse during 0.5 10 ms

configuration error

tCD2UM (175) — 5 ms
CONF_DONE high to user mode

tST12CF0 Minimum time to drive nCONFIG 0 — ms

from high to low after nSTATUS
transitions from low to high

tST02CF1 Minimum time to drive nCONFIG 0 — ms

from low to high after nSTATUS
transitions from high to low

(174)
You need to drive nCONFIG low pulse by referring to maximum value if nSTATUS cannot be monitored by host.
(175)
This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.

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Figure 48. General Configuration Timing Diagram

tST0 tST12CF0 tCF02ST0 tCD2UM
tST02CF1
Reconfiguration Triggered Reconfiguration Configuration Error Recovered Reconfiguration
tCF12ST1
nCONFIG

nSTATUS

CONF_DONE

INIT_DONE

Configuration_State User Mode Device Clean Idle Configuration Err Configuration Fail Device Clean Idle Configuration Initialization User Mode

POR Specifications
Power-on reset (POR) delay is defined as the delay between last power rail (VCCIO_SDM) monitored by POR circuitry reached
the minimum operating voltage to the time the device is ready to begin configuration.

Table 107. POR Delay Specifications

For specification status, see the Data Sheet Status table

POR Delay Minimum Maximum Unit

AS (Normal mode), AVST ×8, AVST ×16 11.5 20.2 ms

AS (Fast mode) 1.5 7.6 ms

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External Configuration Clock Source Requirements

Table 108. External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements
For specification status, see the Data Sheet Status table

Description External Clock Source Min Typ Max Unit

Clock input frequency(176) Powered by VCCIO_SDM 25/100/125 MHz

Clock input peak-to-peak — — 2 %

period jitter tolerance

Clock input duty cycle 45 50 55 %

JTAG Configuration Timing

Table 109. JTAG Timing Parameters and Values
For specification status, see the Data Sheet Status table

Symbol Description Requirement Unit

Minimum Maximum

tJCP TCK clock period 30 — ns

tJCH TCK clock high time 14 — ns

tJCL TCK clock low time 14 — ns

tJPSU (TDI) (177) 2 — ns

TDI JTAG port setup time

tJPSU (TMS) (177) 3 — ns

TMS JTAG port setup time

tJPH (177) JTAG port hold time 5 — ns

continued...

(176) The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency
on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus Prime software. Other frequencies in the
range are not supported.
(177)
For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.

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Symbol Description Requirement Unit

Minimum Maximum

tJPCO JTAG port clock to output — 7(178) ns

tJPZX JTAG port high impedance to — 14 ns

valid output

tJPXZ JTAG port valid output to high — 14 ns

impedance

Figure 49. JTAG Timing Diagram

TMS

TDI
tJCP
tJCH tJCL tJPSU tJPH

TCK
tJPZX tJPCO tJPXZ
TDO

AS Configuration Timing
Table 110. AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit

Tclk (179) — 6.02 — ns

AS_CLK clock period

Tdutycycle AS_CLK duty cycle 45 50 55 %

continued...

(178) Capacitance loading at 10 pF.

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Symbol Description Minimum Typical Maximum Unit

Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 8.5(180) — — ns

Tdcslst Last AS_CLK edge to AS_nCSO[3:0] 6.8(180) — — ns

deasserted

Tdo (181) –0.6 — 0.6 ns

AS_DATA[3:0] output delay

Text_delay (182) (183) Total external propagation delay on AS signals — — 13.5 ns

(184)

continued...

(179)
AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash
devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash
setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the
Configuration User Guide for the recommended AS_CLK frequency and maximum board loading.
(180) AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
(181)
Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver,
transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash
setup time,
• Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
• Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
(182) Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
• Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
• Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the
minimum and maximum specification values.
• Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
• Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
(183)
Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency.
(184)
Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.

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Symbol Description Minimum Typical Maximum Unit

Tdcsb2b Minimum delay of slave select deassertion 62 — — ns

between two back-to-back transfers

Skew (AS_CLK – Maximum skew tolerance between nCSO and Tsu_ncso – Tdcsfrs < Skew (AS_CLK – AS_nCSO) < AS_CLK/2 + Tdcslst – ns
AS_nCSO) AS_CLK Tho_ncso (185)

Skew (AS_CLK – Maximum skew tolerance between AS_CLK and –AS_CLK/2 + Tdo(max) + Tsu < Skew (AS_CLK – AS_DATA) < AS_CLK/2 ns
AS_DATA) AS_DATA + Tdo(min) – Tho (185)

Figure 50. AS Configuration Serial Output Timing Diagram

Tdcsb2b
Tdcsfrs Tdo (min) Tdcslst
Tdo (max)
nCSO

AS_CLK

AS_DATA OUT0 OUT1 OUTn

(185) • Tsu = Data setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
• Tho = Data hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
• Tdo = AS_DATA[3:0] output delay. Refer to the specification in this table.
• AS_CLK = AS_CLK clock period.
• Tsu_ncso = Chip select setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
• Tho_ncso = Chip select hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
• Tdcsfrs = AS_nCSO[3:0] asserted to first AS_CLK edge. Refer to the specification in this table.
• Tdcslst = Last AS_CLK edge to AS_nCSO[3:0] deasserted. Refer to the specification in this table.

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Figure 51. AS Configuration Serial Input Timing Diagram

Tdcsb2b
nCSO

AS_CLK
Text_delay
AS_DATA IN0 IN1 INn

Avalon Streaming Configuration Timing

Table 111. Avalon Streaming Timing Parameters for ×8 and ×16 Configurations
For specification status, see the Data Sheet Status table

Symbol Description Minimum Unit

tACLKH AVST_CLK high time 3.6 ns

tACLKL AVST_CLK low time 3.6 ns

tACLKP AVST_CLK period 8 ns

tADSU (186) 2.1 ns

AVST_DATA setup time before rising
edge of AVST_CLK

tADH (186) 0.1 ns

AVST_DATA hold time after rising edge of
AVST_CLK

tAVSU AVST_VALID setup time before rising 2.1 ns

edge of AVST_CLK

tAVDH AVST_VALID hold time after rising edge 0 ns

of AVST_CLK

(186) Data sampled by the FPGA (sink) at the next rising clock edge.

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Figure 52. Avalon Streaming Configuration Timing Diagram

tACLKP
tACLKH tACLKL
AVSTx8_CLK
or AVST_CLK
AVST_READY
or AVSTx8_READY tAVSU tAVDH

AVSTx8_VALID
or AVST_VALID
tADSU tADH must deassert
within 6 cycles
AVSTx8_DATA[7:0]
data0 data1 data2 data3
AVST_DATA[15:0]

Configuration Bit Stream Sizes

Table 112. Configuration Bit Stream Sizes

Configuration bit stream sizes shown in this table are based on worst-case scenarios. The sizes are typically substantially smaller because of the use of the Intel
bit stream compression. The Intel bit stream compression efficiency has dependency on your design complexity.

128 Mb quad SPI flash size is adequate to store the periphery image.

For specification status, see the Data Sheet Status table

Variant Compressed Configuration Bit Stream Size (Mbits)

A5E 005, A5E 007 38

A5E 008, A5E 013 62

A5E 043, A5E 052, A5E 065 193

A5D 051, A5D 064 255

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I/O Timing
I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing
analysis. You may generate the I/O timing report manually using the Timing Analyzer.

The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the
design after you complete place-and-route.

Programmable IOE Delay

Table 113. Programmable IOE Delay Specifications
For specification status, see the Data Sheet Status table

Parameter Maximum Minimum Fast Model Slow Model Unit

Offset Offset
–E1V, –I1V –E2V, –I2V –E3V, –I3V –E4S, –I4S –E5S, –I5S –E6S, –I6S,
–E6X, –I6X

Input Delay 63 0 0.062 7.095 7.100 7.105 7.110 7.115 7.120 ns

Chain
(INPUT_DELA
Y_CHAIN)

Output Delay 15 0 0.062 1.925 1.930 1.935 1.940 1.945 1.950 ns

Chain
(OUTPUT_DE
LAY_CHAIN)

Output 15 0 0.062 1.925 1.930 1.935 1.940 1.945 1.950 ns

Enable Delay
Chain
(OUTPUT_EE
NABLE_DELA
Y_CHAIN)

Glossary
Table 114. Glossary
Term Definition

Differential I/O Standards Receiver Input Waveforms

continued...

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Term Definition

Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground

Differential Waveform

VID
p-n=0V
VID

Transmitter Output Waveforms

Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground

Differential Waveform

VOD
p-n=0V
VOD

fHSCLK I/O PLL input clock frequency.

fHSDR LVDS SERDES block—maximum/minimum LVDS data transfer rate

(fHSDR = 1/TUI), non-DPA.

fHSDRDPA LVDS SERDES block—maximum/minimum LVDS data transfer rate

(fHSDRDPA = 1/TUI), DPA.

J (SERDES factor) LVDS SERDES block—deserialization factor (width of parallel data bus).

JTAG Timing Specifications JTAG Timing Specifications:

continued...

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Term Definition

TMS

TDI

t JCP
t JCH t JCL t JPSU tJPH
TCK

tJPZX tJPCO t JPXZ

TDO

RL Receiver differential input discrete resistor (external to the device).

Sampling window (SW) Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold
times determine the ideal strobe position in the sampling window, as shown:
Bit Time

0.5 x TCCS RSKM Sampling Window RSKM 0.5 x TCCS

(SW)

Single-ended voltage referenced I/O standard The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
continued...

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Term Definition

V CCIO

V OH
V IH(AC)
V IH(DC)
V REF
V IL(DC)
V IL(AC)

V OL
V SS

tC High-speed receiver/transmitter input and output clock period.

TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).

tDUTY LVDS SERDES block—duty cycle on high-speed transmitter output clock.

tFALL Signal high-to-low transition time (80–20%).

tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input.

tOUTPJ_IO Period jitter on the GPIO driven by a PLL.

tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL.

tRISE Signal low-to-high transition time (20–80%).

Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).

VCM(DC) DC Common mode input voltage.

VICM Input Common mode voltage—the common mode of the differential signal at the receiver.

VICM(DC) VCM(DC) DC Common mode input voltage.

VID Input differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.

VDIF(AC) AC differential input voltage—minimum AC input differential voltage required for switching.

VDIF(DC) DC differential input voltage—minimum DC input differential voltage required for switching.
continued...

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Term Definition

VIH Voltage input high—the minimum positive voltage applied to the input which is accepted by the device as a logic high.

VIH(AC) High-level AC input voltage.

VIH(DC) High-level DC input voltage.

VIL Voltage input low—the maximum positive voltage applied to the input which is accepted by the device as a logic low.

VIL(AC) Low-level AC input voltage.

VIL(DC) Low-level DC input voltage.

VOCM Output Common mode voltage—the common mode of the differential signal at the transmitter.

VOD Output differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission line at the transmitter.

VSWING Differential input voltage.

VOX Output differential cross point voltage.

VIX(AC) VIX Input differential cross point voltage.

W LVDS SERDES block—Clock Boost Factor.

Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Document Changes
Version

2025.04.07 • Updated the footnote and removed LP mode (HS) label for M20K block in the D-Series FPGAs Memory Block Performance Specifications (M20K Block)
and E-Series FPGAs Memory Block Performance Specifications (M20K Block) tables.
• Updated the transmitter tx Jitter and TCCS specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series
Device Group B FPGAs LVDS SERDES Specifications tables.
• Updated VOD(V) to VOD(DC)(V) in the D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications and E-Series FPGAs MIPI D-PHY High-
Speed I/O Standards Specifications tables.
• Removed QDR-IV XP memory standard in the D-Series FPGAs Memory Standards Supported table.
• Updated the configuration bit stream sizes for A5E005 and A5E007 variants in the Configuration Bit Stream Sizes table.
• Updated specifications for the HPS and SDM I/O Pin Leakage Current table.
• Removed Max and Typ specifications for the HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input table.
• Added notes to the HSIO Single-Ended LVSTL I/O Standards Specifications and HSIO Differential LVSTL I/O Standards Specifications tables.
• Added footnote for AC input voltage Vi (AC) in the Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5V and 3.3 V in HVIO Bank table.
continued...

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Document Changes
Version

• Added note about voltage sensor accuracy specifications in the Voltage Sensor Specifications table.
• Added SPIM_CLK frequency in the SPI Master Timing Requirements and SPI Slave Timing Requirements tables.
• Added USB_CLK clock frequency in the following tables:
— HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
— HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
• Added Serial Clock (SCL) frequency in the HPS I2C Timing Requirements table.
• Added Trace clock frequency and updated clock period in the Trace Timing Requirements table.
• Added TCK clock frequency in the HPS JTAG Timing Requirements table.
• Updated specifications in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables.
• Added footnote for VCO in the -5 and -6 speed grade in the HPS PLL Performance table.
• Added MDC clock frequency in the Management Data Input/Output (MDIO) Timing Requirements table.
• Updated SCL clock period (TCLK) specifications in the HPS I3C Push-Pull Timing Requirements for SDR mode table.
• Added SCL high period (for First Broadcast Address) specification in the HPS I3C Open Drain Timing Requirements table.
• Updated the description of VCCH_SDM in the Recommended Operating Conditions and Absolute Maximum Ratings tables.

2025.01.23 • Updated the 9x9 and 27x27 specifications in the D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks and E-Series FPGAs
DSP Block Performance Specifications for Multiple DSP Blocks) tables.
• Updated Internal VREF specifications for LVSTL700, LVSTL105 and LVSTL11 I/O standards in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and
LVSTL I/O Reference Voltage Specifications table.
• Updated the maximum data rate for True Differential Signaling I/O standards – fHSDR (data rate) when using LVDS SERDES factor J=1 and J=2 in the
D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
• Added the configuration bit stream sizes for A5D 051 and A5D 064 variants in Configuration Bit Stream Sizes table.

2024.11.25 • Updated the minimum value of Text_delay symbol in the AS Timing Parameters table.
• Update the maximum data rate for LVDS SERDES Receiver specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES
Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
• Minor update on the description in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
• Updated the maximum frequency of DDR4 SDRAM Memory Standards in the D-Series FPGAs Memory Standards Supported and E-Series Device Group
B FPGAs Memory Standards Supported tables.
• Minor update in the footnote for the Voltage Sensor Specifications table.
• Updated the fHSDR data rate (without DPA) in SERDES factor J = 4 and 8 specifications in the D-Series and E-Series Device Group A FPGAs LVDS
SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
• Updated the clause used to IEEE 802.3by for 25GAUI-C2C/C2M in the Electrical Compliance List table.
• Updated the Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] (Th) specifications in the HPS USB UPLI Timing Characteristics table.

2024.08.05 • Added note on 100 ohm for VCCIO_PIO in HSIO OCT Without Calibration Resistance Tolerance Specifications table.
• Updated the minimum timing parameters for tADSU and tAVSU symbols in Avalon Streaming Timing Parameters for x8 and x16 Configurations table.
• Updated the specifications in HVIO I/O Pin Leakage Current table.
• Updated the specifications in HVIO Internal Weak Pull-Up and Pull Down Resistor Value table.
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Document Changes
Version

• Updated the specifications in D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O
Standards Specifications tables.
• Updated the specifications in the -E6S, -I6S, -E6X and -I6X speed grade in Programmable IOE Delay Specifications table.
• Updated the LPDDR5 SDRAM Memory Standard paramaters in E-Series Device Group B FPGAs Memory Standards Supported table.
• Added footnote for Receiver DPA mode with J-factor 4 and 8 for all speed grade at maximum corner data rates in the following tables:
— D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
— E-Series Device Group B FPGAs LVDS SERDES Specifications
• Updated the Typical values in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables.
• Updated tINCCJ specifications to ±750 ps in I/O PLL Specifications table.
• Added CML and HSCL as the supported I/O standards in GTS Transceiver and System PLL Reference Clock Input Specifications table.

2024.04.01 Initial release.

2023.08.11 • Updated the D-Series FPGAs Absolute Maximum Ratings table.

— Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
— Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
— Updated VI specifications and footnote.
— Updated IOUT specifications and added footnote.
• Updated the E-Series FPGAs Absolute Maximum Ratings table.
— Updated –6L to –6X speed grade.
— Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
— Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
— Updated VI specifications and footnote.
— Updated IOUT specifications and added footnote.
• Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section and added the following tables:
— Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank
— Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank
• Updated the D-Series FPGAs Recommended Operating Conditions table.
— Updated VCCIO_PIO_SDM specifications.
— Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
— Updated VCCIO_PIO specifications and footnote.
— Updated VI specifications and footnote.
— Added VO specifications for VCCIO_PIO = 1.0 V.
— Updated tRAMP footnote.
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Document Changes
Version

• Updated the E-Series FPGAs Recommended Operating Conditions table.

— Updated –6L to –6X speed grade.
— Updated VCCH_SDM, VCCIO_PIO_SDM, and VCC_IO_SDM specifications.
— Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
— Updated VCCIO_PIO specifications and footnote.
— Updated VI specifications and footnote.
— Added VO specifications for VCCIO_PIO = 1.0 V.
— Updated tRAMP footnote.
• Added footnote to maximum value column in the D-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
• Updated the E-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
— Added footnote to maximum value column.
— Updated –6L to –6X speed grade.
• Updated the HSIO OCT Calibration Accuracy Specifications table.
— Removed 50-Ω RS specification.
— Added footnote to RS and RT.
— Removed DPHY11 I/O standards support.
• Updated the HSIO OCT Without Calibration Resistance Tolerance Specifications table.
— Added 34-Ω and 40-Ω RS specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards.
— Added footnote to RS and RT.
• Added specifications for VCCIO_PIO = 1.0 ±5% and VCCIO_PIO = 1.3 ±5% in the HSIO Internal Weak Pull-Up Resistor table.
• Updated II and IOZ specifications for VI = 0 V to VCCIO_HVIO = 2.5 V in the HVIO I/O Pin Leakage Current table.
• Updated CIO specification in the HVIO Pin Capacitance table.
• Updated VHYS specification for VCCIO_HVIO = 3.3 V in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
• Added specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards in the HSIO Single-Ended I/O Standards Specifications table.
• Updated POD11 and POD12 specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications table.
• Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Single-Ended LVSTL I/O Standards Specifications table.
• Added footnote to SSTL-12, HSTL-12, and HSUL-12 in the HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications table.
• Updated POD11 and POD12 specifications in the HSIO Differential POD I/O Standards Specifications table.
• Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Differential LVSTL I/O Standards Specifications table.
• Updated fIN specifications in the D-Series FPGAs I/O PLL Specifications table.
• Updated the E-Series FPGAs I/O PLL Specifications table.
— Updated fIN specifications.
— Updated –6L to –6X speed grade.
• Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode in the D-Series FPGAs DSP Block Performance
Specifications for Multiple DSP Blocks table.
• Updated –6L to –6X speed grade in the E-Series FPGAs DSP Block Performance Specifications for Single DSP Block table.
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Document Changes
Version

• Updated the E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table.
— Updated –6L to –6X speed grade.
— Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode.
• Updated –6L to –6X speed grade in the E-Series FPGAs Memory Block Performance Specifications table.
• Updated the Voltage Sensor Specifications table.
— Added external reference voltage specifications.
— Updated footnote to voltage sensor accuracy, Vin.
• Split the LVDS SERDES Specifications table into the following tables and updated specifications:
— D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
— E-Series Device Group B FPGAs LVDS SERDES Specifications
• Removed TPP-JITTER-TOLERANCE specifications in the System PLL Reference Clock (Using HVIO) Specifications table.
• Updated the Electrical Compliance List table.
— Updated specification for IEEE 802.3by 111/110 and CPRI V7.0.
— Added footnote to PCIe BASE 4.0 / PIPE 4.4.1 specification.
— Updated specification/clause and protocol for USB.
• Removed the following RMII content:
— Reduced Media Independent Interface (RMII) Clock Timing Requirements table
— RMII TX Timing Requirements table
— RMII TX Timing Diagram
— RMII RX Timing Requirements table
— RMII RX Timing Diagram
• Removed ONFI 3.x, INFI 4.x, NV-DDR2, and NV-DDR3 in the table description of the following tables:
— HPS NAND SDR Timing Requirements
— HPS NAND DDR Timing Requirements
• Updated tJCP, tJCH, tJCL, tJPSU (TMS), tJPH, tJPCO, tJPZX, and tJPXZ specifications in the JTAG Timing Parameters and Values table.
• Updated tACLKH, tACLKL, tACLKP, tADSU, tADH, and tAVSU specifications in the Avalon Streaming Timing Parameters for ×8 and ×16 Configurations table.
• Updated the Programmable IOE Delay Specifications table.
— Added specifications for Output Enable Delay Chain (OUTPUT_EENABLE_DELAY_CHAIN).
— Updated –6L to –6X speed grade.

2023.03.27 Initial release.

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