FPGA Programming Blockset

Getting Started
For FPGA Programming Blockset 2024-A

Release 2024-A – May 2024

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 Contents

Contents

About This Document 5

Brief Introduction to FPGA Programming 7

FPGA Applications vs. Processor Applications................................................... 7
Basic Features of the FPGA Programming Blockset........................................... 8
Software Tools for Working with the FPGA Programming Blockset.... .............. 9

FPGA Programming Blockset Tutorial 13

Introduction to the Tutorial..................................................................................... 14
Working with the Tutorial.............................................................................. 14
Overview of Lessons...................................................................................... 15

Preparatory Steps to Work with the FPGA Programming Blockset........................... 17

Step 1: How to Install the Required Software................................................. 17
Step 2: How to Open the Demo Model......................................................... 21

Lesson 1: Modeling the FPGA Functionality................................................ ............ 22

Overview of Lesson 1.................................................................................... 22
Step 1: How to Select the Framework for the dSPACE Platform..................... 22
Step 2: How to Specify the FPGA Functionality.............................................. 25
Step 3: How to Simulate the FPGA Functionality in Simulink (Offline
Simulation).................................................................................................... 29
Result of Lesson 1......................................................................................... 31

Lesson 2: Adding the Processor Functionality.......................................................... 32

Overview of Lesson 2.................................................................................... 32
Step 1: How to Add a Processor Model......................................................... 32
Step 2: How to Model the Processor Communication.................................... 33
Step 3: How to Simulate the Entire Model..................................................... 35
Result of Lesson 2......................................................................................... 36

Lesson 3: Building the FPGA Application and Using the Build Results in
ConfigurationDesk................................................................................................. 37
Overview of Lesson 3.................................................................................... 37
Step 1: How to Build the FPGA Application................................................... 38
Step 2: How to Prepare the Processor Model Separation................................ 39
Step 3: How to Continue the Development Process in
ConfigurationDesk........................................................................................ 42
Result of Lesson 3......................................................................................... 43

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 Contents

FPGA-Specific Modeling Aspects 45

Timing in FPGA Designs............................................................................. ............ 46
Basics on Timing in FPGA Designs..................................................... ............ 46
Detecting and Fixing Timing Problems........................................................... 47
Signal Path Synchronization........................................................................... 52

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 About This Document

About This Document

Content This guide introduces you to the first steps of graphically implementing an FPGA
application when using a MicroLabBox II, MicroAutoBox III, or SCALEXIO.

Audience profile It is recommended that you have a basic working knowledge of the following:
§ Modeling with Simulink®.
§ Using the AMD® design tools for simulation and debugging.

Symbols dSPACE user documentation uses the following symbols:

Symbol Description
Indicates a hazardous situation that, if not avoided,
V DANGER
will result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V WARNING could result in death or serious injury.
Indicates a hazardous situation that, if not avoided,
V CAUTION could result in minor or moderate injury.
Indicates a hazard that, if not avoided, could result in
NOTICE
property damage.
Indicates important information that you should take
Note
into account to avoid malfunctions.
Indicates tips that can make your work easier.
Tip
Indicates a link that refers to a definition in the
glossary, which you can find at the end of the
document unless stated otherwise.
Follows the document title in a link that refers to
another document.

Naming conventions dSPACE user documentation uses the following naming conventions:

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May 2024 FPGA Programming Blockset Getting Started
 About This Document

%name% Names enclosed in percent signs refer to environment variables for

file and path names.

<> Angle brackets contain wildcard characters or placeholders for variable

file and path names, etc.

Special Windows folders Windows‑based software products use the following special folders:

Common Program Data folder A standard folder for application-specific

program data that is used by all users.
%PROGRAMDATA%\dSPACE\<InstallationGUID>\<ProductName>
or
%PROGRAMDATA%\dSPACE\<ProductName>\<VersionNumber>

Documents folder A standard folder for application‑specific files that are

used by the current user.
%USERPROFILE%\Documents\dSPACE\<ProductName>\<VersionNumber>

Local Program Data folder A standard folder for application-specific

program data that is used by the current user.
%USERPROFILE%\AppData\Local\dSPACE\<InstallationGUID>\
<ProductName>

Accessing dSPACE Help and After you install and decrypt Windows‑based dSPACE software, the
PDF files documentation for the installed products is available in dSPACE Help and as PDF
files.

dSPACE Help (local) You can open your local installation of dSPACE Help:
§ On its home page via Windows Start Menu
§ On specific content using context-sensitive help via F1

PDF files You can access PDF files via the icon in dSPACE Help. The PDF
opens on the first page.

dSPACE Help (Web) Independently of the software installation, you can

access the Web version of dSPACE Help at https://www.dspace.com/go/help.
To access the Web version, you must have a mydSPACE account.
For more information on the mydSPACE registration process, refer to
https://www.dspace.com/faq?097.

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FPGA Programming Blockset Getting Started May 2024
 Brief Introduction to FPGA Programming

Brief Introduction to FPGA Programming

Where to go from here Information in this section

FPGA Applications vs. Processor Applications............................................. 7

The basic differences between FPGA applications and processor
applications.

Basic Features of the FPGA Programming Blockset..................................... 8

Tasks that the FPGA Programming Blockset performs during the
development of the first FPGA application.

Software Tools for Working with the FPGA Programming Blockset............. 9

Information about the required software tools.

FPGA Applications vs. Processor Applications

The basic difference A processor application is mainly a sequence of instructions that is processed
by the central processing unit (CPU) in a sequential manner. In contrast to the
sequential processing of instructions, an FPGA application programs a series of
logic blocks to perform different tasks in parallel. The following illustration shows
the difference.

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 Brief Introduction to FPGA Programming

5 instructions to be looped
are loaded to the RAM

time
The CPU executes one instruction after the other.
After last task is executed, the CPU can output the result.

5 logical functions
instantiated on the FPGA

time
The FPGA can execute all logical functions in parallel.
After all functions have been executed for the first time,
the FPGA can output a result in each step.

Fields of FPGA applications FPGAs are used for the following applications:
§ Applications that require low latencies, for example, digital signal processing or
electric motor control.
§ Flexible hardware interfaces.

Basic Features of the FPGA Programming Blockset

Introduction These are the basic features of the FPGA Programming Blockset to support
MicroLabBox II, MicroAutoBox III, and SCALEXIO systems:
§ Blockset to access the I/O channels and to exchange data with the real-time
processor.
§ Utilities to support the modeling and build workflow.

FPGA modeling The FPGA Programming Blockset is a Simulink blockset for integrating an FPGA
application into a dSPACE system. The blockset is used to model the interfaces of
an FPGA application for the following tasks:
§ Accessing I/O channels to generate and measure external signals.
§ Accessing the internal bus to exchange data with the real-time processor.

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 Software Tools for Working with the FPGA Programming Blockset

The FPGA Programming Blockset does not provide a blockset to model the FPGA
functionality. You model the FPGA functionality with the HDL block library of the
AMD Vitis Model Composer.

FPGA

FPGA Setup

Data output block of

Channel interface output the FPGA
block of the FPGA Programming Blockset Real-time
I/O channels Programming Blockset processor
FPGA_XDATA_WRITE_BL1
FPGA_IO_WRITE_BL1

Data input block of

Channel interface input the FPGA
block of the FPGA Programming Blockset
Programming Blockset FPGA_XDATA_READ_BL1
FPGA_IO_READ_BL1

FPGA functionality

Modeling and build support With the FPGA Programming Blockset, you can synthesize and build FPGA
applications directly from Simulink.

To program the FPGA, the FPGA Programming Blockset makes the build results
available in ConfigurationDesk. ConfigurationDesk is the dSPACE software
product for integrating the FPGA application and processor functionality into
an executable real-time application.

Software Tools for Working with the FPGA Programming Blockset

Introduction To model and build an FPGA application for dSPACE hardware, several software
tools are necessary.

Tools from The MathWorks® MATLAB®, Simulink® and Simulink® CoderTM are required for modeling and
simulating the application.

The following tools from The MathWorks are optional:

§ In addition to the Word Length Calculator of the FPGA Programming Blockset,
you can use the Fixed-Point DesignerTM to optimize the use of fixed-point
data types. Using fixed-point data types reduces the FPGA utilization of your
application.
§ HDL CoderTM can be used to generate VHDL code from parts of the FPGA
model that use Simulink blocks. HDL Coder is not required if you use only
the HDL library of the AMD Vitis Model Composer for the functionality of the
FPGA model.

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 Brief Introduction to FPGA Programming

§ Simulink Report GeneratorTM to generate an HTML model of the FPGA model.

The backup process of the FPGA Programming Blockset can automatically back
up the Simulink model of the entire model. In addition, you can specify that
a web view (HTML model) of the Simulink model is generated to display the
entire model in any Internet browser. Refer to Configuring the Backing Up of
Build Results (FPGA Programming Blockset Guide ).

For compatibility information, refer to Supported software versions on page 11.

Tools from AMD AMD provides several tools for designing applications for AMD FPGAs. The
Vivado® Design Suite covers all the aspects of designing FPGAs. Working with
the FPGA Programming Blockset requires the following products:

Vivado Design Suite The Vivado Design Suite provides a logic design
environment for AMD FPGAs. It contains tools and wizards, for example, for I/O
assignment, power analysis, timing-driven design closure, and HDL simulation.
With the Vivado software, you can build the FPGA application according to the
implemented FPGA model.
The FPGA Programming Blockset uses the Vivado software in the background
without the GUI.

AMD Vitis Model Composer AMD® VitisTM Model Composer for modeling
FPGA applications with Simulink is the unified AMD add-on for MATLAB
Simulink.
The following items of the AMD Vitis Model Composer are required for modeling
and generating the FPGA application:
§ The AMD Vitis Model Composer Blockset.
The AMD Vitis Model Composer Blockset is a Simulink block library that lets
you graphically model FPGA applications. The AMD Vitis Model Composer
Blockset requires a separate license.
The FPGA Programming Blockset supports only the HDL library of the AMD
Vitis Model Composer.
§ The code generator that is included in the AMD Vitis Model Composer.
The code generator is used to generate the HDL code based on blocks of the
FPGA Programming Blockset and the AMD Vitis Model Composer Blockset.

Tip

To use the AMD Vitis Model Composer with a specific MATLAB version, the
-matlab "<matlabdir>" parameter must be specified. You can add this
parameter to the Vitis Model Composer icon on the desktop, for example.

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 Software Tools for Working with the FPGA Programming Blockset

Ordering AMD software Currently, you cannot order the AMD software
from dSPACE.

Supported software versions The following table shows you the supported products and their software
versions for the current version of the FPGA Programming Blockset.

Design Tool Version MATLAB Operating System

Version
AMD Vivado 2023.2 MATLAB Windows operating system that is supported by the RCP and HIL software of
R2022b the current Release.
For a list of supported operating systems, refer to Operating System (New
Features and Migration ). The listed Windows Server operating systems
are not supported by AMD.

For software versions that are compatible with older versions of the FPGA
Programming Blockset, refer to https://www.dspace.com/faq?295.

MATLAB compatibility The limited MATLAB compatibility reflects the

requirements of the AMD Design Tools and its impacts on the building processes
for creating an FPGA application.
In contrast to the FPGA build process, the blocksets and tools for modeling and
building the processor application support the regular MATLAB compatibility of
a dSPACE Release. Therefore, you can extend the MATLAB compatibility if you
model and build the processor application separately from the FPGA application.
The only requirement is that the same dSPACE Release is used to build the FPGA
application and the processor application.
For example: The FPGA application is created with an installation set containing
the current dSPACE Release, Vivado 2023.2, and MATLAB R2022b. You can
transfer and import the generated FPGA application to an installation set
containing the current dSPACE Release and MATLAB R2024a to continue your
work with ConfigurationDesk or the Processor Interface sublibrary of the FPGA
Programming Blockset.

Required blocksets for the The MicroLabBox II, MicroAutoBox III, and SCALEXIO require the dSPACE Model
processor model Interface Package for Simulink to implement the interface between the real-
time processor and the FPGA. The Model Interface Package for Simulink is the
blockset for specifying all interfaces of processor models (behavior models) used
in ConfigurationDesk.

ConfigurationDesk ConfigurationDesk is the required dSPACE implementation tool for the

MicroLabBox II, MicroAutoBox III, or SCALEXIO system. ConfigurationDesk lets
you implement I/O functionality, bus communication, and the connection to
processor models and FPGA applications. ConfigurationDesk is used to build
the real-time application that includes the FPGA application and runs on the
MicroLabBox II/MicroAutoBox III/SCALEXIO.

ControlDesk ControlDesk is the dSPACE software tool for experimenting with a dSPACE
system. It can be used to register the connected hardware, to manage the

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simulation platform, to download the real-time application (processor and FPGA

application), and to control the experiment. The great variety of instruments
allows you to access and visualize variables of the processor application.

Related topics HowTos

Step 1: How to Install the Required Software............................................................................ 17

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 FPGA Programming Blockset Tutorial

FPGA Programming Blockset Tutorial

Where to go from here Information in this section

Introduction to the Tutorial...................................................................... 14

Information on working with the tutorial.

Preparatory Steps to Work with the FPGA Programming Blockset............ 17

Installing the required software and opening the demo model used for
the tutorial.

Lesson 1: Modeling the FPGA Functionality.............................................. 22

Modeling and simulating the FPGA functionality in Simulink.

Lesson 2: Adding the Processor Functionality........................................... 32

Modeling and simulating the processor application including the
communication between the processor model and the FPGA model.

Lesson 3: Building the FPGA Application and Using the Build

Results in ConfigurationDesk................................................................... 37
FPGA application and exporting the build results to ConfigurationDesk.

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Introduction to the Tutorial

Where to go from here Information in this section

Working with the Tutorial........................................................................ 14

Basics on working with the tutorial.

Overview of Lessons................................................................................ 15
Overview of the learning objectives.

Working with the Tutorial

Purpose This tutorial will help you learn the following basic workflows:
§ Modeling the FPGA functionality.
§ Modeling the data exchange between the processor functionality and the
FPGA functionality.
§ Exporting the results to ConfigurationDesk to develop the application further
in ConfigurationDesk.
ConfigurationDesk is the dSPACE software tool to configure and build
applications for the MicroLabBox II, MicroAutoBox III, and SCALEXIO.

Use scenario The tutorial use scenario is a closed-loop system. The controller is implemented
in an FPGA application. The setpoint value is provided by a processor application.
The following illustration shows the signal flow of the use scenario.

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 Introduction to the Tutorial

dSPACE hardware Real-time processor

Analog Digital to
to digital FPGA analog
converter converter

Controlled
device

Order of processing Work through the tutorial sequentially in the specified order. Start with
Preparatory Steps to Work with the FPGA Programming Blockset.

Hardware requirements No hardware is required to complete the tutorial.

Software requirements The FPGA Programming Blockset and the tools from the MathWorks and AMD
are required. The installation of the required software is part of the tutorial.

For an overview on the required software, refer to Software Tools for Working
with the FPGA Programming Blockset on page 9.

Overview of Lessons

Overview The following table gives an overview of lessons. Work through the tutorial
sequentially in the specified order.

Content Lesson
§ Installing the software products required to model and execute an FPGA Preparatory Steps to Work
application on a MicroLabBox II, a MicroAutoBox III, or a SCALEXIO system. with the FPGA Programming
§ Opening the demo model for copying parts of the model used in the tutorial. Blockset
§ Selecting the correct FPGA framework for the dSPACE platform you are using. Lesson 1: Modeling the FPGA
§ Modeling the FPGA functionality in Simulink. Functionality
§ Simulating the FPGA functionality with simulated I/O functionality to detect
modeling errors at an early stage.

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Content Lesson
§ Providing one subsystem for the processor model and one for the FPGA model. Lesson 2: Adding the Processor
§ Modeling the communication within the dSPACE hardware between the real- Functionality
time processor and the FPGA.
§ Verifying the functional behavior of the entire model, including the
communication between the processor model and the FPGA model.
§ Building the FPGA application that programs the FPGA with the specified Lesson 3: Building the FPGA
functionality. Application and Using the Build
§ Preparing the Simulink model so that the framework can separate the processor Results in ConfigurationDesk
model from the FPGA model. The separation is required to use the processor
model with ConfigurationDesk.
§ Exporting the build result to develop the application further in
ConfigurationDesk.

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 Preparatory Steps to Work with the FPGA Programming Blockset

Preparatory Steps to Work with the FPGA Programming

Blockset
Where to go from here Information in this section

Step 1: How to Install the Required Software........................................... 17

Installing the software products required to model and execute an FPGA
application on a MicroLabBox II, a MicroAutoBox III, or a SCALEXIO
system.

Step 2: How to Open the Demo Model.................................................... 21

Opening the demo model for copying parts of the model used in the
tutorial.

Step 1: How to Install the Required Software

Objective Installing the software products required to model and execute an FPGA
application on a MicroLabBox II, a MicroAutoBox III, or a SCALEXIO system.

Supported software versions The FPGA Programming Blockset supports the following versions of the third-
party software products:

Design Tool Version MATLAB Operating System

Version
AMD Vivado 2023.2 MATLAB Windows operating system that is supported by the RCP and HIL software of
R2022b the current Release.
For a list of supported operating systems, refer to Operating System (New
Features and Migration ). The listed Windows Server operating systems
are not supported by AMD.

More information on the For more information on the dSPACE Installation Manager, refer to What Do You
dSPACE Installation Manager Want To Do? (Installing dSPACE Software ).

Preconditions The following preconditions must be fulfilled:

§ Your host PC meets specific requirements. Refer to Appendix: System
Requirements (Installing dSPACE Software ).
§ Your host PC has Internet access during installation of the software.
If you want to install dSPACE software on a PC without an Internet
connection, you have to manually install specific root certificates on the PC

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before installing the dSPACE software. Refer to Installing Root Certificates

Required for Using dSPACE Software (Installing dSPACE Software ).
§ You have unrestricted administrator rights. For other required rights, refer to
Required User Rights (Installing dSPACE Software ).
§ The installation process is not blocked. Refer to Protecting the Installation
Process Against Blocking (Installing dSPACE Software ).
§ You have access to the source media, e.g., dSPACE DVDs or downloaded
installation files.

Method To install the required software

1 Install MATLAB and Simulink. For instruction, refer to
https://www.mathworks.com/help/install/install-products.html.

2 Install the Vivado ML Enterprise edition and the AMD Vitis Model Composer
from AMD.
During the installation, select the following content on the Select Extra
Content page of the Vivado Installer dialog:

For instructions, refer to https://support.xilinx.com/s/article/60117?

language=en_US.

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 Preparatory Steps to Work with the FPGA Programming Blockset

3 Install the dSPACE software:

§ Start dSPACE Setup (Install_Release.exe)

§ Follow the dialog to install dSPACE software.

§ Select the ConfigurationDesk product set.

The FPGA Programming Blockset and the Model Interface Package for
Simulink are part of this product set.
For instructions, refer to How to Install dSPACE Software (Installing dSPACE
Software ).
4 Open the dSPACE Installation Manager and activate the licenses for the
FPGA Programming Blockset, Model Interface Package for Simulink, and
ConfigurationDesk.

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For instructions, refer to License Activation (Working with CodeMeter

Licensing Technology ).
5 Decrypt software archives of your dSPACE installation with the dSPACE
Installation Manager.

For instructions, refer to How to Decrypt Encrypted Archives of dSPACE

Software Installations (Managing dSPACE Software Installations ).

Result You installed the software required to model and execute an FPGA application
on dSPACE hardware.

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 Preparatory Steps to Work with the FPGA Programming Blockset

Step 2: How to Open the Demo Model

Objective Opening the demo model for copying parts of the model used in the tutorial.

Method To open the demo model

1 In the MATLAB Command Window, enter rtifpga.
The FPGA Programming Blockset opens.

If the FPGA Interface is not available, the FPGA license is not activated.
Refer to Step 1: How to Install the Required Software on page 17.

2 Double-click Demos - DemoFPGApipt1 - DS6601_XCKU035.

A dialog opens.
3 Click Yes to copy the demo model file to the current MATLAB folder.
The demo model opens and another dialog opens.
4 Click Yes to copy the ControlDesk experiment to the current folder.
After all files have been copied, the demo model opens.

Result You copied demo model to the current MATLAB folder and opened the model.
You can now copy parts of the demo to use in the tutorial.

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Lesson 1: Modeling the FPGA Functionality

Where to go from here Information in this section

Overview of Lesson 1............................................................................... 22

Information on the purposes of this lesson.

Step 1: How to Select the Framework for the dSPACE Platform..... .......... 22
Selecting the correct FPGA framework for the dSPACE platform you are
using.

Step 2: How to Specify the FPGA Functionality........................................ 25

Modeling the FPGA functionality in Simulink.

Step 3: How to Simulate the FPGA Functionality in Simulink

(Offline Simulation).................................................................................. 29
Simulating the FPGA functionality with simulated I/O functionality to
detect modeling errors at an early stage.

Result of Lesson 1.................................................................................... 31

Summarizes the results of the lesson.

Overview of Lesson 1

Task to be performed This lesson describes how to model the FPGA functionalities, including the
simulation of the modeled functionalities.

What you will learn The lesson includes the following steps:
§ Selecting the correct FPGA framework for the dSPACE platform you are using.
§ Modeling the FPGA functionality in Simulink.
§ Simulating the FPGA functionality with simulated I/O functionality to detect
modeling errors at an early stage.

Step 1: How to Select the Framework for the dSPACE Platform

Objective Selecting the correct FPGA framework for the dSPACE platform you are using.

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 Lesson 1: Modeling the FPGA Functionality

Method To select the framework for the dSPACE platform

1 In the MATLAB Command Window, enter rtifpga.
The FPGA Programming Blockset opens.

If the FPGA Interface is not available, the FPGA license is not activated.
Refer to Step 1: How to Install the Required Software on page 17.
2 Open the FPGA Interface sublibrary.

3 Create a new Simulink model.

4 Drag an FPGA_SETUP_BL block from the FPGA Interface sublibrary to the
Simulink model.
5 In the Simulink model, double-click the FPGA Setup block to open its
dialog.

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6 On the Unit page, select the following settings for the framework:

Note

The tutorial uses the framework for the DS6601 FPGA Base Board.
Complete the tutorial using the DS6601 FPGA Base Board framework
before using the framework that matches your dSPACE hardware.
The framework you use does not affect the steps for programming a
dSPACE FPGA board.

7 Click OK.
8 Save the Simulink model as FPGAGettingStarted_Lesson01.slx.

Result You selected the FPGA framework for the DS6601 FPGA Base Board with an
DS6651 Multi-I/O Module inserted to module slot 1.

The System Generator block is added next to the FPGA Setup block.

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 Lesson 1: Modeling the FPGA Functionality

Note

Do not open and update the System Generator block added by the
FPGA Programming Blockset. The update process will migrate the System
Generator block to the Vitis Model Composer Hub block that is not
compatible to the FPGA Programming Blockset.
For measures if the System Generator block is migrated to the Vitis
Model Composer Hub block, refer to General modeling issues (FPGA
Programming Blockset Guide ).

Step 2: How to Specify the FPGA Functionality

Objective Modeling the FPGA functionality in Simulink.

Method To specify the FPGA functionality

1 Implement the PI-controlled system with blocks from the HDL library of the
AMD Vitis Model Composer.

The following table shows the the blocks used and the specified values of
their block properties. The same controller is used in the DemoFPGApipt1
demo model.

HDL Block Name Set Block Properties1)

AddSub AddSub § Operation: Subtraction
§ Latency: 2
AddSub1 Latency: 2
AddSub2 Basic page:
§ Latency: 0

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HDL Block Name Set Block Properties1)

Output page:
§ Precision: User Defined
§ Arithmetic type: Signed (2's comp)
§ Number of bits: 64
§ Binary point: 40
Constant Kp_const § Constant value: 3.2351
§ Arithmetic type: Unsigned
§ Number of bits: 32
§ Binary point: 18
Ki_const § Constant value: 3000
§ Arithmetic type: Unsigned
§ Number of bits: 32
§ Binary point: 18
CMult CMult § Constant value: 10e-9
§ Number of bits: 48
§ Binary point: 48
§ Latency: 3
Mult Mult Latency: 6
Mult1 Latency: 6
Register Register ‑
1) Keep the default values for all other block properties.

Tip

Press Ctrl + D from time to time to update the diagram. This helps you
to detect modeling errors early.
Check if the messages are plausible. Error messages due to open inputs
at the AddSub blocks can be ignored, for example.

2 From the FPGA Interface sublibrary of the FPGA Programming Blockset,

add an FPGA_IO_WRITE_BL block to the model.

The FPGA_IO_WRITE_BL block lets you access an I/O channel to output the
controlled variable.

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3 Double-click the block to open the block dialog.

The block dialog opens.

4 Configure the block parameters to access an analog output channel.

Dialog Page Set Parameter1)

Unit I/O type: Analog_Mod_1
Select Analog Out - Ch: 17 [Mod: 1]
Parameters Scaling: mV
1) Keep the default values for all other block parameters.
5 Click OK.
The block display changes.

6 Add an FPGA_IO_READ_BL block to the model.

The FPGA_IO_READ_BL block lets you read the actual value of the
controlled system from an analog input channel.
7 Open the block dialog and configure the parameters to access an analog
input channel.

Dialog Page Set Parameter1)

Unit page I/O type: Analog_Mod_1
Select Analog In - Ch: 23 [Mod: 1].

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Dialog Page Set Parameter1)

Parameters page Input range: -10V..+10V
Scaling: mV
1) Keep the default values for all other block parameters.
The block display changes.
8 Add an FPGA_XDATA_READ_BL block to the model and configure the
parameters of the block dialog.

Dialog Page Set Parameter1)

Unit page Access type: Register
Channel name: Set point
Parameters page Binary point position (or fraction width): 0
Format: signed
1) Keep the default values for all other block parameters.
The FPGA_XDATA_READ_BL block lets you read data values from an
application running on the real-time processor.
9 Connect the added blocks as shown in the following illustration. Terminate
the Data New ports of the register and analog input blocks with AMD
Terminator blocks.

Result You modeled the FPGA functionality in Simulink.

To keep the model clear, you can place the controller in a subsystem:
§ Select all AMD blocks.
§ Press Ctrl+G to create a subsystem from the selection.
§ Open the subsystem and rename the inports and outports.
§ Press Ctrl+S to save the model.

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Step 3: How to Simulate the FPGA Functionality in Simulink (Offline

Simulation)

Objective Simulating the FPGA functionality with simulated I/O functionality to detect
modeling errors at an early stage.

Method To simulate the FPGA functionality in Simulink

1 Open the CN subsystem of the DemoFPGApipt1 demo and select the First
Order Lag 1 subsystem.
The First Order Lag 1 subsystem represents the device to be controlled. For
instructions on opening the demo model, refer to Step 2: How to Open the
Demo Model on page 21.

2 Copy the First Order 1 subsystem to your FPGA model and press Ctrl + I
to flip the block.

3 Open the dialog of the Analog Out block.

4 On the Parameters page, select Enable simulation port and click OK.

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The Sim Data simulation port is added to the block.

5 Repeat steps 3 and 4 with the Register In and Analog In blocks.

6 Complete the model as shown in the following illustration.

Steps to complete the model:

§ Rename the First Order Lag 1 subsystem to Simulated Device.
§ Add two Simulink Constant blocks:
§ Set the constant value parameter of one block to 1.
Rename this block to gain.
§ Set the constant value parameter of the other block to 0.001.
Rename this block to time constant.
§ Add a Simulink Signal Generator Simulink block to the model with the
following settings:
§ Waveform parameter: square
§ Amplitude: 1000
The analog I/O blocks are scaled to millivolt, so the amplitude is set to
1,000 mV = 1 V.
§ Frequency: 100
§ Units: Hertz
§ Add a Simulink Constant block to connect the Sim Trigger Input port of
the Analog In block to a defined value.
The triggering of the analog input is set to free-running so that the Sim
Trigger Input port has no influence on the analog-to-digital conversion.
§ Connect the ports.

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 Lesson 1: Modeling the FPGA Functionality

7 In the SIMULATION pane of Simulink, set the Stop Time for a Simulink
simulation to 0.01.

8 Press Ctrl+S to save the model.

9 Add Simulink Scope blocks to the signals you want to check and press
Ctrl + T to start the simulation.

Result You added sinks and sources to the interfaces of the FPGA to simulate the FPGA
functionality. This lets you validate the FPGA functionality and eliminate errors in
an early stage.

Result of Lesson 1

Results You specified the FPGA model for a specific FPGA base board and simulated its
behavior to detect modeling errors at an early stage.

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Lesson 2: Adding the Processor Functionality

Where to go from here Information in this section

Overview of Lesson 2............................................................................... 32

Information on the purposes of this lesson.

Step 1: How to Add a Processor Model.................................................... 32

Providing one subsystem for the processor model and one for the FPGA
model.

Step 2: How to Model the Processor Communication.............................. 33

Modeling the communication within the dSPACE hardware between the
real-time processor and the FPGA.

Step 3: How to Simulate the Entire Model............................................... 35

Verifying the functional behavior of the entire model, including the
communication between the processor model and the FPGA model.

Result of Lesson 2.................................................................................... 36

Summarizes the results of the lesson.

Overview of Lesson 2

Task to be performed This lesson describes how to model the processor functionalities including the
simulation of the entire model.

What you will learn The lesson includes the following steps:
§ Providing one subsystem for the processor model and one for the FPGA
model.
§ Modeling the communication within the dSPACE hardware between the real-
time processor and the FPGA.
§ Verifying the functional behavior of the entire model, including the
communication between the processor model and the FPGA model.

Step 1: How to Add a Processor Model

Objective Providing one subsystem for the processor model and one for the FPGA model.

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Method To add the processor model

1 Select all blocks of the FPGA model. An RTI Data block that was possibly
added automatically does not belong to the FPGA model.

2 Press CTRL + G to create a subsystem from the selection.

3 Rename the created subsystem to FPGA model.

4 Add a new subsystem to the root level of the Simulink model and name it
Processor model.
5 Save the Simulink model as FPGAGettingStarted_Lesson02.slx.

Result You created one Simulink model that includes a subsystem for the processor
functionality and a subsystem for the FPGA functionality.

Step 2: How to Model the Processor Communication

Objective Modeling the communication within the dSPACE hardware between the real-
time processor and the FPGA.

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Method Modeling the processor communication

1 In the FPGA model subsystem, open the dialog of the FPGA Setup block.
2 On the ConfigurationDesk Interface page, click Generate to generate all
processor interface blocks.

A Simulink model opens including the generated Register Out processor

interface block. The generated block is the counterpart to the Register In
FPGA interface block.

3 Move the generated block to the Processor model subsystem.

4 Add a Simulink Signal Generator block to the processor model with the
following settings:
§ Waveform parameter: square
§ Amplitude: 1,000
§ Frequency: 100
§ Units: Hertz
5 Connect the Signal Generator block with the Register Out processor
interface block.
6 Press Ctrl+S to save the model.

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Result You modeled the interface to the FPGA and added the signal generation to the
processor model.

Tip

The dialogs of the interface blocks let you show the corresponding interface
block in the other subsystem.
§ In the Processor model subsystem, open the dialog of the of
the Register Out processor interface block. On the FPGA Block
Connections page of the dialog, the dialog provides a link to the
corresponding interface block in the FPGA model after you clicked the
update button.
§ In the FPGA model subsystem, right-click on the Register In block and
select dSPACE FPGA - Show Corresponding Block.

Step 3: How to Simulate the Entire Model

Objective Verifying the functional behavior of the entire model, including the
communication between the processor model and the FPGA model.

Method To simulate the entire model

1 In the FPGA model subsystem, remove the simulation ports of the

Register In interface block, because the processor model now provides the
required data.
§ Open the Register In block dialog.
§ On the Parameters page, clear Enable simulation port.
§ Press OK.

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2 Remove the Simulink Signal Generator block that was connected to the
simulation port.
3 Press Ctrl+S to save the model.
4 Press Ctrl+T to start the simulation.

Result You simulate the FPGA functionality, the processor communication, and the
processor functionality.

Result of Lesson 2

Results You specified the processor model for the real-time processor of the dSPACE
hardware and simulated the behavior of the entire model to detect modeling
errors at an early stage.

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 Lesson 3: Building the FPGA Application and Using the Build Results in ConfigurationDesk

Lesson 3: Building the FPGA Application and Using the Build

Results in ConfigurationDesk
Where to go from here Information in this section

Overview of Lesson 3............................................................................... 37

Information on the purposes of this lesson.

Step 1: How to Build the FPGA Application.............................................. 38

Building the FPGA application that programs the FPGA with the specified
functionality.

Step 2: How to Prepare the Processor Model Separation.......................... 39

Preparing the Simulink model so that the framework can separate the
processor model from the FPGA model. The separation is required to use
the processor model with ConfigurationDesk.

Step 3: How to Continue the Development Process in

ConfigurationDesk.................................................................................. 42
Exporting the build result to develop the application further in
ConfigurationDesk.

Result of Lesson 3.................................................................................... 43

Summarizes the results of the lesson.

Overview of Lesson 3

Task to be performed This lesson describes how to build the FPGA application to use the build results
in ConfigurationDesk.

What you will learn The lesson includes the following steps:
§ Building the FPGA application that programs the FPGA with the specified
functionality.
§ Preparing the Simulink model so that the framework can separate the
processor model from the FPGA model. The separation is required to use the
processor model with ConfigurationDesk.
§ Exporting the build result to develop the application further in
ConfigurationDesk.

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Step 1: How to Build the FPGA Application

Objective Building the FPGA application that programs the FPGA with the specified
functionality.

Method To build the FPGA application

1 In the FPGA Model subsystem, open the dialog of the FPGA Setup block
and switch to its Parameters page.
2 Set the build parameters:
§ Clear Current directory and enter C:\MyApplication as Build
directory.
§ Select FPGA Build as Model action.
§ Select the maximum number of Thread(s).

3 Click Execute and wait.

Result The build process starts and the FPGA Build Monitor opens. The FPGA Build
Monitor displays status information and the build progress.

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The following illustration shows the basic elements of the FPGA Build Monitor
user interface.

1 2

5 4

Element Name Description

1 Current build Displays and lets you specify the current build folder. After you specified a folder, the
folder working area displays status information on all builds that use the build folder.
2 Open button Lets you open the file explorer to select the build folder to be monitored.
3 Menu button Lets you open/close the command menu.
4 Command Gives you access to the following commands:
menu § Clear Caches: Lets you clear all build caches of the monitored build folder.
§ Sort by: Lets you sort the monitored builds by date, name, or state.
§ Help: Opens the FPGA Programming Blockset Guide PDF. The document provides
information on using the FPGA Build Server and FPGA Build Monitor.
§ About: Opens a dialog with information on the version.
5 Working area Lets you drag & drop a build folder to be monitored. After you drop a folder, the
working area displays status information on all builds that use the build folder.

Step 2: How to Prepare the Processor Model Separation

Objective Preparing the Simulink model so that the framework can separate the processor
model from the FPGA model. The separation is required to use the processor
model with ConfigurationDesk.

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Method To prepare the processor model separation

1 Click Model Port Blocks - Open Model Interface Blockset.

The dSPACE Model Interface Blockset opens.

2 Add the Model Separation Setup block from the Model Interface Package
for Simulink to the top-level of the Simulink model.

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3 Open the dialog of the Model Separation Setup block.

The Model Separation Setup block analyzes the entire model and displays
all top-level subsystems that can be separated as models.

4 Select model.
5 In the Model Name edit field, enter TutorialProcessorModel as the
name for the processor model to be separated.
6 Clear the Model Folder edit field.
The framework saves the separated processor model to the folder of the
entire model.
7 From the Available Subsystems list, select the Processor model

subsystems and click to assign the subsystems to the model entry.

8 Click Save to save the configuration to the source model followed by Close
to close the dialog.
9 Save the Simulink model as FPGAGettingStarted_Lesson03.slx.

Result You prepared the separation of the processor model from the entire model.

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Step 3: How to Continue the Development Process in ConfigurationDesk

Objective Exporting the build result to develop the application further in

ConfigurationDesk. ConfigurationDesk lets you configure the dSPACE hardware
and build the real-time application.

Method To continue the development process in ConfigurationDesk

1 In the FPGA Model subsystem, open the dialog of the FPGA Setup block
and switch to its ConfigurationDesk Interface page.
2 Enter MyFPGAApplication in the Name of (new) project edit field.

3 Click Export to new project and wait.

Result The framework mainly performs the following steps when it exports the build
results and the processor model to ConfigurationDesk:
§ Opens ConfigurationDesk.
§ Creates a new project in ConfigurationDesk.
§ Adds the file path of the current build results to the global user location file.
The global user location file is located at
%LOCALAPPDATA%\dSPACE\ConfigurationDesk\Settings\<ReleaseVersion>
(<ProductVersion>)
When you add the file paths to the global user location file, the
FPGA application is available as FPGA custom function block types in all
ConfigurationDesk projects.
Different versions of FPGAC files differ only in the application ID
(<FPGAApplicationName>_<ApplicationID>.fpgac). When updating the
FPGAC file, the FPGA Programming Blockset adds an application ID so that
ConfigurationDesk can find the latest version first and ignores the other
FPGAC files. In ConfigurationDesk, the Message Viewer displays the found
FPGAC files and the ignored FPGAC files.
The following illustration shows messages of the Message Viewer concerning
the registration of FPGA custom function block types.

§ Adds instances of the added custom function block types to the signal chain.

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The framework performs the following steps only if the processor model can be
separated and the processor interface is implemented:
§ Separates and saves the processor models according to the settings of the
Model Separation Setup block.
In ConfigurationDesk, the processor models are implemented outside
ConfigurationDesk in Simulink models.
§ Exports the model interface of the processor models to ConfigurationDesk.
§ Maps the function ports of the added FPGA custom function blocks to the
model ports of the processor model (behavior model).

After the export process has been finished, you can display the resulting signal
chain in ConfigurationDesk.

Next steps In ConfigurationDesk, you configure the hardware assignment and you can build
the real-time application that runs on the dSPACE hardware to execute the
specified functionality.

To familiarize with the workflow in ConfigurationDesk, refer to

ConfigurationDesk Tutorial Starting with Simulink .

Result of Lesson 3

Results You built the FPGA application and you made the build results and the processor
model available in ConfigurationDesk. In ConfigurationDesk, you can implement
the application on dSPACE hardware and build the the real-time application.

ConfigurationDesk lets you download and run the real-time application on the
dSPACE hardware.

Next steps The following tutorials make you familiar with the dSPACE tools for building and
downloading real-time applications and experimenting with them.
§ To familiarize with the basic steps in ConfigurationDesk, refer to
ConfigurationDesk Tutorial Starting with Simulink .

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§ For basic practices with ControlDesk, refer to Introduction to the Measurement

and Recording Tutorial (ControlDesk Measurement and Recording ).

Tip

The FPGA demos provided by the FPGA Programming Blockset include

ControlDesk experiments for the FPGA demo applications.

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 FPGA-Specific Modeling Aspects

FPGA-Specific Modeling Aspects

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Timing in FPGA Designs

Where to go from here Information in this section

Basics on Timing in FPGA Designs............................................................ 46

Basic terms and definitions required to understand timing in FPGA
designs.

Detecting and Fixing Timing Problems..................................................... 47

Using tools to detect timing problems and measures to correct them.

Signal Path Synchronization..................................................................... 52

Method for synchronous processing of signals.

Basics on Timing in FPGA Designs

Introduction An FPGA processes signals in parallel, so timing is critical for the reliable
processing of signals. To be able to control the timing of a signal, the FPGA
uses flip-flops to hold the state of signals. Flip-flops are also known as registers.

Basic information on flip-flops The following illustration shows a D-flip-flop (DFF) and its signals as an example.

D Q Clk

CE D
Clk
Q
DFF

Port Description
D Data input
Q Data output
Clk Clock input
CE Chip enable

The state of the data output changes synchronously to the clock input: With the
rising edge of the clock, the flip-flop outputs the state of the data input. The
chip enable port enables the chip.

The following terms are important for the timing of FPGA designs.

Setup time This is the time for which the data input signal must be stable
before the clock signal rises from low to high.

Hold time This is the time for which the data input signal must be stable
after the clock signal rises from low to high.

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Propagation delay The propagation delay is the time a signals requires from
one flip-flop to the next.
The propagation delay depends on the used logic levels and the routing of the
signals.

Metastability FPGA signals are electrical signals that take time to change
their state. This is critical when the data input signal changes close to a rising
edge of the clock signal. To have a reliable output stage, the data input signal
must be stable when the clock signal rises from low to high. Otherwise, the state
of the data output is unknown or can even oscillate.

FPGA timing In FPGA logic, timing is always measured between two flip-flops. If a signal does
not make its way through the combinatorial logic (i.e., all operations with latency
0) in the clock period, a timing error occurs.

The following illustration shows an example.

C Q C Q
12 ns
D D
DFF Combinatorial logic DFF

10 ns

For a reliable transmission, the data signal must reach the data input of the
receiving flip-flop early enough and with a stable signal level.

Detecting and Fixing Timing Problems

Introduction The build process automatically starts a timing analysis of the entire FPGA
application including the framework for the used platform. In the MATLAB
Command Window, the build process outputs links to the results of the analysis.

Depending on your preferences and the build FPGA model, click one of the
following links to the results of the timing analysis:
§ Show Timing Report of complete FPGA:
Opens the Vivado Timing Analyzer to show the results. The Vivado Timing
Analyzer shows only the signal paths that are modeled with the HDL library of
the AMD Vitis Model Composer. The Vivado Timing Analyzer does not show
signal paths that are modeled with Simulink blocks.
§ dSPACE Timing Analyzer:
Opens the dSPACE Timing Analyzer to show FPGA timing failures
independently of the used blockset, including FPGA subsystems based
on Simulink blocks (HDL coder subsystems). For more information, refer
to Features of the dSPACE Timing Analyzer (FPGA Programming Blockset
Guide ).

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dSPACE Timing Analyzer The dSPACE Timing Analyzer has the following elements.

Element Name Description

1 Status Shows the result of the timing analysis:
§ Green: Timing passed.
§ Red: Timing failed.
2 Signal Shows the most critical FPGA signal paths of the built FPGA application:
paths § Slack: Timing reserve of the signal paths. Negative values indicate the lack of time.
table
§ Source: Block at the starting point of the timing path.
§ Destination: Block at the end point of the timing path.
If the Source and Destination blocks of the signal path are <…>/FPGA_SETUP_BL1, the
path is in the dSPACE framework. Paths with little slack can be located there. However, the
framework should not generate timing errors (Slack < 0 ns) below 70% FPGA utilization.
3 Details Details on the selected path in the signal paths table.
pane § Slack: Timing reserve of the signal paths. Negative values indicate the lack of time.
§ Requirement: Maximum possible delay of the signal path.
§ Delay: Sum of logic delay and routing delay.
§ Logic Delay: Delay caused by the block logic.
§ Route Delay: Delay caused by routing of the signal in the FPGA.
4 Path tab Details on the blocks of the selected signal path.
§ Parent Subsystem: Path to the subsystem that includes all blocks of the selected signal path.
§ Delay: Logic and routing delay of a block in the FPGA model.
§ Block: Path to the block in the FPGA model relative to the parent subsystem.

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Element Name Description

Tip

Double-click a block to highlight the block in the FPGA model.

5 Report Detailed timing report on the selected signal path.

tab

Vivado Timing Analyzer The timing analyzer shows the timing paths. The timing analyzer starts with the
slowest timing path.

The table shows the 50 signal paths where timing is tightest. To avoid timing
errors, you must ensure that the timing is not too tight. If a path delay is greater
than the FPGA sample time, the actual path is marked in red.

The following table shows a description of the columns:

Column Description
Slack Timing reserve.
Delay Sum of logic delay and routing delay.
Logic Delay Delay caused by the logic.
Routing Delay Delay caused by routing.
Levels of Logic Number of serial logic operations on the timing path
between the source and destination flip-flop.
Source Flip-flop at the starting point of the timing path.
Destination Flip-flop at the end point of the timing path.
Source Clock Clock of the source flip-flop.
Destination Clock Clock of the destination flip-flop.
Path Constraints Specifies the clock period in ns.

If the Source and Destination blocks of the signal path are <…
>/FPGA_SETUP_BL1, the path is in the dSPACE framework. Paths with little slack

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can be located there. However, the framework should not generate timing errors
(Slack < 0 ns) below 70% FPGA utilization.

Fixing timing problems Too many levels of logic in a signal path result in long propagation delays, which
causes timing problems.

C Q C Q
12 ns
D D
DFF Combinatorial logic DFF

10 ns

To fix timing problems, you can do the following:

§ Break up your logic into different parts (pipelining). Refer to Pipelining on
page 50.
§ Analyze and reduce the number of logic levels to be more efficient.
For example: If the multiplication of signals leads to timing problems, reduce
the bit width of the signals, for example, use a 16-bit data type instead of a
32-bit data type. The smaller the bit width, the fewer logic levels are needed.
§ If the time resolution is not critical, you can downsample the clock frequency
(multi-cycle paths). Refer to Downsampling on page 51.

Pipelining The following methods can be used for pipelining.

Adding additional latency Most blocks of the HDL library of the AMD Vitis
Model Composer let you add additional latency in the block parameters dialog.
The Model Composer usually implements additional latency by adding a shift
register at the output of the block. The added shift register is based on flip-flops
and breaks up the logic in two timing paths.

Adding additional registers To break up the logic, you can add an

additional registers (flip-flops) to the logic to divide a big logic in two little logics,
for example, by adding an AMD Delay block.

100 MHz

C Q C Q C Q
6 ns 6 ns
D D D
DFF Combinatorial logic DFF Combinatorial logic DFF

10 ns

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Downsampling The following illustration shows the usual mechanism of downsampled paths.
As an example, the combinatorial logic has a latency of 42 ns. The signal path
is downsampled from 100 MHz to 20 MHz. You can do this, for example, by
adding a AMD Down Sample block at the beginning of the path and an Up
Sample block at the end. The added AMD blocks are based on D flip-flops.

100 MHz

C Q C Q
CE 42 ns CE
D D
DFF Combinatorial logic DFF

50 ns

For more information, refer to Notes on Using Multicycle Paths (FPGA

Programming Blockset Guide ).

For the sampling rate, follow generally accepted FPGA design rules to ensure a
stable and reliable FPGA application.

Verifying the measures To verify the measures, you can execute the timing analysis from the
FPGA_Setup_BL block dialog before you build the FPGA application. This timing
analysis considers only the signal paths that you model with the HDL library of
the AMD Vitis Model Composer. If you fix timing errors in these signal paths, you
can check if the measures to avoid timing errors are effective.

If you fix timing errors in a signal path using Simulink blocks, you have to build
the FPGA application to check if the measures are effective.

More information For more information on timing analysis and fixing timing problems,
refer to https://www.xilinx.com/support/documentation-navigation/design-
hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html.

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Related topics Basics

Notes on Using Multicycle Paths (FPGA Programming Blockset Guide )

Signal Path Synchronization

Introduction If different signal paths have different lengths, the resulting signals are available
at different points in time. Synchronous signals become asynchronous due to
different signal paths. This might cause unexpected behavior of your application.

For example: The values of three signals are processed to one signal as shown in
the following illustration.

A
3-cycle
delay
B
3-cycle
Logic delay Out
C
Logic

Detecting asynchronous paths If synchronous signals are required for the application, ensure that the signal
paths are synchronized. You can do this, for example, by executing an offline
simulation to visualize the signals and detect asynchronous paths. Refer to
Step 3: How to Simulate the FPGA Functionality in Simulink (Offline Simulation)
on page 29.

Synchronizing signal paths To synchronize the length of the signal paths of different signals, you can add
delay blocks. With delay blocks, you can extend shorter signal paths to the
length of the longest signal path.

A
3-cycle
delay
B
Logic
Out

3-cycle
C delay Logic

Delay

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