S32k312evb Q172 HW Um
S32k312evb Q172 HW Um
S32K312EVBQ172ND
S32K312EVB-Q172
NXP Semiconductors S32K312EVB-Q172 HWUM
S32K312EVB-Q172 | S32K312EVBQ172ND - Hardware User Manual
1 Table of contents
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CD Compact Disk
CMOS Complementary Metal Oxide Semiconductor
CPLD Custom Programmed Logic Devices
CPU Central Processing Unit
CSI Camera Sensor Imaging
CSPI Serial Peripheral Interface
DDR Double Data Rate
DIP Dual In-line Package
EEPROM Electrically Erasable Programmable Read Only Memory
EPROM Erasable Programmable Read Only Memory
GPIO General Purpose Input/output
GPO General Purpose Output
I2C Inter-Integrated Circuit
ICE In-Circuit Emulator
I/O Input/output
JTAG Joint Test Access Group
LAN Local Area Network
LCD Liquid Crystal Display
LED Light Emitting Diode
MB Megabyte
MCU Microcontroller Unit
MMC Multi-Media Card
MCP Multi-chip product
MS Memory Stick
NVRAM Non-volatile Random-Access Memory
PC Personal Computer
PCB Printed Circuit Board
PHY Physical interface
POR Power on Reset
PSRAM Pseudo Random Access Memory
PWR Power
PWM Pulse Width Modulation
QVGA Graphics Adapter
RAM Random Access Memory
SD SanDisk (Smart Media)
SDRAM Synchronous Dynamic Random-Access Memory
SI System International (international system of units and measures)
SIMM Single In-Line Memory Module
SPST Single Pole Single Throw
TFT Thin Film Transistor
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus.
HW Hardware.
POP Populate – Component placed
DNP Do not populate – Component removed
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172HDQFP
4 S32K312EVB-Q172 - Features
IMPORTANT
• Before the S32K312 Customer Evaluation Board is used or power is applied, please fully read
this user manual. An incorrect configuration in the board may cause a damage irreparable on the
component, MCU or EVB. Power must be removed from the EVB prior to:
- Removing or placing some component or measurement
- Re-configuring the board jumpers
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MCU
Power Supply
● ● VDD_HV_A_MCU +5.0V The VDDA_HV_A domain is connected to +5.0V–
Switching Power Supply
OnBoard
Debugg
● - PTA15 PTA15/LPUART6_RX is routed to OpenSDA for serial
interface
PTA16 PTA16/LPUART6_TX is routed to OpenSDA for serial
interface
CAN
Interface
● ● TJA1043/CAN0 PTA6 PTA26 is routed to the CAN0_RX signal
PTA7 PTA27 is routed to the CAN0_TX
PTC23 PTC23 is routed to the CAN0_ERRN
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ARDUINO
● ● - -
6 S32K312EVB-Q172 - Startup
Follow these steps to connect and power on the board
1. Carefully unpack the S32K312EVB-Q172 and observe ESD preventive measures while handling the K3 development board.
2. Connect necessary cables between host PC and EVB board prior to applying power to the EVB.
3. The power-ON sequence for the EVB must be as follows:
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- The power switch -SW1 must be in OFF position before to the EVB be connected to an external power supply.
a)
- Once the power switch -SW1 is in OFF position, then the EVB can be connected to an external power supply.
b)
4. When power is applied to the EVB, three orange LED’s adjacent to the voltage regulators show the presence of the supply
voltages as follows:
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Figure 3 . S32 K312 EVB- Q172 – Power supply Input and LED power indicators
If no LED’s are illuminated when power is applied to the EVB and the regulators are correctly enabled using the appropriate
jumpers, it is possible that either power supply is not connected properly, or the voltage level is lower that the specified [+12.0V
to ≥2Amps].
Note that the fuse will not protect against one of the EVB regulators being shorted. If this happens, damage is likely to occ ur to
the EVB and / or components.
5. The board is ready to use now.
The EVB requires an external power supply voltage of between to +12V/≥2A. This allows the EVB to be easily used in a
vehicle if required. The 12v input is on the EVB is used to supply a FS26/SBC – U1, the power management IC controller
provides +5.0V, +3.3V and +1.5V, for the different power configurations of VDD_HV_A, VDD_HV_B, V15 and other
interfaces.
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7.1 S32K312EVB-Q172 - Main Power Supply
V+ (+12Volts).
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J5 1-2 The R297 is selected for the divider voltage, +8.0V is applied on
VDEBUG pin to set the FS26-SBC on MCU Flash Mode. In this
mode device power up sequence starts with debug mode
enabled and can be used during customer production process to
flash MCU without need of WD refresh. After ~80ms once the
SW1 is in ON-position the VDEBUG pin will be switching to a low
voltage (GND) due to the RC delay circuitry and Q18
Debug J1 1-2
Mode The R2 resistor to VBATP (VBAT protected +12.0V) is routed as
pull-up to the VDEBUG Pin. This is a common pull-up resistor for
the 2 voltage divider configurations, with R6 or R297.
J5 2-3 The R297 is selected for the divider voltage, +5.0V is applied on
VDEBUG pin to set the FS26-SBC on Debug Mode, voltage must
be removed from debug pin in order to start power up sequence.
In this mode Watchdog refresh is not needed. After ~80ms once
the SW1 is in ON-position the VDEBUG pin will be switching to a
low voltage (GND) due to the RC delay circuitry and Q18.
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Reference Jumper Position Description Comments
Normal Mode J1 OPEN In this mode the FS26 can enter Normal mode by configuring the
init_fs window and sending properly serviced watchdog refresh by
SPI. Please review the FS26 documentation.
J5 OPEN
All change of jumpers must be done once the EVB is unpowered from J3 and J5 as MANDATORY
J22
SILK = P5V0
JUMPER(Default) = 1-2 TP26
HDR 1X3 FS26_VLDO1 SILK = P5V0 P5V0 P5V0_OSDA_OUT
1
5V0 OUTPUT 2
3
Figure 6. S32K312 EVB-Q172 – General jumper for the P5V0 (+5.0 V) reference
J22 The +5.0V output of the FS26x SBC [FS26_VLDO1] is routed Default closed
to the main P5V0 domain (+5.0V for all board).
1-2
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J26 TP29
HDR1X2 FS26_VLDO2 SILK = P3V3 P3V3
1
3 V3 OUTPUT 2
SILK = P3V3
JUMPER(Default) = 1-2 Closed
Figure 7. S32K312 EVB-Q172 – General jumper for the P3V3 (+3.3V) reference
J26 1-2 The +3.3V Switching power supply is routed to the Default closed
main P3V3 domain (+3.3V for all board).
J18 VDD_HV_A
HDR 1X3 S32K3XX Primary I/Os Supply
SILK = VDD_HV_A
JUMPER(Default) = 1-2 Closed P5V0 P3V3 VDD_HV_A
Voltage Domain VDD_HV_A_MCU
1
2 VDD_HV_A R303 0.5 VDD_HV_A_MCU
3
J10
HDR1X2
JUMPER(Default) = 1-2 Closed
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Table 6. S32K312EVB-Q172 – VDD_HV_A
Reference Jumper Position Description Comments
J18 1-2 P5V0 (+5.0V from the FS26) is selected for the Default closed
VDD_HV_A_MCU reference
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8.2 On-board Debugger
The EVB incorporates an On-Board Debugger embedded well as JTAG connectors. It bridges serial and debug communications between
a USB host and an embedded target processor.
Reference/
Connector Component Description
10-Pin Cortex J50 The Cortex Debug Connector provides support for Serial Wire and JTAG interface
Debug + ETM modes in a very small, and low cost 10-pin (0.05") connector. This new connector
Connector style provides access to all SWD, SWV, and JTAG signals available on a Cortex-M
device.
A 10-pin header (Samtec FTSH-105-01) is specified with these dimensions: 0.25" x
0.188" (6.35 mm x 4.78 mm).
NOTE - JTAG – TRACE Signals
Due that the MCU ports used for the trace signals also are shared with other
interfaces. It is important to isolate these signals/interfaces for the J4-Cortex Debug
D ETM connector.
All TRACE signals are DISABLED as default configuration. In order to enable the TRACE interface, the MCU signals routed to the QSPIA interface
must be disabled and isolated.
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The pinout of these headers is shown below and is also detailed on the PCB silkscreen.
J23 1 GND
2 GND
3 NC
4 NC
5 VBAT
6 VBAT
7 LIN2_OUT
8 LIN1_OUT
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LIN MCU
Signal Name Comment/Description
Interface Port
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CAN MCU
Signal Name Comment/Description
Interface Port
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1. There are zero-ohm resistors on the direct connections between each USER_SWx and the MCU pins. These can be removed
if required to isolate or change the User Switch from the default MCU pin.
NOTE
1. There are zero-ohm resistors on the direct connections between each USERSW and the MCU pins. These can be removed if required
to isolate or change the User Switch from the default MCU pin.
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Interface
Reference Position Description / Comments
13 S32K312EVB-Q172 – Errata
For use I2C in this EVB is mandatory use external pull-ups resistors due this board doesn’t include this feature in order to
the final user can select the value of the resistors according to their application and configurations for this
communication protocol. The user must ensure the pull-up resistor are connected to the same voltage reference than
VDD_HV_A and PTC6 (J4-25) and TPTC7 (J4-28) respectively.
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A2 09/2023 51972 A Fixed all 20-pin references on the debug Efren Diaz
connector, changed for 10-pin connector that is
actually on the board.
A3 29/01/2024 51972 A Errata chapter added related to I2C required Luis Rico
external pull up resistors
Incorrect description of MCU corrected
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15 Legal Information
15.1 Definitions minimize the risks associated with their applications and
products. NXP Semiconductors does not accept any liability
Draft — A draft status on a document indicates that the
related to any default, damage, costs or problem which is
content is still under internal review and subject to formal
based on any weakness or default in the customer’s
approval, which may result in modifications or additions. NXP
applications or products, or the application or use by
Semiconductors does not give any representations or
customer’s third-party customer(s). Customer is responsible
warranties as to the accuracy or completeness of information
for doing all necessary testing for the customer’s applications
included in a draft version of a document and shall have no
and products using NXP Semiconductors products in order to
liability for the consequences of use of such information . avoid a default of the applications and the products or of the
application or use by customer’s third-party customer(s). NXP
does not accept any liability in this respect.
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