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Programmable Timer 8254

The document discusses the INTEL 8254 programmable timer, which features three independent counters and operates at a maximum clock frequency of 10 MHz. It details the timer's applications, interfacing with the 8086 processor, programming methods, and six operational modes. Additionally, it contrasts the 8254 with the 8253 timer, highlighting their compatibility and differences in clock frequency.

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10 views9 pages

Programmable Timer 8254

The document discusses the INTEL 8254 programmable timer, which features three independent counters and operates at a maximum clock frequency of 10 MHz. It details the timer's applications, interfacing with the 8086 processor, programming methods, and six operational modes. Additionally, it contrasts the 8254 with the 8253 timer, highlighting their compatibility and differences in clock frequency.

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b53904537
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© © All Rights Reserved
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Note: Another timer released by INTEL is 8253 which is a low clock

version of the 8254. The maximum input clock frequency to 8253 is 2.6
MHz. The 8253 and 8254 are pin to pin compatible and functionally
same except the clock frequency.

Programmable timer - INTEL 8254


 The INTEL 8254 timer has three independent counters. In each
counter a count value can be loaded and the count value can be
decremented by applying a clock signal.
 At the end of count, each counter will generate an output which
can be used as an interrupt to the processor to initiate the time-
based activity. Some of the applications of a programmable timer
are given below

1. The timer can interrupt a time-sharing operating system at


specified intervals so that it can switch programs.

2. The timer can send timing signals at periodic intervals to IO


devices. (For e.g., start of conversion signal to ADC.)

3. The timer can be used as a baud rate generator. (For e.g., the timer
can be used as a clock divider to divide the processor clock to
desired the frequency for TxC and RxC of USART-8251A.)

4. The timer can be used to measure the time between external


events.
5. The timer can be used as an external event counter to count
repetitive external operations and inform the count value to the
processor.
6. The timer can be used to initiate an activity through the interrupt
after a programmed number of external events have occurred.
 The 8254 is a 24-pin IC packed in DIP and requires a single +5-V
supply. The pin configuration of 8254 is shown in Fig.(a). The
functional block diagram of 8254 is shown in Fig. (b).

Fig.(a) Pin configuration of 8254

 The 8254 has three independent 16-bit counters, which can be


programmed to work in any one of the possible six modes.
 Each counter has a clock input, gate input and counter output. To
operate a counter, a count value has to be loaded in count register,
gate should be tied high and a clock signal should be applied
through the clock input.

Fig. (b) : Functional block diagram of an 8254 timer.

 The counter counts by decrementing the count value by one in


each cycle of the clock signal and generates an output depending
on the mode of operation. The maximum input clock frequency for
8254 is 10 MHz.

 The 8254 has eight data lines which can be used for
communication with the processor. The control words and
count values are written into 8254 registers through the data
bus buffer.
 The 𝐶𝑆 is used to select the chip. The address lines A0 and A1
are used to select any one of the four internal devices as
shown in Table-below. The control signals 𝑅𝐷 and 𝑊𝑅 are
used by the processor to perform read/write operation. The
processor can read the count value in the count register
with/without stopping the counter at any time.

Interfacing 8254 with 8086 Processor

 A simple schematic for interfacing the 8254 with 8086 processor is


shown in Fig.(c). The 8254 can be either memory-mapped or IO-
mapped in the system.
 In the schematic shown in Fig.(c), the 8254 is IO-mapped in the
system with even addresses.
 The chip select signals for IO-mapped devices are generated by
using a 3-to-8 decoder. The address lines A5, A6 and A7 are
decoded to generate eight chip select signals (IOCS-0 to IOCS-7)
and in this, the chip
Fig. 7.48 : Interfacing of 8254 with 8086 processor.

select IOCS-5 is used to select 8254. The address line A0 and the control
signal M/𝐼𝑂 are used to enable the decoder.
 The address lines A1 and A2 of 8086 are connected to A0 and A1 of
8254 to provide the internal addresses. The IO addresses allotted to
the internal devices of 8254 are listed in Table - 7.17. The data
lines D0 -D7 are connected to D0-D7 of the processor, and 𝑅𝐷 and
𝑊𝑅 signals of 8254 are connected to the 𝑅𝐷 and 𝑊𝑅 of the
processor respectively to achieve parallel data transfer.
TABLE: IO ADDRESSES OF 8254
 The clock signals required for the counters can be obtained either
from the processor clock or from the Peripherals clock (PCLK)
supplied by the clock generator 8284. The clock signals from 8284
can also be divided to lower values by using clock divider circuits
and then applied to the clock input of counters

Programming 8254

 Each counter of 8254 can be individually programmed by writing a


control word followed by the count value. The format of control
word is shown in Fig. (d).

Fig.(d) : Format of control word for timer 8254.

 The bit B0 (BCD) of the control word is used to select BCD or


binary count and the bits B1 to B3 (M0, M1 and M2) are used to
select the mode of operation for the counter specified by bits B 6
and B7 of control word.
 Take in mind that for each counter separate control word has to be
sent to the same control register address. The 8254 identifies the
control word for a particular counter from bits B6 and B7 of the
control word.
 The bits B4 and B5 are used for read/write command. These bits are
programmed for reading/writing the 16-bit count value in a proper
order. If the count value is read without stopping the counter, then
the count value may change between reading the LSB and MSB.
To avoid this, the counter latch command can be used to latch the
count value to an internal latch available at the output of each
counter before the read operation.

 Alternatively, a separate read-back control word is available for


latching the count value in 8254. (This control word is not
available in 8253.) The format of the read-back control word of
8254 is shown in Fig.(e). This control word has to be sent to the
same control register address before the read operation to latch the
count value. The control register identifies this control word from
the value of bits B6 and B7.

Fig. (e) : Format of read-back control word of 8254

 The read-back control word can be used to latch one or all the
counters by sending a single control word. This control word is
also used to latch the status register to the output latch of the
counters, so that the status registers can be read by using the
respective counter address. At any one time, we can latch either the
count value by programming the bit B5 as zero or latch the status
register by programming the bit B4 as zero.

 The format of the status register of each counter is shown in Fig.


(f). The status word of a counter can be read to check the
programmed status of the counter and also to verify whether the
count value has reached terminal count, i.e., zero or not.

Operating Modes of 8254


The 8254 has six modes of operation. Each counter of 8254 can be
independently programmed to work in one of the possible six operating
modes. The six modes are :
Mode - 0 → Interrupt on terminal count.
Mode - 1 → Hardware retriggerable one shot.
Mode - 2 → Rate generator or Timed interrupt generator.
Mode - 3 → Square wave mode.
Mode - 4 → Software triggered strobe.
Mode - 5 → Hardware triggered strobe.

The initialization procedure for each mode is almost same, but the
output of each mode will be different. To initialize a counter, the
following steps are necessary:
1. Write a control word into the control register.
2. Write a count value in the count register

The writing of count value depends on the control word. There may be
three possible choices :
1. If the control word is framed for writing LSB only then write LSB
alone.
2. If the control word is framed for writing MSB only then write
MSB alone.
3. If the control word is framed for writing LSB first and MSB next,
then write LSB first and write MSB next.
 In all the modes, the GATE signal act as a control signal to start,
stop or maintain the counting process. In modes 0, 2, 3 and 4 once
the count value is loaded in the counter, the timer starts
decrementing the count value if the GATE is high. Whenever the
GATE signal goes low, the counter stops counting and will resume
counting only when the GATE is made high again

 In modes 1 and 5, the GATE act as a triggering pulse. In these


modes, the count value is loaded in the counter and it starts the
decrementing process only when the GATE signal makes a low-to-
high transition (i.e., the count process is initiated only on the rising
edge of the GATE signal). In modes 1 and 5, the GATE signal
need not remain high (after initiation) to maintain the counting
process.

ADC INTERFACE

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