Architecture of 8086 or Functional Block diagram of 8086

· 8086 has two blocks Bus Interface Unit (BIU) and Execution Unit (EU).

· The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.

· EU executes instructions from the instruction system byte queue.

· Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.

· BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
· EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.

Figure: 8086 Architecture

· It provides a full 16 bit bidirectional data bus and 20 bit address bus.

· The bus interface unit is responsible for performing all external bus operations.

· Specifically it has the following functions:

· Instruction fetch Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.

· The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.

· This queue permits prefetch of up to six bytes of instruction code. When ever the queue of
the BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.

· These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.

· After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.

· The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory.

· These intervals of no bus activity, which may occur between bus cycles are known as Idle
state.

· If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.

· The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed by adding an appended 16
bit segment address and a 16 bit offset address.

· For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of the
instruction pointer IP register.
· The BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write.
Execution Unit

· The Execution unit is responsible for decoding and executing all instructions.

· The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the read or
write bus cycles to memory or I/O and perform the operation specified by the instruction on
the operands.

· During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.

· If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.

· When the EU executes a branch or jump instruction, it transfers control to a location

· Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

General Bus Operation

· The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
· The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.

· The bus can be demultiplexed using a few latches and transceivers, when ever required.

· Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor during T1. It is
present on the bus only for one cycle.

· The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.
· Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
Maximum mode

· In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

· In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.

· In the maximum mode, there may be more than one microprocessor in the system
configuration.

Minimum mode

· In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

· In this mode, all the control signals are given out by the microprocessor chip itself.

· There is a single microprocessor in the minimum mode system.