Everything You Always Wanted to Know About Colpitts Oscillators

■ Ulrich L. Rohde and Anisha M. Apte

o
scillators are integral to the
design of modern communica-
tions systems. Generally, these
oscillators act as part of a synthesizer
and are voltage controlled, meaning
that the frequency is determined by
tuning diodes, frequently called varac-
tors. The applied dc voltage varies the
frequency. For high-performance cir- A-Z image ©istockphoto.com/Simon Bradfield, wave image licensed by ingram publishing

cuits, the Colpitts oscillator is most fre-

quently selected [1]–[30]. change occurs by changing C3. [If the heavy loading of the tuned circuit by
The Colpitts oscillator comes in three frequency of the circuit in Figure 1(a) the transistor.
flavors. Figure 1(a) shows the conven- needs to be changed, a better choice is The circuit shown in Figure 1(b) is
tional circuit configuration based on to vary the inductor L.] frequently referred to as the Clapp–
a design developed by Edwin Henry Colpitts’s colleague Ralph Hartley [2] Gouriet circuit [3], also considered a
Colpitts, who is known for his invention invented an inductive coupling oscilla- Colpitts oscillator. At frequencies below
of the oscillator that carries his name [1]. tor with the advantage of having capac- 1 GHz, both gallium arsenide (GaAs)
It employs a capacitive-voltage divider itors C1 and C2 replaced by a tapped FETs and complementary-metal-oxide-
and an inductor. This simple circuit is high-Q inductor or with a tapped heli- semiconductor FETs are not a good
not used in reality, but rather its deri- cal resonator. The frequency tuning is choice because of their high flicker
vation shown in Figure 1(b). The advan- achieved purely capacitively. To mini- noise contribution.
tage of this circuit is that the values for mize loading, the transistor of choice For the circuit of Figure 1(b), it is
C1 and C2 are fixed and the frequency here is a field-effect transistor (FET), theoretically possible to have L and C3
which has very high input impedance in resonance; in this case, the oscillator
and provides minimum loading to the will cease to work. It is important to
Ulrich L. Rohde (ulr@synergymwave.com) circuit. The disadvantage is that this note that the same circuit is also used
is with Cottbus University of Technology, circuit, using junction FETs, is limited for crystal oscillators; here, the induc-
Germany; the Technical University to about 400 MHz; the transition fre- tor L is replaced by the crystal. The
Munich, Germany; and the University quency f T is about 500 MHz. FETs can crystal is a series combination of Ls, R s,
of Oradea, Romania.
also be used in the Colpitts oscillator and Cs with Q = ~L/R. In practice, the
Anisha M. Apte (anisha_apte@ieee.org) is with
Cottbus University, Germany. shown in Figure 1(a) because of the product of crystal Q and frequency is a
relatively lower loading compared to constant. For 5 MHz, a typical Q of 2.5
that of the bipolar transistor. The draw- # 106 is possible, resulting in a prod-
Digital Object Identifier 10.1109/MMM.2016.2561498
Date of publication: 11 July 2016 back of the Figure 1(a) design is the uct of 12.5 # 1012. If this is scaled to a

August 2016 59
 c c c

b b b

C1 C1 C1
e L e e

L C3
L RL RL RL
Re
C2 C2 C2
C3

(a) (b) (c)

Figure 1. (a) A conventional Colpitts configuration, (b) a modified Colpitts (Clapp–Gouriet) configuration, and (c) a modified Colpitts
configuration for oscillators used with ceramic resonators.

Figure 3(a) and (b) ­illustrates the oscillator oscillator into real and imaginary parts,
subcircuit for the purpose of calculating including parasitics, we obtain
the negative resistance.
Based on Figure 3(b), the circuit RN  (3)
R NEQ =
equation is given from Kirchoff’s volt- (1 + ~ 2 Y 221 L 2p)

age law (KVL) as  1 = 1
C EQ *> (C 1 + C P) C 2 H
Vin = I in ^X C 1 + X C 2 h - I b ^X C 1 - bX C 2 h (C 1 + C 2 + C P)
(1a)
- = ~ Y221 L2 P 2 G
2

0 = - I in ^X C 1 h + I b ^X C 1 + h ie h . (1b) (1 + ~ Y 21 L P)
Figure 2. A photograph of a 1-GHz
#> H4
ceramic resonator oscillator [12], [28]. Y21 (4)
Considering 1/Y11 = h ie, ~ (C 1 + C P) C 2

Z in = Vin RN = - Y21 , (5)

crystal oscillator operating at 100 MHz, I in 2
~ C1 C2
^ 1 + b h X C 1 X C 2 + h ie ^ X C 1 + X C 2 h
the Q would be 125,000. Manufacturers  =
X C 1 + h ie
typically guarantee values greater (1c) where R N is the negative resistance
than 100,000. without lead inductance and pack-
(1 + b) (C 1 + C 2) 1
A third oscillator variation is shown c- + m age capacitance; R NEQ is the negative
2
~ C1 C2 j~ C 1 C 2 Y11
in Figure 1(c). Here, we have a parallel- Z in = . resistance with base–lead inductance
1 + 1
tuned circuit coupled loosely to the c m and package capacitance; and C EQ
Y11 j~ C 1
transistor. This circuit is used when (1d) is the equivalent capacitance with
building oscillators using ceramic reso- base–lead inductance and package
nators. Figure 2 shows such a design. The input impedance (Zin) of this capacitance.
This “Application Notes” column Colpitts oscillator circuit, including the The method shown here is called a
will summarize the various methods parasitics, is given as [4], [5] one-port oscillator design [6]; Figure 4
of oscillator analysis; present a step- shows the general schematic diagram
by-step design procedure showing the Z in = of a one-port negative-resistance model.
pacakage
simulated, measured, and calculated The negative real part of Zin is used
results for phase noise and other impor- -; 2
Y21 1
2 E to compensate for the losses of the
~ (C 1 + C p) C 2 (1 + ~ 2 Y 21 L 2p)
tant parameters; and conclude with ­parallel-tuned circuit.
- j;
(C 1 + C P + C 2) 
a discussion of the effect that tuning ~ (C 1 + C P) C 2
diodes have. Linear S-Parameters Approach
E . (2)
~Y21 L P Y21
-
(1 + ~ 2 Y 221 L 2p) ~ (C 1 + C P) C 2 At this point, readers may wish to
Linear Approach see how an oscillator can be analyzed
Until recently, oscillators were for many The resonator losses are expressed by using S-parameters. It should be noted
years analyzed using a linear approach. Rs1. Now, splitting the Zin of the Colpitts that this method is based on linear

60 August 2016
 I in I in Ib

hie

C1 C1 β Ib RL
RL
V in Z in V in

C2
C2

(a) (b)
Cc1

Cc Lp

C1 Cp
L C
YL
Lp
R sl
C2
Z IN

(c)

Figure 3. (a) An oscillator subcircuit for impedance analysis, (b) an equivalent suboscillator circuit for calculating the negative
resistance, and (c) a Colpitts oscillator with base–lead inductances and package capacitance.

approximations and works for practi- 1 - S 11 C G is the useful power to the load. An
CL = (11)
cally all microwave oscillator designs S 22 - DC G empirical expression for the common-
[6], [28]. The equivalent criteria for the source amplifier output power, found
S S C S - DC G
negative resistance can be calculated Sl22 = S 22 + 12 21 G = 22  by Johnson [29], is
1 - S 11 C G 1 - S 11 C G
in the form of S-parameters. (Detailed (12)
definitions of S-parameters can be
Pout = Psat c 1 - exp - GPin m, (15)
found in [31].) This negative resistance 1 = 1 - S 11 C G . (13) Psat
will cause oscillations if the following Sl22 S 22 - DC G
conditions are satisfied. Assume that where Psat is the saturated output power
the oscillation condition is satisfied at Comparing (9) and (12), we find that of the amplifier and G is the tuned
port 1 and is given by small-signal common-source transdu­
1 = C , (14)
Sl22 G cer gain of the amplifier, which is identi-
1 = C . (6) cal to S 21 2 . Because the objective is to
G
Sl11
where S11 and S22 are the input and out- maximize (Pout - Pin), where Pout and
Thus, put reflection coefficients, respectively. Pin are the output and input power of
The previous discussion shows that the amplifier,
the oscillation condition is also satis-
Sl11 = S 11 + S 12 S 21 C L fied at port 2, which proves the simul- d (Pout - Pin) = 0 (16)
1 - S 22 C L
 taneous oscillation condition at both
= 11 DC L
S - (7)
ports. Thus, if either port is oscillat-
1 - S 22 C L 2Pout
ing, the other port must be oscillating = 1 (17)
Pin
1 = 1 - S 22 C L = C . (8)
Sl11 S 11 - DC L G as well. A load may appear at either or
2Pout
both ports, but normally the load is in = G exp - GPin = 1 (18)
C L, the output termination. Pin Psat
By expanding (7), we get
It is helpful to use the common-
source-based amplifier to compute exp GPin = G (19)
Psat
C G S 11 - DC L C G = 1 - S 22 C L (9) the oscillator output power. For osc­
illators, the objective is to maximize Pin = ln G . (20)
C L (S 22 - DC G) = 1 - S 11 C G (10) (Pout - Pin) of the amplifier, which Psat G

August 2016 61
 little under large signal conditions, e x cos (wt) = / a n (x) cos (nwt)
as does S 22 . Reliable large-signal S- n

Frequency- \ 
Active parameters for bipolar transistors and = I 0 (x) + 2 / I n (x) cos (nwt) .
Determining 
Circuit FETs are difficult to obtain. 1
(34)
Circuit

Time-Domain-Based I n (x) is the modified Bessel function.

Analysis for Transistor As
ZIN(A, f ) Z r (f ) Nonlinarities
(x/2) n
Following is a correct calculation for     x " 0 & I n (x) "    (35)
n!
Figure 4. A schematic diagram of a one- the frequency-dependent parame­ t­
port negative-resistance model. ers, based on “simulation” for larger and I 0 (x) are monotonic functions hav-
dri­­­­ve level. ing positive values for x $ 0 and n $ 0,
At the maximum value of (Pout - Pin), The voltage v (t) across the base– I 0 (0) is unity, whereas all higher-order
the amplifier output is emitter junction consists of a dc com- Bessel functions start at zero (see Table 1,
ponent and a driven signal voltage line 1).
V1 cos (wt) . It can be expressed as The short current pulses are gener-
Pout = Psat ` 1 - 1 j, (21)
G ated from the growing large-­­­signal
v (t) = Vdc + V1 cos (wt) . (26) drive level across the base–emitter
and the maximum oscillator output junction, which leads to strong har-
power is As the driven voltage V1 cos (wt) i n­­ monic generation [5], [27]. The advan-
creases and develops enough ampli- tage of this pulse performance is the
Posc = (Pout - Pin) (22) tude across the base–emitter junction, reduction of phase noise, due to the
the resulting current is a periodic smaller duty cycle of the transistor [4].
= Psat c 1 - 1 - ln G m . (23) series of pulses, the amplitude of which The emitter current represented earlier
G G
depends on the nonlinear characteris- can be expressed in terms of harm­
Thus, the maximum oscillator output tics of the device, given as onics as
power can be predicted from the com-
qv (t)
I n (x)
I (x) =1 + 2 / cos (nwt)G
qVdc \
mon-source-amplifier saturated output i e (t) = I s e kT (27) i e (t) = I s e kT 0
power and the small-signal common- 1
I 0 (x)
qVdc qV1 cos (wt) 
source transducer gain G. i e (t) = I s e kT e kT (28) (36)
For high oscillator output power, qVdc
qVdc I dc = I s e kT 0 I (x) (37)
high (loop) gain is important. Ano­ i e (t ) = I s e kT e x cos (wt), (29)
ther definition of gain useful for
Vdc = kT ln ; dc E & kT ln ; dc E
I I
large-signal amplifier or oscillator assuming q I s I 0 (x) q Is

ln ; E.
design is the maximum efficient gain, kT 1
+ (38)
defined by I c . I e (b > 10) q I 0 (x)

Pout - Pin V1 = qV1 . (30)

G ME = . (24) x= I s is the collector saturation current
Pin (kT/q) kT
For maximum oscillator power, the Vdc = VdcQ - kT ln I 0 (x) (39)
q
maximum efficient gain from (20) and i e (t) is the emitter current, and x is the
(21) is drive level normalized to kT/q. I n (x)
i e (t) = I dc =1 + 2 / cos (nwt)G . (40)
\

From the Fourier series expansion, I 0 (x)

G ME max = G - 1 . (25) 1
ln G e x cos (wt) is expressed as
VdcQ and I dc are the operating
The RF gain GMEmax is a considerably dc bias voltage and the dc value of
e x cos (wt)
= / a n (x) cos (nwt) . (31)
smaller value compared to G, the small- n the emitter current. Furthermore, the
signal gain [7]–[12]. Fourier transform of i e (t), a current
Designing oscillators based on a n (x) is a Fourier coefficient and given pulse or series of pulses in the time
S-parameters in a linear mode has as domain, yields a number of frequency
been cited by many authors using 2r harmonics common in oscillator cir­­cuit
the first approximation of large sig- a 0 (x) n = 0 = 1 # e x cos (wt) d (wt) = I 0 (x) designs using nonlinear devices.
2r
nal, as described in [8]. The prob- (32) 0 The peak amplitude of the harm­
lem with this published approach onic content of the output current is
defined as 6^I N (x) /I 1 (x) h@, and the dc
2r
is that it uses a GaAs FET, where a n (x) n20 = 1 # e x cos (wt) cos (nwt) d (wt)
only the transconductance g m has a 2r offset voltages are calculated ana-
0
major ­i nfluence. S11 changes very  = I n (x) (33) lytically in terms of the drive level,

62 August 2016
 Table 1. The data generated at various drive levels for T = 300 K.

Fundamental
Drive Level Drive Voltage Offset Coefficient DC Offset Current Second Harmonic
c; E * x m mV
[x] kT ln [I 0 (x)] kT [ln I (x)] mV 2 [I 1 (x) /I 0 (x)] [I 2 (x) /I 1 (x)]
0
q q

0.00 0.000 0.000 0.000 0.000 0.000

0.50 13.00 0.062 1.612 0.485 0.124
1.00 26.00 0.236 6.136 0.893 0.240
2.00 52.00 0.823 21.398 1.396 0.433
3.00 78.00 1.585 41.210 1.620 0.568
4.00 104.00 2.425 63.050 1.737 0.658
5.00 130.00 3.305 85.800 1.787 0.719
6.00 156.00 4.208 206.180 1.825 0.762
7.00 182.00 5.127 330.980 1.851 0.794
8.00 208.00 6.058 459.600 1.870 0.819
9.00 234.00 6.997 181.922 1.885 0.835
10.00 260.00 7.943 206.518 1.897 0.854
15.00 390.00 12.736 331.136 1.932 0.902
20.00 520.00 17.590 457.340 1.949 0.926

as shown in Table 1. This gives good I c = 70 mA, and Ptot = 300 mW; the noise transistor BFG520 is used. At the pro-
insight into the nonlinearities involved figure Fmin at 350 MHz is lower than posed starting dc current of 6 mA (this
in oscilla­tor design. 1 dB, and at 5 mA the associated gain is being close to the minimum noise fig-
It may be of interest at this point to more than 17 dB. ure current and used as a first trial to
see the start-up condition of an oscilla- meet the output power), fT is 6 GHz.
tor; the transient response is shown in A Design Example for a When se­­ l­­
ecting a transistor with a
Figure 5. 350-MHz Fixed-Frequency higher fT, there is always a possibil-
Colpitts Oscillator ity of unwanted microwave oscilla-
Selecting the Right Transistor Following is an exact ­m athematical tion and higher flicker noise.
The basic design of a Colpitts oscilla- solution for designing a 350-MHz Col­­ Comparing microwave transist­
tor is the same, whether one uses an pitts oscillator. o­rs with audio transistors, it becomes
FET or a bipolar junction transistor The circuit consists of the Colpitts apparent that at much lower fT fre-
(BJT). Bipolar-transistor-based oscilla- configuration following Figure 1(c). To quencies, there is much less flicker
tors can now easily be designed up to have enough loop gain, a microwave noise contribution. This transistor can
20 GHz. The basic advantage of the bipo-
lar transistor (also known as BIP) is the
lower flicker noise corner frequency. 800.00
Currently, transistor chips with Fmax up Vemit
emitter
m ter

to 300 GHz are available in the foundry 600.00

environment and commercially up to
about 150 GHz.
V (Port3) (mV)

400.00
For the purpose of this design sy­­ n­­
thesis, we use a Philips BFG520, a 200.00
highly linear transistor. It is vali-
dated with a three-tone test (the typi-
0.00
cal two-tone test is easier to perform),
as explained on the product data sheet;
–200.00
the mixing products are better than −60 0.00 10.00 20.00 30.00 40.00 50.00
dB suppressed relative to the carrier. Time (ns)
Based on past experience, the BFG520
shows good linearity and, therefore, Figure 5. An example of the transient simulation of a ceramic-resonator-based high-Q
also has low distortion and low noise. oscillator with the dc offset shown in the fourth column of Table 1. (The voltage displayed
The key parameters are VCEO = 15 V, is taken from the emitter.)

August 2016 63
be safely operated at 30 mA, but the oscillation at 350 MHz. Experimenting Vout = Pout (mW) # 2R L
rule of thumb when using 10–15% of with the simulation, it turns out that Lb = 14 # 10 -3 # 2 # 200
Ic max is that the flicker contribution is set to 0.5 uH gives a much better phase = 2.37 V (41)
much lower. For low noise operation, noise, about 10 dB better at 100 Hz offset; 
V
the data sheet indicates a 1.1-dB spot- however, this could not be verified yet in I 1 = out = 2.37 , 11.85 mA (42)
200 200
noise figure at 900 MHz, 5 mA. a real circuit.
The 350-MHz oscillator, using The output power is taken from I1
I e = I dc =
the bipolar transistor BFG520, is de­­­ the collector with the f­ollowing 1.932

signed based on analytical equations de­s ig n procedure. The goal is to = 11.85 = 6.13 mA. (43)
and later verified with simulation obtain an output power of over 1.932
results. Based on the output power 10 dBm, using a simple design for Note that no saturation voltage is
requirement and harmonics at a given good understanding. assumed. This results in slight varia-
load, the drive level is fixed. The nor- tions among the calculated, simulated,
malized drive level ( x = 15) is chosen Step 1: Initial Specification and measured values of Pout.
to allow adequate drive level to sustain The normalized drive level is set
oscillation and still not produce exces- at 15, for which the fundamental peak Step 2: Biasing
sive harmonic content. current I 1 (fundamental) = 1.932I dc The transistor uses a 12-V power supply
Figure 6 shows the values of the opti- (this is taken from Table 1). I 1 is the and an 825-Ω emitter resistor at ~6 mA,
mized circuit. While simulating for a fundamental current specified by the resulting in ~5-V drop, so the transistor
series resonant configuration, the value output power needed for the desig- can afford a large voltage swing between
of C p = 8.2 fF was used as a place holder, nated load. base and ground. This reduces flicker
based on impedance considerations. The primary impedance of the trans- noise (resistive feedback) and distortion.
C p was set to 8.2 pF for parallel resonant former is 200 X, and we calculate the RF The base voltage divider, for reasons
configuration, and the values of L = voltage for R L = 200 X and for an out- pertaining to temperature stability, uses
21 nH and C c = 3.3 pF were set to achieve put power of Pout . 11 dBm . 14 mW: a higher than normal dc current and is

Ind
+
–

10 µH cap
blos

3.9 nF
2.29 koh

V : 12
res

200 to 50 Ω 220 pF

R2 res R1 trf
n1 n2 cap
2.27 koh Vb
220 pF
n3 n4
1.7 µH

Q = 120 V
Ind

c cap C0
Lb
b/p P1
3.3 pF osc
ptr bfg520
b
cap Cc
cap

22 pF

e
L
cap

C1
8.2 pF
21 nh

Ind

res
Cp
Q = 220 1 oh
cap

825 oh
8.2 pF

res

C2
Re

Figure 6. The design of a 350-MHz Colpitts oscillator, optimized for phase noise.

64 August 2016
isolated from the base using an RF choke Figure 9 show Ic as a function of drive The large-signal transconduc-
(frequently, in designs, this circuit trick is level X. tances Y21 and G1 are transformed to
not used): Based on KVL, the following set of the current source through the volt-
equations can be used to determine the age divider Veb /Vcb . The voltage Veb
Vb = I e ;R e + R e E + Vbe = 5.96 V. (44)
feedback factor n [the oscillator circuit must be added to Vce to calculate the
b+1 with passive component parameters is transformation ratio, which is also the
shown in Figure 7(a)]: inverse of the feedback factor and can
b is assumed to be around 100, and be written as
Y 21L = 1.1 mS
V be is approximately 0.8 V. Bias resistor
Veb
R1 and R 2 is given as (dc transconductance, with no high- = C 2 = 1 (51d)
Vcb C1 + C2 n
frequency effects included), where
a = 0.99. Then, Vce
Vb = R 2 Vcc = 5.96 V & R 1 . 1  = C 1 = n - 1 . (51e)
R1 + R2 R2 Vcb C1 + C2 n
(45) Y 1 = G 1 + jB 1 & j~C 1 for G 1 = 0 (51a)
R 1 = 2270 X (46) The conductance G2 is already in
Y 2 = G 2 + jB 2 & G 2 + j = 2 G.
(~ 2 LC - 1) ~C c
parallel with the current source, so it
R 2 = 2290 X (47) ~ L (C c + C) - 1
 remains unchanged. The factor n rep-
Vcc = 12 V. (48) (51b) resents the ratio of the collector–base
voltage to the emitter–base voltage at
Here, G 2 equals the loss parameter/
Resistor bias current is ~2.6 mA, (Vcc / the oscillator resonant frequency
load conductance of the resona-
(R 1 + R 2)) . Base current is 43 nA, so the
tor connected parallel to the reso-
safety factor is 2.6/0.043 , 60. G 1 " G21 (51f)
nator components C 1, C 2 , and L, n
respectively.
Step 3: Determining the Large- Y21 " Y212 & G m2 (51g)
Signal Transconductance n n
Y 3 = G 3 + jB 3 & G 3 + j~C 2 . (51c)
Based on Table 1 and x = 15, the dc
G 3 " 8 n - 1 B G 3 . (51h)
2

transconductance equals Here, G 3 equals the conductance of the n

bias resistor placed across C2, 1/R L, as
shown in Figure 7(a). G2 remains constant.
Y21 = I 1
V1 fundamental - freq
1.932I dc 11.85 mA
 = 1000 mV = 1000 mV , 12 mS.
(49)
Y2
This dc transconductance means that
the frequency depende­ nce has not CC Y3
been considered.
An analysis of the transistor shows L C = Cp
that the small-signal transconductance C2
at 6 mA (dc) is about 6 # 39 . 240 mS. RL
At 350 MHz, this reduces to 200 mS, down
from 240 mS (which is valid only if the Y1 C1
transistor does not have any emitter
feedback). In the case of the Colpitts
oscillator, we have an emitter resis- (a)
tor that reduces the transconductance; Y3
therefore, we have to multiply Y21 by Collector Emitter
[26, p. 177]

αIe Y2 Y1 Y21 Vbe

1
c m . (50)
(1/gm) + R e
Base

The resulting large signal loop trans­­ (b)

conductance Y21L is (1/(1/12 # 10 - 3)
+ 825) , 1.1 mS, which is an acceptable Figure 7. (a) An oscillator circuit with the passive components Y1, Y2, and Y3. (b) The
approximation as the exact value of x equivalent oscillator circuit for analyzing the transformed conductance seen by the
is about 20. The simulation results in current source.

August 2016 65
 Y21 R P = n (51v)
–50.00 n 1-n
x = Drive–Level
R P = 1 , Y21 R P " loop gain (51w)
–75.00 G2 n

PN1<H1> (dBc/Hz) –100.00 loop gain Y21 R P " 1. (51x)

n
x=3
–125.00 x = 10
x = 15 From (51r) and (51u),
–150.00 [C 1 + C 2] 2
x = 20 Y21 & G m (x) = 1 . (51y)
RP C1 C2
–175.00
The quadratic equation for n (from
1.00E02

1.00E03

1.00E04

1.00E05

1.00E06

1.00E07
(51n) is reduced to

n 2 (G 3) - n (2G 3 + Y21 a) + (G 3 + Y21) = 0 

FDev (Hz)

G 3 = 1 = 1 = 1.21 mS (52a)
Figure 8. An example of the single sideband phase noise as a function of the normalized Re 825
drive level x for a high-Q 1-GHz oscillator.
n 2 (1.21) - n (2 # 1.21 + 1.1 # 0.99) 
(52b)
+ (1.21 + 1.1) = 0
The transformed conductance is pro- To ensure higher loop gain, n 1 is
1.21n 2 - 3.514n + 2.313 = 0 (52c)
portional to the square of the voltage selected from n max [n 1, n 2] . Once the
ratios given in (51d) and (51e), producing value of n is fixed, then the ratio of the 3.514 ! (3.514) 2 - 4 # 1.21 # 2.313
a total conductance as seen by the current capacitance is calculated as n=
2 # 1.21
source at resonance as (53)
C 2 = 1 (51r) n & n 1 = 1.888 and n 2 = 1.01. (54)
G tot al = G 2 + G m +2 G 1 + 8 n - 1 B G 3 . (51i)
2
C1 + C2 n
n n
The higher value of the transformation
C 2 = C 1 & C 1 = n - 1. (51s)
For sustained oscillation, the closed n-1 C2 factor, n, is selected as n = 1.888.
loop gain at resonance is given as The ratio for the values of C1 and C2
If G 3 and G 1 are zero, then the qua- is calculated as
V Y a dratic equation (51n) reduces to
c be 21 m
> nG total H = 1 & nG = Y a (51j) C 2 = 1 & C = C 1 (55)
C1 + C2 n 2
n-1
V be
total 21 n 2 G 2 - nY21 a + Y21 = 0 (51t)

Y21 = 1 & Y21 2 1. (51k) n 2 G & Y = ; n 2 E 1 (51u) C 2 = C 1 = C 1 & C 1 , 0.9 . 1.

Y21 , n-1 0.888 C2
nG total a nG total 1-n 2 21
1 - n RP (56)

Here, a is assumed to be 0.0.99, and

variation in the value of a does
not greatly influence the previouse
Y21 a = n ;G 2 + Y21 +2 G 1 + ` n - 1 j G 3E & ; E Y21
2 - (1 - na)
expression. Rearranging the device n n n2
conductance and circuit conductance, 
= ;G 2 + G21 + ` n - 1 j G 3E
2
(51m)
the general oscillator equation, after n n
multiplying (51i) with n on both sides,
is written as n 2 (G 2 + G 3) - n (2G 3 + Y21 a) + (G 1 + G 3 + Y21) = 0 (51n)

nG total = n ;G 2 + Y21 +2 G 1 + ` n - 1 j G 3E
2
(2G 3 + Y21 a) ! (2G 3 + Y21 a) 2 - 4 (G 2 + G 3) (G 1 + G 3 + Y21)
n n n= (51o)
 2 (G 2 + G 3)
(51l)
(2G 3 + Y21 a) (2G 3 + Y21 a) 2 - 4 (G 2 + G 3) (G 1 + G 3 + Y21)
and (51m)–(51q) in the box to the n1 = + (51p)
2 (G 2 + G 3) 2 (G 2 + G 3)
right. From the quadratic equation
(51l)–(51q), the value of the factor n can
be calculated, and, thereby, an estima- (2G 3 + Y21 a) (2G 3 + Y21 a) 2 - 4 (G 2 + G 3) (G 1 + G 3 + Y21)
n2 = - (51q)
tion of the capacitance can be made 2 (G 2 + G 3) 2 (G 2 + G 3)
a priori.

66 August 2016
The ratio of the capacitor C1 to C2 is assessed for individual circuits, but the thus producing less loading and bet-
1. For larger transconductance, Y21, (C1/ general trend follows the plot shown. ter phase noise, but at the cost of lower
C2) > 1. In Figure 9, x = 1 is the linear case power output.
(class-A operation), and the values If the transistor is overdriven at the
A Discussion About above x = 15 produce narrow pulses. base, the collector current folds back
Drive Level and Noise Class-A operation gives higher out- (dip), and the actual current gain falls
The plot in Figure 8 [5] shows the impact put power but is not optimized for phase to values of 1.4, in our case (Figure 9).
of the normalized drive level x on the noise. However, at higher drive levels, For the uncompressed current gain
phase noise. The exact values have to be the transistor is on for a shorter duration, (Y21/Y11) . (C2/C1) . 270 pF/10 pF, the

08/21/15 Ansoft Corporation-Harmonica ® v8.71 16:35:30 Y21_BFG52Y1

lc(_lib1)
freq = 3.5E + 008 Hz

80.00
x = 15
60.00 x = 2 to 14

x=1
40.00
lc(_lib1) (mA)

20.00

0.00

–20.00

–40.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Time (ns)

Figure 9. Ic as a function of drive level X.

08/25/15 Ansoft Corporation-Harmonica ® v8.71 16:02:08 colpitts scheY1

colpitts_schematics_350 MHz.ckt PN1<H1>
0.00
colpitts scheY1
PN1<H1>

–50.00
PN1<H1> (dBc/Hz)

1 colpitts scheY1
PN1<H1>
2
–100.00 3
C1/C
C2 = 33 pf/10 pF for Optmized
Phase Noise (Series Tuned Circuit)
4
–150.00

–200.00
1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06
FDev (Hz)
X1 = 1.00E01 Hz X2 = 8.11E01 Hz X3 = 1.18E03 Hz X4 = 8.70E04 Hz
Y1 = –68.11 dBc/Hz Y2 = –86.32 dBc/Hz Y3 = –109.57 dBc/Hz Y4 = –146.94 dBc/Hz

Figure 10. Optimization of the phase noise for the series-tuned circuit.

August 2016 67
circuit will actually oscillate but does not as found in ceramic-resonator-based 1 1 + 1 
~= ; E (59)
have acceptable phase noise [low value oscillators.  L C1 C2
of x, n = 28, where n = (C 1 /C 2) + 1)] . The quality factor of the induc-
; E
By changing the capacitors C 1 /C 2 tor is assumed 60 at 350 MHz, a 2
~ =
1 1 + 1 = C 1 + C 2 . (60)
L C1 C2 LC 1 C 2
to 33 pF/10 pF, n = 4.3, the phase low Q case. The value of inductor is
noise performance is optimized, as obtained as
shown in Figure 10. This circuit is a The value of the capacitor is deter-
series-tuned oscillator, and now we Q T = R P & L = 3649 , (57) mined as
~0L 60 # ~ 0
move on to a high-Q (from Q = 220 to
Q = 450) circuit, where the resonator where R p is calculated using C2 = 2.55 . 14 pF (61)
2
~ # 17E - 9
is loosely coupled to the transistor.
G m (x) = 1 C 1 ;1 + C 2 E
2
The tuned circuit consists of a 22-nH C 1 . C 2 . 14 pF. (62)
RP C2 C1
inductor and 8.2-pF capacitor. The
following shows the design calcula- L= 3649 . 27 nH Taking into consideration the actual
60 # 2r # 350 # E6
tion for the parallel-tuned circuit, (58) parasitics and RF parameters of the

Phase Noise Equation

Ic := 6.2⋅10–3 Ib := 43.2⋅10–6 L := 22⋅10–9 C1 := 12⋅10–12 C2 := 8.2⋅10–12 CC := 3.3⋅10–12

K := 1.3806⋅10–23 T := 300 KT := 4.143⋅10–21 R := 0.3 Kf := 1⋅10–7 AF := 2

Q := 60 Vcc := 12 f := 350⋅106 w0 := 2 π⋅f β := 140

26⋅10–3 1
re := gm1 := gm1 := 0.238 q := 1.602⋅10–19 i := 0...7 foi := 10i
Ic re

w o i Is the Frequency Offset from the Carrier wo i := 2⋅π⋅foi

Kf⋅IbAF
4⋅q⋅Ic⋅gm12 + ⋅gm12
woi w02 1 (C 1 + C 2)2
Lwi := 10⋅log 4⋅KT⋅R + ⋅ ⋅ +
2 4⋅(woi)2⋅Vcc2 Q2 2 2
C 1⋅C 2⋅(w 0)4⋅L 2
2 C2
(w0)2⋅C 1 ⋅ (w0)2⋅β 2⋅C22 + gml2⋅ 2
C1

foi Lwi
0
1 –5.227
10 –35.222 –20
100 –65.165 –40
1⋅103 –94.633
–60
–121.303
1⋅104
–143.272 –80
1⋅105 –163.529 Lwi –100
1⋅106 –183.555
–120
1⋅107
–140

–160

–180

–200
1 10 100 1 + 103 1 + 104 1 + 105 1 + 106 1 + 107
foi

Figure 11. The Mathcad calculation for phase noise.

68 August 2016
transistor, the optimized values are L (~) = 10Log •• Q L = loaded Q of the tuned circuit
C 1 = 12 pF and C 2 = 8.2 pF. ZR R VV •• Q O = unloaded Q of the tuned
]S S K f I bAF 2 WW
]S S 4qI c g 2m + gm WW
# [S4kTR +S ~ circuit
2 WW
 ]]SS SS ~ 0 C 1 (~ 0 c b ) C 2 + g m 2 m WWWW
2 2 2 + 2 2 2 C2 • • kT = 4.1 # 10 −21 at 30 0 K (room
Step 4: Calculating the Coupling \T C1 tem­­­perature)
T XX
; 2 2 E= 2 + 2 2 4 2 G3,
Capacitor Cc
2
~0 1 [C 1 + C 2] 2 •• R = equivalent loss resistance of
The expression for the coupling capaci- 4~ V cc Q C1 C2 ~0 L (65) the tuned resonator circuit
tor is •• I c = RF collector current
where
•• I b = RF base current
•• b + = ; + E;
C 1 Ep
C 2C 2 +
Y 21
10 C •• Vcc = RF collector voltage
Y 11 C 2
Z _ •• C 1, C 2 = feedback capacitor.
]] (~ 2 C 1 C 2) (1 + ~ 2 Y 221 L 2P) bb  •• g m = 6Y +21@6C 1 /C 2@q , with the values Using a Mathcad calculation, we
[ [Y 21 C 2 - ~ C 1 C 2)(1+ ~ Y 21 L P) ` (63)
2 2 2 2 2
of p and q depending upon the obtain the results as shown in Figure 11
] # (C 1 + C P + C 2)] b
\ a drive level (x) [5], which compare well with the mea-
•• Y +21, Y +11 = large signal [Y] param- sured data.
C c = 3.3 pF. (64)
eter of the active device
•• K f = flicker noise coefficient Measured Results for
Step 5: Calculating the •• AF = flicker noise exponent a 350-MHz Oscillator
Phase Noise of the Colpitts •• L (~) = ratio of sideband power in a The measured phase noise of the
Oscillator 1-Hz bandwidth at ~ to total power oscillator shown in Figure 12 is not
The mathematical expression of the in dB quite comparable with the mathemat-
phase noise of a Colpitts oscillator is •• ~ = frequency offset from the c­ arrier ics be­­cause it has a two-stage buffer
[5, p. 180] •• ~ 0 = center frequency amplifier that isolates the oscillator

R&S FSUP 8 Signal Source Analyzer Locked

Settings Residual Noise [T1 W/o spurs] Phase Detector +20 dB
Signal Frequency: 350.000030 MHz Int PHN (1.0 .. 10.0 M) –2.7 dBc
Signal Level: 10.67 dBm Residual PM 59.306°
Cross Corr Mode Harmonic 1 Residual FM 1.106 khz
Internal Ref Tuned Internal Phase Det RMS Jitter 470.6825 ps

Phase Noise (dBc/Hz) RF Atten 5 dB Top 10 dBc/Hz

Spot Noise [T1 w/o Spurs]

LoopBW 100.000 Hz –65.31 dBc/Hz
1.000 kHz –97.40 dBc/Hz
10.000 kHz –129.32 dBc/Hz
100.000 kHz –144.37 dBc/Hz
–30 502.929 kHz –146.28 dBc/Hz
1 CLRWR
SMTH 3%
2 CLRWR –50

–70

–90

–110
SPR Off
TH 0 dB
–130

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz

Frequency Offset

Figure 12. The measured phase noise result for a 350-MHz oscillator.

August 2016 69
 08/27/15 Ansoft Corporation-Harmonica ® v8.71 11:23:33 colpitts scheY1
colpitts_schematics_350 MHz.ckt PN1<H1>
0.00

–50.00
2
PN1<H1> (dBc/Hz)

3
–100.00
4
5
–150.00

–200.00
1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06
FDev (Hz)
X1 = 9.33E00 Hz X2 = 1.00E02 Hz X3 = 1.07E03 Hz X4 = 1.00E04 Hz X5 = 9.33E04 Hz
Y1 = –37.37 dBc/Hz Y2 = –68.15 dBc/Hz Y3 = –97.93 dBc/Hz Y4 = –122.10 dBc/Hz Y5 = –142.55 dBc/Hz

(a)

12/10/15 Ansoft Corporation-Harmonica ® v8.71 12:16:03 colpitts scheY1

colpitts_schematics_350 MHz.ckt PN1<H1>
–25.00
1
–50.00
2
PN1<H1> (dBc/Hz)

–75.00

3
–100.00

4
–125.00
5
–150.00

–175.00
1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06
FDev (Hz)
X1 = 1.00E01 Hz X2 = 1.02E02 Hz X3 = 1.05E03 Hz X4 = 1.07E04 Hz X5 = 9.77E04 Hz
Y1 = –43.57 dBc/Hz Y2 = –73.56 dBc/Hz Y3 = –101.50 dBc/Hz Y4 = –124.58 dBc/Hz Y5 = –144.18 dBc/Hz

(b)

Figure 13. (a) The simulated phase noise and (b) the optimized simulated phase noise for a 350-MHz parallel-tuned Colpitts
configuration.

from the output termination. This the phase noise from −122 dBc/Hz 2.44 nH/pF in the case of discrete com-
explains the limit of −146 dBc/Hz to −125 dBc/Hz at 10-kHz offset. This ponents used in our demonstration), the
at far offset. At close in, the phase is a result of trial-and-error, as we do simulated phase noise is 105 dBc/Hz at
noise is influenced by an automatic not know all the paras­ itics. Figure 10-kHz offset. (Note: this is due to the
frequency control circuit. The actual 13(a) shows the simulated phase noise fact that the characteristic impedance of a
comparison should be made between plot, and Figure 13(b) shows further ceramic resonator is much lower than the
10 Hz–10 kHz offsets. improvement after optimizing the discrete case: Z 0 = 60 X 1/ f r ln D/d,
To optimize the phase noise for circuit for phase noise. where D = the outer diameter and d =
this type of oscillator using discrete If we replace the parallel-tuned cir- the inner diameter of the ceramic reso-
components, the selection of the val- cuit with a ceramic resonator (at this nator [12], p. 754].) The prediction agrees
ues C p = 8.2 pF, L = 21 nH, C 1 = 22 pF, frequency range, f r will be 88, and the well with the measured phase noise [12,
C 2 = 8.2 pF, and C c = 3.3 pF im­proved L/C ratio will be 0.048 nH/pF versus Figs. 5–37].

70 August 2016
 Figure 14 shows the plots of the col- drive level: (x) is V1/(kT/q). From A table of normalized transconductance
lector and base currents Ic and Ib for the Figure 15, we see that the root mean as a function of the drive level, including
optimized case [C p = 8.2 pF, L = 21 nH square (RMS) value of V be is used the large values, is given in Table 2 [5].
(Q = 60 at 350 MHz), C c = 3.3 pF, to determine the approximate drive Figures 16 and 17 show the phase-
C 1 = 12 pF, and C 2 = 8.2 pF] . From the level. Because V be = V1, t he d r ive noise variation, with variation of
plot in Figure 14, we can determine that the level is Q (L = 22nH) in the L/C resonator. The
ratio of the large signal (Y21/Y11) = b = 1.4. output power, collector current, and
The next critical parameter, shown 500 mVrms base voltage ^Vbh and ^Vbeh plots are
(x) . . 20. (66)
in Figure 15, is for the ­n ormalized 26 mV also shown for the same combination.

08/25/15 Ansoft Corporation-Harmonica ® v8.71 18:08:52 colpitts scheY1

colpitts_schematics_350 MHz.ckt Plb(_lib1)
freq = 10 Hz

15.00 20.00 colpitts scheY2

Plb(_lib1)
freq = 10 Hz
10.00
15.00

5.00
lb(_lib1) (mA)
lc(_lib1) (mA)

10.00
0.00
5.00
–5.00

0.00
–10.00

–15.00 –5.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00
X1 = 2.46 ns X2 = 3.26 ns X3 = 2.68 ns Time (ns)
Y1 = 12.27 mA Y2 = –12.64 mA Y3 = 19.05 mA

Figure 14. The Y21/Y11 large signal condition.

08/26/15 Ansoft Corporation-Harmonica ® v8.71 15:45:55 colpitts scheY1

Vbe(_lib1)
colpitts_schematics_350 MHz.ckt freq = 10 Hz

1.00

0.50
Vbe(_lib1) (V)

0.00

–0.50
0.00 1.00 2.00 3.00 4.00 5.00 6.00
X1 = 2.69 ns X2 = 4.16 ns Time (ns)
Y1 = 0.96 V Y2 = –0.44 V

Figure 15. The drive level calculated using V be.

August 2016 71
 The parallel-tuned circuit shows mensionless quantity) and is a bi- corner, requires solving the following
better phase noise performance, as as-dependent curve-fitting term, equation [20], [21]:
seen in Figure 18, due to the fact that typicaly 2.
the rate of change of reactance in a •• The KF (flicker noise constant) Fbn = Fmeas [1 + 1/b + 2Vth G in /IB, (68)
parallel-tuned circuit is significantly value ranges from 10−12 to 10−6
larger than that in a simple series- and defines the flicker corner fre- where Fbn = intrinsic base flicker noise
tuned oscillator. quency [32]. corner, Fmeas = measured flicker corner,
One of the important characteris- b = collector–base current gain, Vth =
1/f Noise tics for device evaluation and selec- thermal voltage = kT/q, G in = external
The electrical properties of surfaces or tion is 1/f noise, which is a function of input conductance, and IB = dc base-
boundary layers are influenced ener- the active device characteristics and a biasing current.
getically by states, which are subject to major contributor to phase noise, espe- The equation for the intrinsic base
statistical fluctuations and, therefore, cially in applications such as voltage- flicker corner modifies the measured
lead to the flicker noise, or 1/f noise, for controlled oscillators (VCOs) [5], [20]. flicker corner to account for the device’s
the current flow. In an oscillator, 1/f noise that is pres- input conductance, base current, and
1/f− noise is observable at low fre- ent in transistors at low frequencies is dc current gain. The formula for Fbn
quencies and generally decreases with upconverted and added to the phase is valid, provided that the measured
increasing frequency f according to noise around the carrier signal. Hence, output noise characteristics are domi-
the 1/f− law until it is covered by a fre- proper characterization of 1/f noise and nated by the base flicker and base shot
quency-independent mechanism, such its effects on phase noise is an impor- noise sources.
as thermal noise or shot noise. tant topic. In addition, 1/f noise is not Changing the KF and AF factors
Example: The noise for a conducting solely an active device phenomenon. affects the phase noise, as can be seen
diode is bias dependent and is expressed Passive devices such as carbon resis- from the plots. The Y-intercept of the
in terms of exponents AF and KF: tors, quartz resonators, surface acous- 1/f spectra increases proportionally
tic wave devices, and ceramic capaci- to KF (Figure 19), which is in accor-
AF
I DC tors are among the devices that show dance with (34). The Y-intercept of the
i 2Dn = 2qI dc B + KF B
AC
f  the presence of this phenomenon when 1/f spectra decreases more rapidly
used as part of low-noise electronic sys- with an increase in AF (Figure 20).
•• The AF (flicker noise exponent) is tems. Generally, 1/f noise is present in As discussed in the following sec-
generally in the range of 1–3 (di- most physical systems and many elec- tion, the tuning diodes result a noise
tronic components [19], [22], [23]. contribution similar to this flicker
Flicker noise in BJTs is also known mechanism.
Table 2. Large-signal as 1/f noise because of the 1/f slope
transconductance as a function of characteristics of the noise spectra. This AM-to-PM Conversion
drive level based on Bessel function noise is caused mainly by traps associ- from Tuning Diodes
calculations: Gm(x)/gm = 2[I1(x)/xI0(x)] ated with contamination and crystal Figure 21 shows a parallel-tuned circuit
versus the drive level = x. defects in the emitter–base depletion that is connected to the oscillator dis-
layer. These traps capture and release cussed earlier. The frequency change is
Gm(x)/gm
Drive level = x = 2[I1(x)/xI0(x)]
carriers in a random fashion. The time obtained by applying a positive voltage
constants associated with the process to the + terminal. The parallel capacitor is
0.00 1 produce a noise signal at low frequen- replaced by the two tuning diodes. Here,
0.50 0.970 cies. The flicker noise spectral density we will show the influence of the tuning
1.00 0.893 is given by diodes in the VCOs; the resulting phase
2.00 0.698 noise generated by the tuning diodes is
S (f) = (KF) IB AF df/Fc, (67)
3.00 0.540 shown in Figure 22.
where KF = flicker noise constant, It is possible to define an equivalent
4.00 0.432
AF = flicker noise exponent, IB = dc noise Raeq that—inserted in Nyquist’s
5.00 0.357
base current, and FC = flicker noise cor- Johnson noise equation
6.00 0.304
ner frequency.
7.00 0.264 The measured flicker corner fre- Vn = 4kTo RDf , (69)
8.00 0.233 quency, Fmeas , is determined by noting
9.00 0.209 the intersection of the 1/f noise spec- where kTo = 4.2 # 10 -21 at about 300 K,
10.00 0.190 trum and the white-noise spectrum. R is the equivalent noise resistor, and
15.00 0.129 This intersection is where the mea- Df is the bandwidth—determines an
20.00 0.0975 sured flicker noise power and the white open-circuit noise voltage across the
noise power are equal. Determining tuning diode. Practical values of Raeq
25.00 0.075
Fbn, the intrinsic base flicker noise for carefully selected tuning diodes

72 August 2016
 are in the vicinity of 200 W–50 kW.   ^Dfrmsh = K o # ^1.296 # 10 -8 V h  (70) 0.00183 rad (72)
id =
If we now determine the noise fm
­voltage, Vn = 4 # 4.2 # 10 -21 # 10, 000 , in 1-Hz bandwidth. To translate this into
the resulting voltage value is 1.296 # an equivalent peak phase deviation, in 1-Hz bandwidth. For fm = 25 kHz
10−8 V Hz . (the typical spacing for adjacent-channel
Ko 2 ^
This noise voltage generated from   i d = 1.296 # 10 -8h rad   (71) measurements for FM mobile radios),
fm -8
the tuning diode is now multiplied i c = 7.32 # 10 . This can now be con-
with the VCO gain Ko, resulting in the in 1-Hz bandwidth; or, for a typical oscil- verted into the single-sideband modula-
RMS frequency deviation lator gain of 100 kHz/V, tion signal-to-noise ratio as follows:

08/14/15 Ansoft Corporation-Harmonica ® v8.71 15:45:55 colpitts scheY1

PN1<H1>
colpitts_schematics_350 MHz.ckt
1.00 colpitts scheY1
TR1 Cc = 5.6 pF, C1 = 8.2 pF, C2 = 8.2 pF, Q (L = 22 nH) = 50 PN1<H1>

TR2 Cc = 3.3 pF, C1 = 12 pF, C2 = 8.2 pF, Q (L = 22 nH) = 120

TR3 Cc = 3.3 pF, C1 = 22 pF, C2 = 8.2 pF, Q (L = 22 nH) = 220 colpitts scheY1
–50.00 TR4 Cc = 3.3 pF, C1 = 20 pF, C2 = 20 pF, Q (L = 22 nH) = 450 PN1<H1>
PN1<H1> (dBc/Hz)

colpitts scheY1
PN1<H1>
–100.00

–150.00

–200.00
1.00E00 1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06 1.00E07
FDev (Hz)

Figure 16. The optimized phase noise for different values of inductor Q.

08/17/15 Ansoft Corporation-Harmonica ® v8.71 15:52:11 colpitts scheY1

PN1<H1>
colpitts_schematics_350 MHz.ckt
0.00
colpitts scheY1
PN1<H1>

TR1 Cc = 3.7 pF, C1 = 22 pF, C2 = 10 pF, Q (L = 89 nH) = 220

colpitts scheY1
–50.00 PN1<H1>
PN1<H1> (dBc/Hz)

–100.00
Lower TR Cc = 3.3 pF, C1 = 22 pF,
C2 = 8.2 pF, Q (L = 22 nH) = 220
–150.00

–200.00
1.00E00 1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06 1.00E07
FDev (Hz)

Figure 17. The results of series and parallel-tuned circuits for the same value of inductor Q.

August 2016 73
L (fm) = 20 log 10 i c = - 149 dBc/Hz.  changes the picture again. Therefore, 1 # 10 7 2 ^
2 id = 1.833 # 10 -9h rad
(73) with kTo = 4.2 # 10 -21, the resulting fm
noise voltage will be (75)
For the typical oscillator gain of
10 MHz/V found in wireless appli- Vn = 4 # 4.2 # 10 -21 # 200 or
      0.026 rad (76)
cations, the resulting phase noise = 1.833 # 10 -9 V Hz . (74) id =
will be 20 dB worse [10 log (10 MHz fm
÷ 100 kHz)]. However, the best tun- From (72), the equivalent peak phase in 1-Hz bandwidth, with fm = 25 kHz,
-6
ing diodes, like the BB104, have an deviation for a gain of 10 MHz/V in a i c = 1.04 # 10 . Expre­ssing this as phase
Rn of 200 X instead of 10 kX, which 1-Hz bandwidth is then noise,

08/17/15 Ansoft Corporation-Harmonica ® v8.71 17:25:49 colpitts scheY1

PN1<H1>
colpitts_schematics_350 MHz.ckt
0.00
colpitts scheY1
Top Trace Cc = 3.3 pF, C1 = 20 pF, C2 = 20 pF, Q (L = 89 nH) = 450 PN1<H1>

Lower Trace Cc = 1 pF, C1 = 20 pF, C2 = 20 pF, Q (L = 270 nH) = 450

–50.00 colpitts scheY1
PN1<H1>
PN1<H1> (dBc/Hz)

–100.00

–150.00 Middle Trace Cc = 3.3 pF, C1 = 20 pF, C2 = 20 pF,

Q (L = 22 nH) = 450, Cp = 8.2 pF (Parallel Tuned Circuit)

–200.00
1.00E00 1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06 1.00E07
FDev (Hz)

Figure 18. The results of series- and parallel-tuned circuits for a higher value of inductor Q.

07/21/15 Ansoft Corporation-Harmonica ® v8.71 17:30:43 350 MHz_colrY1

PN1<H1>
50.00

350 MHz_colrY1
PN1<H1>
0.00
PN1<H1> (dBc/Hz)

TR1, TR2, TR3, TR4 with the Values of 350 MHz_colrY1

KF = 1e-08, 1e-09, 1e-10, 1e-11 Respectively PN1<H1>
–50.00

350 MHz_colrY1
PN1<H1>
–100.00

–150.00

–200.00
1.00E00 1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06 1.00E07
FDev (Hz)
X1 = 1.00E03 Hz X2 = 1.00E04 Hz X3 = 1.00E05 Hz X4 = 1.00E06 Hz X5 = 7.20E06 Hz
Y1 = –89.20 dBc/Hz Y2 = –118.57 dBc/Hz Y3 = –144.87 dBc/Hz Y4 = –166.49 dBc/Hz Y5 = –175.17 dBc/Hz

Figure 19. The effect of KF factor on phase noise.

74 August 2016
 07/21/15 Ansoft Corporation-Harmonica ® v8.71 17:33:37 350 MHz_colrY1
PN1<H1>
50.00

350 MHz_colrY1
PN1<H1>
0.00 TR1, TR2, TR3, TR4 Shows Phase Noise Plots
for the Values of AF = 1, 1.5, 2, and 2.5 Respectively
PN1<H1> (dBc/Hz)

350 MHz_colrY1
PN1<H1>
–50.00

350 MHz_colrY1
PN1<H1>
–100.00

–150.00

–200.00
1.00E00 1.00E01 1.00E02 1.00E03 1.00E04 1.00E05 1.00E06 1.00E07
FDev (Hz)
X1 = 1.00E03 Hz X2 = 1.00E04 Hz X3 = 1.00E05 Hz X4 = 1.00E06 Hz X5 = 7.20E06 Hz
Y1 = –89.20 dBc/Hz Y2 = –118.57 dBc/Hz Y3 = –144.87 dBc/Hz Y4 = –166.49 dBc/Hz Y5 = –175.17 dBc/Hz

Figure 20. The effect of the AF factor on phase noise.

L (fm) = 20 log 10 i c = - 126 dBc/Hz.

2
(77)

Ctot
Figure 22 shows the influence of
RF Choke
the tuning diode on the phase noise. CP = 0 +
L
For the purpose of this discussion, the
equivalent-noise resistance is assumed Ctot ∞
to be 1 kX, and three sensitivity curves
–
are shown. For a tuning sensitivity
of more than 100 kHz/V, the varactor
noise dominates. As the tuning sen-
Figure 21. A parallel-tuned circuit with tuning diodes [2].
sitivity increases, the influence of the
oscillator noise itself disappears.

Summary
Based on a systematic approach to the –40
Colpitts oscillator, this article provides 1 MHz/V A = 155 dB/Hz
information for an optimized design and –60 100 kHz/V B = 143 dB/Hz (R&S SMDU)
C = 123 dB/Hz
the resulting phase noise. Starting with –80 Fe = 150 MHz
L(/_) (dBc/Hz)

an explanation of the Colpitts oscilla- fm = 1 kΩ

tor, we have discussed a linear analysis –100
10 kHz/V
based on Y-parameters, followed by an C
–120
S-parameter approach, which is applica-
ble to practically all oscillators; we then –140 B
No Tuning Diode A
moved into the important time-domain
–160
analysis. This allows a very reliable
design, where the simulated, calculated, –180
1 Hz

10 Hz

100 Hz

1 kHz

35 kHz
100 kHz

1 MHz

10 MHz

100 MHz

and the measured results agree well.

This detailed analysis gives a thorough
insight into the design approach and Eight Decades
results of a Colpitts oscillator. Finally, the
noise contribution of the tuning diodes is
added. Interested readers having access Figure 22. The influence of the tuning diode on phase noise [2].

August 2016 75
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Correction
Due to a production error, an incorrect spelling was given Reference
for the surname of the author of the June 2016 “Around the [1] C. Andriese, “Expanding centers for microwave research in Romania,”
IEEE Microwave Mag., vol. 17, no. 6, pp. 102–103, June 2016.
Globe” column [1]. The correct spelling is Cristian Andriesei.

Digital Object Identifier 10.1109/MMM.2016.2574518

Date of publication: 11 July 2016

76 August 2016