MICROPROCESSOR

SYSTEMS
The Intel Microprocessors
8086/8088, 80186/80188, 80286, 80386,
80486, Pentium, Pentium Pro Processor,
Pentium II, Pentium III, Pentium 4, and Core2
with 64-Bit Extensions

Architecture, Programming, and Interfacing

Eighth Edition, 2009 (By: BARRY B. BREY)

Mohamed M. Eljhani, Ph.D.

Department of Computer Engineering
University of Tripoli
Spring 2023
Chapter 2
The Microprocessor and
Its Architecture
Chapter Outline
◼ Microprocessor as a programmable device
◼ Microprocessor Internal programming model
◼ How its memory space is addressed
◼ Architecture of Intel microprocessors
◼ Ways that addresses the memory system
◼ Real mode
◼ Protected mode
◼ Flat mode
◼ Operation of memory-paging mechanism

Chapter 2 — The Microprocessor and Its Architecture — 2

Microprocessor Architecture
◼ Before a low level program is written or
instruction investigated, internal configuration of
the microprocessor must be known
◼ In a multiple core microprocessor each core
contains the same programming model
◼ Each core runs a separate task or thread (multiple
thread within a task) simultaneously

Chapter 2 — The Microprocessor and Its Architecture — 3

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The Programming Model
◼ Registers of 8086 through Core2 considered
program visible
◼ Registers are used during programming and are
specified by the instructions
◼ Other registers considered to be program
invisible
◼ Not addressable directly during applications
programming
◼ 80286 and above contain program-invisible
registers to control and operate protected
memory

Chapter 2 — The Microprocessor and Its Architecture — 23

The Programming Model
◼ The programming
model of the 8086
through the Core2
microprocessor
including the 64-bit
extensions

◼ R8 - R15 found in
the Pentium 4 and
Core2 if 64-bit
extensions are
enabled

Chapter 2 — The Microprocessor and Its Architecture — 24

Memory Address Space
◼ Address Bus: Intel plans to expand the address
bus to 52 bits to address 4 Peta Bytes 252 of
memory
◼ 16 bit => Address Space: 64 K Bytes
◼ 20 bit => Address Space: 1 M Bytes
◼ 32 bit => Address Space: 4 G Bytes
◼ 34 bit => Address Space: 16 G Bytes
◼ 36 bit => Address Space: 64 G Bytes
◼ 38 bit => Address Space: 256 G Bytes
◼ 52 bit => Address Space: 4 Peta Bytes

Chapter 2 — The Microprocessor and Its Architecture — 25

Multipurpose Registers
◼ RAX, 64-bit register
◼ 32-bit register (accumulator) (EAX)
◼ 16-bit register (AX)
◼ 8-bit registers (AH and AL)
◼ The accumulator is used for instructions such as
multiplication, division

Chapter 2 — The Microprocessor and Its Architecture — 26

Multipurpose Registers
◼ RBX, addressable as RBX, EBX, BX, BH, or BL
◼ (base index) holds offset address of a location in the
memory system
◼ RCX, addressable as RCX, ECX, CX, CH, or CL
◼ (count) general-purpose register that also holds the
count for various instructions
◼ RDX, addressable as RDX, EDX, DX, DH, or DL
◼ (data) general-purpose register, holds a part of the
result from a multiplication or part of dividend before a
division

Chapter 2 — The Microprocessor and Its Architecture — 27

Multipurpose Registers
◼ RBP, used as RBP, EBP, or BP
◼ Points to a memory (base pointer) location for
memory data transfers
◼ RDI, addressable as RDI, EDI, or DI
◼ Often addresses (destination index) string destination
data for the string instructions
◼ RSI, used as RSI, ESI, or SI
◼ (source index) register addresses source string data
for the string instructions
◼ Like RDI, RSI also functions as a general-purpose
register

Chapter 2 — The Microprocessor and Its Architecture — 28

Special-Purpose Registers
◼ Include RIP, RSP, and RFLAGS
◼ Segment registers include CS, DS, ES, SS, FS,
and GS
◼ RIP, addresses the next instruction in a section
of memory
◼ Defined as (instruction pointer) of code segment
◼ RSP, addresses an area of memory called
the stack
◼ The (stack pointer) stores data through this pointer
◼ RFLAGS, indicate the condition of the
microprocessor and control its operation
Chapter 2 — The Microprocessor and Its Architecture — 29
Special-Purpose Registers

◼ The rightmost five and the overflow flag are changed by

most arithmetic and logic operations
◼ Flags never change for any data transfer or program
control operation (program sequence)

Chapter 2 — The Microprocessor and Its Architecture — 30

Special-Purpose Registers
◼ C (carry) holds the carry after addition or
borrow after subtraction
◼ Also indicates error conditions
◼ P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity
◼ If a number contains three binary one bits, it has odd
parity
◼ If a number contains two binary ones, or no one bits
(all zeros), it has even parity

Chapter 2 — The Microprocessor and Its Architecture — 31

Special-Purpose Registers
◼ A (auxiliary carry) holds the carry (half-carry)
after addition or the borrow after subtraction
between bit positions 3 and 4 of the result
◼ Z (zero) shows that the result of an arithmetic or
logic operation is zero
◼ S (sign) flag holds the arithmetic sign of the
result after an arithmetic or logic instruction
executes
◼ T (trap) the trap flag enables trapping through
an on-chip debugging feature (executing
instructions one by one)
Chapter 2 — The Microprocessor and Its Architecture — 32
Special-Purpose Registers
◼ I (interrupt) controls operation of the INTR
(interrupt request) input pin
◼ D (direction) selects increment or decrement
mode for the DI and/or SI registers
◼ O (overflow) occurs when signed numbers are
added or subtracted
◼ IOPL (input/output privilege level) used in
protected mode operation to select the privilege
level for I/O devices
◼ 00 is the highest and IOPL of 11 is the lowest

Chapter 2 — The Microprocessor and Its Architecture — 33

Special-Purpose Registers
◼ NT (nested task) flag indicates the current task
is nested within another task in protected mode
operation
◼ RF (resume) used with debugging to control
resumption of execution after the next instruction
◼ VM (virtual mode) flag bit selects virtual mode
operation 8086 in a protected mode system
◼ VM is used to simulate or run DOS in the modern

Windows environment

Chapter 2 — The Microprocessor and Its Architecture — 34

Special-Purpose Registers
◼ AC (alignment check) flag bit activates if a word
or doubleword is addressed on a non-word or
non-doubleword boundary
◼ Example of an alignment-check violation is a word
stored at an byte address, or a doubleword stored at a
word address
◼ VIF (virtual interrupt) is a copy of interrupt flag
(IF flag) bit available to Pentium 4 processor

Chapter 2 — The Microprocessor and Its Architecture — 35

Special-Purpose Registers
◼ VIP (virtual interrupt pending) provides a
virtual mode interrupt for Pentium
◼ Used in multitasking environments to provide the
operating system with virtual interrupt flags
◼ ID (identification) flag indicates that the
Pentium microprocessors support the CPUID
instruction
◼ CPUID instruction provides the system with
information about the Pentium microprocessor such
as its version number and manufacturer

Chapter 2 — The Microprocessor and Its Architecture — 36

Segment Registers
◼ Segment registers used to generate memory
addresses when combined with other registers
◼ Four or six segment registers in various versions
of the microprocessor
◼ Segment register functions differently in real
mode than in protected mode

Chapter 2 — The Microprocessor and Its Architecture — 37

Segment Registers
◼ CS (code) segment holds code (programs and
procedures) used by the microprocessor
◼ DS (data) contains data used by a program
◼ Data are accessed by an offset address or contents of
other registers that hold the offset address
◼ ES (extra) an additional data segment used by
some instructions to hold destination data

Chapter 2 — The Microprocessor and Its Architecture — 38

Segment Registers
◼ SS (stack) defines the area of memory used for
the stack
◼ Stack entry (start point) is determined by the stack
segment and stack pointer registers
◼ FS and GS segment registers available in
80386–Core2 microprocessors
◼ Allow two additional memory segments for access by
programs
◼ Windows uses these segments for internal operations

Chapter 2 — The Microprocessor and Its Architecture — 39

Real Mode Memory Addressing

Chapter 2 — The Microprocessor and Its Architecture — 40

Real Mode Memory Addressing
◼ 80286 and above operate in either the real or
protected mode
◼ Real mode operation allows addressing of only
the first 1M byte of memory space
◼ Real mode memory addresses consist of a
segment address plus offset address
◼ Segment address defines the beginning address of
any 64K-byte memory segment
◼ Offset address selects any location within the
64K byte memory segment

Chapter 2 — The Microprocessor and Its Architecture — 41

Segment and Offset Registers
◼ The code segment register defines the start of
the code segment
◼ The instruction pointer locates the next
instruction within the code segment
◼ Stack, stack data are referenced through the
stack segment at the memory location addressed
by either
◼ Stack pointer (SP/ESP) or
◼ Base pointer (BP/EBP)

Chapter 2 — The Microprocessor and Its Architecture — 42

Real Mode Segment Addresses

Chapter 2 — The Microprocessor and Its Architecture — 43

Segment and Offset Registers
◼ Memory segment beginning
at 10000H, ending at
location IFFFFH, 64K bytes
in length
◼ Offset address, called a
displacement, of F000H
selects location 1F000H in
the memory
◼ The offset address is
always added to the
segment starting address to
locate the data
◼ Segment and offset
address is written as
1000:2000
Chapter 2 — The Microprocessor and Its Architecture — 44
Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 45

Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 46

Segment and Offset Registers
◼ Memory system showing
the placement of four
memory segments
◼ Think of segments as
Windows that can be
moved over any area of
memory to access data
or code
◼ Program can have more
than four or six segments

Chapter 2 — The Microprocessor and Its Architecture — 47

Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 48

Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 49

Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 50

Segment and Offset Registers

Chapter 2 — The Microprocessor and Its Architecture — 51

Protected Mode Memory
Addressing

Chapter 2 — The Microprocessor and Its Architecture — 52

Protected Mode Memory
Addressing
◼ Protected mode memory addressing (80286 and above)
allows access to data and programs located above the
first 1M byte of memory, as well as within the first 1M
byte of memory.
◼ Protected mode is where Windows operates. Addressing
this extended section of the memory system requires a
change to the segment plus an offset addressing scheme
used with real mode memory addressing
◼ In place of a segment address, the segment register
contains selector that selects a descriptor from a
descriptor table. Descriptor describes the memory
segment’s location, length, and access rights
Chapter 2 — The Microprocessor and Its Architecture — 53
Protected Mode 80286 and
Above

Chapter 2 — The Microprocessor and Its Architecture — 54

Selectors and Descriptors
◼ Selector is located in the segment register & offset is
located in the offset register
◼ It selects one of 8192 descriptors from one of two

tables of descriptors (global and local)

◼ In protected mode, segment number can address any
memory location in the system ( start from any location)
◼ Indirectly, the segment register still selects a memory
segment, but not directly as in real mode
◼ For example, in the real mode, if CS = 0008H , the code
segment begins at location 00080H. In the protected
mode, this segment number can address any memory
location in the entire system for the code segment

Chapter 2 — The Microprocessor and Its Architecture — 55

Selectors and Descriptors
◼ Two tables of descriptors
◼ Global descriptors (system descriptor) contain

segment definitions that apply to all programs

◼ Local descriptors (application descriptor) are

usually unique to a specific applications

◼ Each descriptor table contains 8192 descriptors, so a

total of 16,384 total descriptors are available to

application or system at any time, this allows up to
16,384 memory segments to be described in the
system

Chapter 2 — The Microprocessor and Its Architecture — 56

Basic Segmentation in
Protected Mode

Chapter 2 — The Microprocessor and Its Architecture — 57

Protected Mode Segmentation

Chapter 2 — The Microprocessor and Its Architecture — 58

Descriptors and Memory
Segments

Chapter 2 — The Microprocessor and Its Architecture — 59

Descriptors and Memory
Segments

Chapter 2 — The Microprocessor and Its Architecture — 60

8-Byte Segment Descriptors

Chapter 2 — The Microprocessor and Its Architecture — 61

Selectors and Descriptors
◼ Format of
descriptor for the
80286 through the
Core2

◼ Each descriptor is
8 bytes in length

◼ Global and local

descriptor tables
are a maximum of
64K bytes in
length
Chapter 2 — The Microprocessor and Its Architecture — 62
Privilege Levels
◼ The requested privilege level (RPL)
requests the access privilege level of
a memory segment
◼ The highest privilege level is 00 and
the lowest is 11
◼ If the requested privilege level
matches or is higher in priority than
the privilege level set by the access
rights byte, access is granted
◼ For example, if the requested privilege
level is 10 and the access rights byte
sets the segment privilege level at 11,
access is granted because 10 is
higher in priority than privilege level 11

Chapter 2 — The Microprocessor and Its Architecture — 63

Selectors and Descriptors
◼ The base address of the descriptor indicates the starting
location of the memory segment
◼ Paragraph boundary limitation is removed in protected mode,
and segments may begin at any address
◼ G, or granularity bit allows a segment length of 4K to
4G bytes in steps of 4K bytes
◼ If G = 0, the limit specifies a segment limit of 00000H

to FFFFFH
◼ If G = 1, the value of the limit is multiplied by 4K bytes.

The limit is then 00000FFFFH to FFFFFFFFH, this

allows a segment length of 4K to 4G bytes in steps of
4K bytes

Chapter 2 — The Microprocessor and Its Architecture — 64

Selectors and Descriptors
◼ L bit (large) selects 64-bit addresses in a Pentium 4 or
Core2 with 64-bit extensions when L = 1, and 32-bit
when L = 0
◼ Access rights byte controls access to the segment
◼ Describes segment function in the system and allows

complete control over the segment

◼ If the segment grows beyond its limit, the operating

system is interrupted, indicating a general protection

fault

Chapter 2 — The Microprocessor and Its Architecture — 65

Selectors and Descriptors
◼ Access rights byte for the 80286 through Core2 descriptor

Chapter 2 — The Microprocessor and Its Architecture — 66

Selectors and Descriptors
◼ Example: DS contains 0008H,
which accesses the descriptor
number 1 from the global
descriptor table using a
requested privilege level of 00
◼ Descriptor number 1 contains
a descriptor that defines the
base address as 100000H with
a segment limit of 00FFH
◼ This means that the value of
0008H loaded into DS causes
the microprocessor to use
memory locations
00100000H – 001000FFH for
the data segment
Chapter 2 — The Microprocessor and Its Architecture — 67
Program-Invisible Registers
◼ The global and local descriptor tables are found in the
memory system
◼ When a new segment number is placed in a segment
register, the microprocessor accesses a descriptor table
and loads the descriptor into the program-invisible
portion of the segment register
◼ It is held there and used to access the memory segment
until the segment number is again changed
◼ This allows the microprocessor to repeatedly access a
memory segment without referring to the descriptor table

Chapter 2 — The Microprocessor and Its Architecture — 68

Program-Invisible Registers

Chapter 2 — The Microprocessor and Its Architecture — 69

Memory Paging
◼ The memory paging mechanism located within the 80386
and above allows any physical memory location to be
assigned to any linear address
◼ Linear address is defined as the address generated by
a program
◼ Physical address is the actual memory location
accessed by a program
◼ Memory paging is a memory management scheme by
which a computer stores and retrieves data from
secondary storage for use in main memory
◼ System retrieves data from secondary storage in same-
size blocks 4K called pages

Chapter 2 — The Microprocessor and Its Architecture — 70

Memory Paging
◼ Computer can address memory beyond the amount
physically installed on the system
◼ This memory, which is called virtual memory, is actually
a section of a hard disk that's set up to emulate the
computer's RAM

Chapter 2 — The Microprocessor and Its Architecture — 71

Paging Registers
◼ The paging unit is controlled by the microprocessor’s
control registers
◼ Contents of control registers CR0, CR1, CR2, CR3, CR4

Chapter 2 — The Microprocessor and Its Architecture — 72

Paging Registers
◼ The linear address, as generated by software, is broken
into three sections that are used to access:
◼ Page directory entry

◼ Page table entry

◼ Memory page offset address

Chapter 2 — The Microprocessor and Its Architecture — 73

Page Directory and Page Table

Chapter 2 — The Microprocessor and Its Architecture — 74

Flat Mode Memory
◼ Flat memory model or linear memory model refers to a
memory addressing paradigm in which memory appears
to the program as a single contiguous address space
◼ Flat mode has maximum execution speed over other
memory models
◼ CPU can directly (and linearly) address all of the available
memory locations without having to resort to any sort of
memory segmentation or paging schemes
◼ Flat memory model is the most appropriate, because it
provides the simplest interface from the programmer's
point of view, with direct access to all memory locations
and minimum design complexity

Chapter 2 — The Microprocessor and Its Architecture — 75

Flat Mode Memory
◼ Memory system in a Pentium-based computer (Pentium 4
or Core2) that uses the 64-bit extensions uses a flat
mode memory system
◼ The flat model does not use a segment register to
address a location in the memory
◼ The flat model does not select the memory address of a
segment using the base and limit in the descriptor
◼ Address of first byte in the memory is at 00 0000 0000H
and last location is at FF FFFF FFFFH (40-bits address)

Chapter 2 — The Microprocessor and Its Architecture — 76

Flat Mode Memory

Chapter 2 — The Microprocessor and Its Architecture — 77

Memory Models
◼ Flat memory model
◼ Simple interface for programmers, clean design
◼ Greatest flexibility due to uniform access speed
◼ Minimum hardware
◼ Maximum execution speed
◼ Not suitable for general multitasking operating systems

Chapter 2 — The Microprocessor and Its Architecture — 78

Memory Models
◼ Paged memory model
◼ Suitable for multitasking operating system
◼ Suitable for virtual memory implementation
◼ Lower speed
◼ More complex to program
◼ Fixed page boundaries, not the most memory efficient
◼ This is the memory model Pentium Pro and newer x86
CPUs use

Chapter 2 — The Microprocessor and Its Architecture — 79

Memory Models
◼ X86 segmented memory mode
◼ Variable page boundaries, more efficient and flexible
than the paged memory model
◼ Quite complex from a programmer's point of view
◼ More difficult for compilers
◼ segment : offset combinations, resolve to the same
physical address
◼ Address = (segment x 16) + offset

◼ Implemented in the original Intel 8086, 8088, and

supported by 80386 and all subsequent x86 machines
through to present day Pentium and Core 2 processors

Chapter 2 — The Microprocessor and Its Architecture — 80