1.

Event vs Process-oriented simulation

In FPGA design, "event-oriented simulation" focuses on simulating a design based on changes in

signal values (events), triggering calculations only when a signal changes, while "process-oriented
simulation" models the design as a series of sequential steps or processes, simulating the flow of
data through the design based on defined actions and dependencies between them; essentially,
event-based is more reactive to signal changes, while process-based simulates the overall flow of
operations within the design.

Key differences:
Triggering mechanism:
 Event-oriented: Simulation advances only when a signal value changes, making it efficient
for complex designs with many potential state transitions.
 Process-oriented: Simulation progresses based on the completion of defined processes or
steps, which can be useful for modeling complex data flows and control logic.

Focus:
 Event-oriented: Primarily concerned with capturing precise timing behavior and accurately
simulating signal changes.
 Process-oriented: Emphasizes the logical sequence of operations within the design, often
used to analyze system-level behavior.

Advantages of event-oriented simulation:

 Faster simulation speed: By only evaluating changes when they occur, event-based
simulation can be significantly faster for large designs with many potential state transitions.
 High timing accuracy: Provides precise timing information due to its focus on signal
changes.

Advantages of process-oriented simulation:

Intuitive modeling:
Can directly reflect the design's logical flow and decision-making process, making it easier to
understand and debug complex systems.
System-level analysis:
Useful for analyzing overall system behavior, including data dependencies and resource
utilization.

 When to use which approach:

Use event-oriented simulation when: Verifying timing critical circuits, Debugging complex
state machine behavior, Testing for race conditions.
Use process-oriented simulation when: Modeling complex data processing pipelines, Analyzing
system-level performance and resource usage, High-level design validation.

2. Logic simulation : is to mimic and validate the functions and features of digital circuit
designs written in hard- ware description languages (HDL). This process aims to verify whether
the circuit design meets its intended purpose by simulating hardware behavior within a
computerized environment.

 Techniques of logic simulation in FPGA design:

Testbenches: A crucial component, a testbench is a dedicated HDL code module that generates
input stimuli for the design under test (DUT) and compares the resulting outputs against expected
values, allowing for comprehensive testing of different scenarios.
Stimulus generation: The testbench creates various input patterns (test vectors) to exercise all
possible functionalities of the design, including edge cases and corner conditions.
Waveform visualization: Simulation tools display the input and output signals as waveforms
over time, enabling visual analysis of signal transitions and timing relationships.
Assertion checking: Advanced features allow designers to define assertions (specific conditions
that must be true at certain points in the simulation) to catch potential design flaws early on.

Benefits of logic simulation in FPGA design:

Early error detection: By simulating the design before physical implementation, designers can
catch errors and design flaws early in the development process, reducing the need for expensive
hardware debugging later.
Design verification: Logic simulation provides a robust method to verify that the design meets
its functional requirements and operates correctly under various conditions.
Optimization and performance analysis: By analyzing the simulation results, designers can
identify areas for improvement and optimize the design for performance and power efficiency.

3. Logic Simulation Algorithms:

In an FPGA design environment, "algorithms in logic simulation" refer to the computational
processes used within the simulation software to evaluate the behavior of a digital circuit designed
using hardware description languages (HDLs), essentially simulating how the circuit's logic gates
would react to different input signals, allowing designers to verify the functionality of their FPGA
design before physically programming it onto the chip.

Key aspects of logic simulation algorithms in FPGA design:

Event-driven simulation: This is the most common approach where the simulation engine only
calculates the logic state of a component when its input signals change, making it efficient for
complex designs with many interconnected logic blocks.

Level-sensitive simulation: This method considers the timing of signal changes, simulating how
signals propagate through the circuit taking into account gate delays and propagation delays,
critical for high-speed designs.

Combinational logic evaluation: For combinational circuits, where the output is directly
dependent on the current input values, the simulation engine performs logic operations (like
AND, OR, XOR) based on the input signals to calculate the output.

Sequential logic evaluation: When dealing with flip-flops and other sequential elements, the
simulation engine needs to track the state of the circuit over time by updating internal state
variables based on the current inputs and previous states.
Timing analysis: The simulation software can perform timing checks to identify potential timing
violations like setup and hold time issues, which can be crucial for ensuring proper circuit
operation at high frequencies.

Common algorithms used in logic simulation:

Breadth-first traversal: Used to efficiently evaluate combinational logic circuits by traversing
through the circuit's logic gates level-by-level, calculating the outputs of each gate based on the
current input values.
Depth-first traversal: Can be used for more complex circuits with feedback loops, where the
simulation engine recursively evaluates the logic paths to determine the final state.
State machine simulation: For circuits with sequential logic, the simulation engine tracks the
current state of the state machine and updates it based on the current input and the state transition
table.
How logic simulation algorithms are used in FPGA design:
Verifying design functionality: By running different input scenarios through the simulation,
designers can check if the circuit outputs match the expected behavior, identifying potential
design errors before synthesis and implementation on the FPGA hardware.
Debugging design issues: When errors occur, the simulation can be used to step through the
circuit's logic, analyzing the state of different signals at various points in time to pinpoint the
source of the problem.
Performance analysis:
By simulating the circuit under different clock frequencies and load conditions, designers can
evaluate the timing characteristics and identify potential bottlenecks in the design.

Impact of languages on FPGA design

Implementing a design for an FPGA ultimately comes down to using one or more
software-programming-like languages to define the functionality of the device.

The traditional languages used for FPGA development are VHDL and Verilog.

Current-generation FPGA development tools generally support both of these

languages together with the ability to define system configurations using block
diagramming techniques. Some tool suites also support the definition of FPGA
functionality using the traditional C and C++ programming languages.

VHDL

VHSIC Hardware Description Language (VHDL), where VHSIC stands

for Very High-Speed Integrated Circuit, has syntax reminiscent of the Ada
programming language. VHDL was developed under the guidance of the US
Department of Defense beginning in 1983.

Like Ada, VHDL tends to be quite verbose and rigidly structured. In programming
language terms, VHDL is strongly typed. The language contains a predefined set of
base data types,
principally boolean, bit, bit_vector, character, string, integer, real, time, and array. All
other data types are defined in terms of the base types.

A set of VHDL libraries has been defined by the Institute of Electrical and
Electronics Engineers (IEEE) and formalized as the IEEE 1164
standard, Multivalue Logic System for VHDL Model Interoperability. These libraries
define the set of logic values to be used in the VHDL language. This library includes
a type named std_logic, which represents a 1-bit signal.

The “strong” 0 and 1 values in the preceding figure represent signals driven to the
specified binary state. The “weak” signals represent signals driven on a bus with
multiple drivers where any driver can assert itself on the bus, overriding the other
drivers. The Z value represents a CMOS output in the high-impedance state, where
rather than driving the bus to a 0 or 1 state, the high-impedance state, where rather
than driving the bus to a 0 or 1 state, the output is instead effectively disconnected
from the bus and does not drive it at all. The U state represents the default values for
all signals. When performing circuit simulation, any signal in the U state will be
detected, which likely indicates an uninitialized value is being used unintentionally.
The X state is associated with wires that do not have any outputs driving them. The –
state represents inputs that are unused, and therefore it does not matter what state they
are in. VHDL circuit designs generally begin by importing the IEEE 1164 libraries via
the following statements:
library IEEE;
use IEEE.std_logic_1164.all;

We will use VHDL in our project example later in the chapter. This is not intended to
represent a strong preference for VHDL over Verilog. Both hardware definition
languages are fully capable of representing essentially any design that can be
synthesized for an FPGA.

Verilog

The Verilog Hardware Description Language (HDL) was introduced in 1984 and
became standardized as IEEE 1364 in 2005. In 2009, the Verilog standard was
combined with the SystemVerilog standard to produce IEEE Standard 1800-2009.
SystemVerilog contains extensive facilities for performing system verification, in
addition to the hardware design features present in Verilog.

Verilog was designed to resemble the C programming language, including similar

operator precedence and the use of some of the same control flow keywords,
including if, else, for, and while.

Verilog uses the concept of a wire to represent signal states. A signal value can take
any of the values 0, 1, don’t care (x), or high impedance (z), and can have
a strong or weak signal strength.

Both VHDL and Verilog define language subsets that can be used to design logic
circuitry. These subsets are referred to as the synthesizable language subsets.
Additional language features beyond the synthesizable subsets are available to support
tasks such as circuit simulation. We’ll see an example of this later in this chapter.

Non-synthesizable language constructs tend to behave more like traditional software

programming languages. For example, a non-synthesizable for loop iterates through a
block of code sequentially the specified number of times, just like in a regular
programming language. A synthesizable for loop, on the other hand, becomes
effectively unrolled to generate a collection of replicated hardware constructs that
execute in parallel representing each iteration of the loop.

C/C++

A number of vendors offer software tools that translate traditional high-level

programming languages, often C and C++, into HDL code for use in FPGA
development. This approach may be attractive if you have a complex algorithm in C
or C++ that you would like to accelerate in an FPGA implementation. These tools
also allow software developers who are familiar with C/C++ to immediately begin
implementing code for FPGA use without a need to learn one of the HDLs.

While FPGA development tools for these high-level languages are capable of significant
optimization of the resulting FPGA implementation of the C/C++ code algorithm, there is still
something of a disconnect in that the C/C++ execution model involves the sequential execution of
statements while the native FPGA environment consists of parallel hardware components. The
FPGA design resulting from C/C++ code typically resembles a collection of state machines that
manage the sequential execution of the operations defined in the programming language
statements. Depending on the availability of opportunities for parallel execution within the C/C++
code, an FPGA implementation may provide a significant performance enhancement compared to
running the same code on a traditional processor.

In modern FPGA development tool suites, all of the methods of FPGA

implementation described in this section (VHDL, Verilog, block diagrams, and C/C+
+) can be combined in a single design, if needed. Because of this, one team member
may prefer to work in VHDL while another uses Verilog. There may be project
management reasons for discouraging multi-HDL use within a single project, but the
languages themselves function together in a single design without issue. One reason a
project manager may wish to avoid the use of multiple HDLs is that the future
sustainment of the effort will require the participation of developers with skills in both
languages.

Similarly, it is possible to define a high-level architecture for a project in terms of a

block diagram and then implement detailed subsystem functionality using the HDL of
choice. In the same design, it is also possible to integrate HDL generated from a C/C+
+ algorithm. Embedded system architects and developers should carefully consider
the implications and select the appropriate implementation method for each portion of
an FPGA design.