Release Notes

Release Notes - 88E6321_88E6320 Rev A0

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Overview

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This document is an update/supplement to the datasheet. It contains the following sections.

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Revision Identification: This section describes how to identify the revision of the device covered in this
document.

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Revision Updates: This section summarizes the bugs closed and new features added, when compared to

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the previous revision (if applicable).

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Errata: This section summarizes the known errata for the 88E6321_88E6320 Rev A0.

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Customer Information: This section discusses important features or modes. These features or modes
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may not be common in similar parts and may differ from what the customer might be accustomed to. It is
critical that customers read this section carefully.
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Datasheet Revisions: This section contains the latest changes made to the datasheet or changes that will
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be made in the next revision of the datasheet. Please refer to the relevant sections in the datasheet as well.
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1. Revision Identification
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The 88E6321_88E6320 Rev A0 can be identified in software by reading a value of 0x310 (88E6321

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device) or 0x115 (88E6320 device) from the Switch Identification Register at Port 0 Address 0x3.
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The package identifies the revision of the 88E6321 device as shown in Figure 1.
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Logo
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88E6321-NAZ2 ND k22
Part numbe, package code and Environmental Code
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Part Number = 88E6321

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Lot Number Package Code = NAZ

Environmental code “2”=Green
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Country of origin YYWW A0@

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contained on mold Country Date code, die revision, assembly plant code
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ID or marked on last
line of package Date Code = YYWW
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Die Revision = A0
Assembly plant code = @
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Pin 1 location
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Figure 1: 88E6321 Device Package Markings

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http://www.marvell.com
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Release Notes - 88E6321_88E6320 Rev A0

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14 in
The package identifies the revision of the 88E6320 device as shown in Figure 2.

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Logo

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Part numbe, package code and Environmental Code

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88E6320-NAZ2
Part Number = 88E6320
Package Code = NAZ

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Lot Number
Environmental code “2”=Green
Country of origin YYWW A0@

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contained on mold
Country Date code, die revision, assembly plant code
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line of package Date Code = YYWW
Die Revision = A0
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Assembly plant code = @

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Pin 1 location
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Figure 2: 88E6320 Device Package Markings

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The 88E6321_88E6320 Rev A0 devices are not speed code marked.

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2. Revision Updates

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Errata fixed: This is the first revision of the device.
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New features: This is the first revision of the device.
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Release Notes - 88E6321_88E6320 Rev A0

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3. Errata

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3.1 Ingress monitor source does not work if Port Ingress Rate Limiting is used.

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When Port Ingress Rate Limiting (PIRL) is used and ingress rate limiting also used ingress monitor source
will have no effect.

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Work around: Use one of the IRL resource to limit IMS bucket type by setting:

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Bucket Type Mask=0x1000

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Bucket Increment = 0x64

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Bucket Rate Factor = 0x3e80
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This will result in allowing IMS to work at the rate defined by the other IRL resources.
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3.2 Internal PHY packet generator may not generate the correct number of packets.
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When an internal PHY linked in Energy Efficient Ethernet (EEE) mode the packet generator may not

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generate the correct number of packets.

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Workaround: Disable advertising of EEE

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3.3 RGMII timing may be out of spec when transmit delay is enabled
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When transmit delay is enabled via Port register 1 bit 14 = 1, duty cycle may be out of spec. Under very
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rare conditions this may cause the attached device receive CRC errors.
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Workaround:
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1. Write Port 5 Register offset 0x1A (decimal 26) with 0xE000
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2. Write Port 4 Register offset 0x1A (decimal 26) with 0xC1E7

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3. Write Port 4 Register offset 0x1A (decimal 26) with 0x81E7

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3.4 Ingress rate limiting burst testing may fail

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When using PIRL bucket may fail to drain after a single burst. Subsequent burst size limiting may fail.
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Normal PIRL operation will work.

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Workaround:
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Write 0x00 To Scratch and Misc Index 0x0a. This will result in slightly more power when the switch is
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completely idle.
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4. Customer Information

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4.1 Fast Link down and EEE

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When using the Fast link down feature in the internal PHY, EEE cannot be used at the same time.

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4.2 Supported SERDES configuration

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The SERDES in this device supports 1000BASE-X, SGMII, and 100BASE-FX. If the S_MODE signal is
sampled high at reset, the SERDES will be configured in 1000BASE-X mode. On startup, the PHY Polling
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Unit (PPU) will poll all devices connected to MDC_PHY and MDIO_PHY. If it reads a non-zero value at
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Address 0 for Port 0 or 1 for Port 1, the PPU will automatically set the PHY Detect bit. While the PHY
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Detect bit = 1, the SERDES will operate in SGMII mode. If the software clears the PHY Detect bit, the
SERDES will operate in 1000BASE-X mode. If the S_MODE signal is pulled low, the SERDES will
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operate in 100BASE-FX mode. SERDES mode can be changed with Registers. Refer to the
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Development Board folder on the extranet for changing SERDES modes after reset.
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4.3 SERDES noise filtiering

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When SERDES is operating in 100BASE-FX mode and fiber optics module is disconnected or the SFP
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connector is empty false link may be detected. This can be corrected by enabling the 100BASE-FX noise

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filter.
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Enabling the noise may cause a longer link up/link down time.
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Noise filtering can also be enabled for 1000BASE-X but should not be necessary due to the more robust
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sync pattern.
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4.4 Synchronous Ethernet (88E6321 Device Only)

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Synchronous Ethernet requires an external clock conditioning circuit to receive the clock on RCLK pin.
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This circuit must qualify and clean up the clock and then provide a continuous 25 MHz clock the
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SE_SCLK pin.
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If the PHY recovering clock is 1000BASE-T mode it should be configured as follows:

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• Slave mode (1000BASE-T only)

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PHY Page 0 Register 9 bit 12=1, bit 11=0

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• Fast link down

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PHY Page 0 Register 26 bit 0=1 and register 11:10=0x0-0x3

• Enable PHY to generate clock to witch core
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o PHY Page 2 Register 16 bit 10=1

• Stop clock when link goes down
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o PHY Page 2 Register 16 bit 11=1

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Release Notes - 88E6321_88E6320 Rev A0

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4.5 Accessing clause 45 registers on internal PHYs

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Clause 45 registers on internal PHYs must be done via clause 22 registers.

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Clause 22 registers are accessed via Page 0 Register 13 and 14.
Please refer to Clause 22 access to Clause 45 register (MND) in device functional specs.

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4.6 Managing Energy Efficient Ethernet (EEE) mode

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In this device EEE is auto negotiated by the PHY but is controlled by the switch port (mac). EEE can be

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disabled or enabled with registers PHY register access. To enable EEE mode, the EEE advertising
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needs to be changed and then the PHY must be reset.
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To enable or disable EEE mode for 1000BASE-T and 100BASE-TX modes, the following sequence can
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be used:
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To disable EEE:
Page 0, Register 22 = 0x0000
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Page 0, Register 13 =0x0007
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Page 0, Register 14 = 0x003C
Page 0, Register 13= 0x4007

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Page 0, Register 14 = 0x0000

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To enable EEE

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Page 0, Register 22 = 0x0000

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Page 0, Register 13 = 0X0007
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Page 0, Register 14 = 0X003C
Page 0, Register 13 = 0x4007
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Page 0, Register 14 = 0x0006
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After changing EEE advertising the PHY must be reset with PHY Page 0 Register 0 bit =0x9140
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Release Notes - 88E6321_88E6320 Rev A0

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5. Release Notes History

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The Release Notes History section lists the entries made to the Release Notes document, sorted by date.
The Release Notes are periodically submitted to the extranet and may not reflect the actual date of an

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errata discovery.

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Document Revision History Table:

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Entry Date Entry Description
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February 20, 2019 Released.

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November 21, 2018 Corrected Revision to Rev A0

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June 21, 2018 Initial release.

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No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the
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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such
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information.
Copyright © 2019. Marvell International Ltd. All rights reserved. Marvell and the Marvell logo are registered trademarks of Marvell. For a more complete listing of Marvell trademarks, visit
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Patent(s) Pending - Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
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