Lec-27 EE-222
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muneebharoon261Lec-27 EE-222
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muneebharoon261MICROPROCESSOR
SYSTEMS
EE-222
RISC vs. CISC Architectures
How does the computer know
what I’m telling it to do
BELOW YOUR PROGRAM: LEVELS
OF ABSTRACTION
Higher-Level Language temp = v[k];
v[k] = v[k+1];
Program (e.g. C) v[k+1] = temp;
Compiler
lw x5, 0(x2)
Assembly Language lw x6, 4(x2)
Program (e.g. RISCV) sw x6, 0(x2) _
sw x5, 4(x2)
AssemblerINSTRUCTION
EVERY IS DIRECTLY
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language
IMPLEMENTED IN THE HARDWARE
1010 1111 0101 1000 0000 1001 1100 0110
Program (RISCV) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation
Hardware Architecture Description
(e.g. block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
THINK ABOUT IT!
• Every Instruction is Directly Implemented in the Hardware:
• Think in terms of CISC vs. RISC
CISC RISC
MULT 2:3, 5:2 LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
• CISC:
• Variable size instructions -> Complex instruction decoder -> More transistors
• Multi-cycle instructions
• RISC:
• Simplified instructions -> simple instruction decoder
• Single-cycle instructions (mostly)
CHANGING THE ARCHITECTURE
CISC VS. RISC
• Early trend:
• Add more and more instructions to do
elaborate operations – Complex Instruction Set
Computing (CISC)
–
– difficult to learn and comprehend language
super-complicated (slow?) hardware
• Later on:
• Opposite philosophy later began to dominate:
Reduced Instruction Set Computing (RISC)
– Simpler (and smaller) instruction set makes it
easier to build fast hardware
– Let software do the complicated operations by
composing simpler ones
RISC ARCHITECTURE
• Feature 1: RISC processors have a fixed instruction size.
• It makes the task of instruction decoder easier.
• In AVR the instructions are 2 or 4 bytes.
• In CISC processors instructions have different lengths
• E.g. in 8051
• CLR C ; a 1-byte instruction
• ADD A, #20H ; a 2-byte instruction
• LJMP HERE ; a 3-byte instruction
RISC ARCHITECTURE
• Feature 2: Reduce the number of instructions
• Pros: Reduces the number of used transistors
• Cons:
• Can make the assembly programming more difficult
• Can lead to using more memory
7
RISC ARCHITECTURE
• Feature 3: Limit the addressing mode
• Advantage
• Hardwiring
• Disadvantage
• Can make the assembly programming more difficult
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RISC ARCHITECTURE
• Feature 4: Load/Store
LDS R20, 0x200
LDS R21, 0x220
ADD R20, R21
STS 0x230, R20
RAM EEPROM Timers
PROGRAM
Flash ROM ALU
PC: Data
CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
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RISC ARCHITECTURE
• Feature 5 (Harvard architecture): separate
buses for opcodes and operands
• Advantage:
LDS R20, 0x100 ; R20and
opcodes = [0x100]
operands can go in and
ADD R20, R21
ADD of
out R20,R21
the CPU ;together.
R20 = R20 + R21
LDS R20, 0x100
• Disadvantage: leads to more cost in general
purpose computers.
Fetch
Execute
Control bus Control bus
Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus
RISC ARCHITECTURE
• Feature 6: more than 95% of instructions are executed in 1
machine cycle
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MAINSTREAM ISAS
Macbooks & PCs Smartphone-like devices
(Core i3, i5, i7, M) (iPhone, iPad, Raspberry Pi)
x86 Instruction Set ARM Instruction Set
What if there were free and
open ISAs we could use for everything?
THIS CLASS FOCUS: RISC-V
Macbooks & PCs Smartphone-like devices Versatile and open-source
(Core i3, i5, i7, M) (iPhone, iPad, Raspberry Pi) Relatively new, designed for
x86 Instruction Set ARM Instruction Set cloud computing, high-end
phones, small embedded sys.
RISCV Instruction Set
RECOMMENDED READING
• The AVR Microcontroller and Embedded Systems: Using
Assembly and C by Mazidi et al., Prentice Hall
• Chapter-3: Section-9 -> RISC Architecture in AVR
THANK YOU