MICROPROCESSOR

SYSTEMS

EE-222

RISC-V Assembly
Data Transfer Instructions
DATA TRANSFER INSTRUCTIONS

• Data Transfer instructions are

between registers (Datapath)
and Memory
–Allow us to fetch and store operands
in memory
Computer
Processor Memory Devices
Control Input
(“brain”)

Store (to)
Datapath Output
Registers Load (from)
 DATA TRANSFER

• C variables map onto registers;

What about large data structures like arrays?
– Don’t forget memory, our one-dimensional array
indexed by addresses starting at 0

• instructions only operate on registers!

RISCV

• Specialized data transfer instructions move data

between registers and memory
– Store (sw): register TO memory
– Load (lw): register FROM memory
 DATA TRANSFER

• Instruction syntax for data transfer:

memop reg, off(bAddr)
– memop = operation name (“operator”)
– reg = register for operation source or destination
– bAddr = register with pointer to memory (“base address”)
– off = address offset (immediate) in bytes (“offset”)
• Accesses memory at address bAddr+off
• Reminder: A register holds a word of raw data (no type)
– make sure to use a register (and offset) that point to a
valid memory address
 MEMORY

• Memory is just a large, single-dimensional array, with the

address acting as the index to that array, starting at 0.
 MEMORY IS BYTE-ADDRESSED

Assume here addr of lowest

• What was the smallest data type we saw in C? byte in word is addr of word
– A char, which was a byte (8 bits)
– Everything in multiples of 8 bits
(e.g. 1 word = 4 bytes)
… …… … …
• Memory addresses are indexed
by bytes, not words 12 13 143
word 15
• Word addresses are 4 bytes apart 8 9 102
word 11
– Word addr is same as left-most byte
– Addrs must be multiples of 4 to be “word-aligned” 4 5 61
word 7
• Pointer arithmetic not done for you in assembly 0 1 20
word 3
– Must take data size into account yourself
 DOUBLE-WORD MEMORY
ADDRESS

• Double word addresses are 8 bytes

 DATA TRANSFER INSTRUCTIONS

• Load Word (lw)

– Takes data at address bAddr+off FROM memory
and places it into reg
• Store Word (sw)
– Takes data in reg and stores it TO memory at
address bAddr+off
• Example Usage:
# addr of int A[] -> s3, a ->
s2
lw t0,12(s3) # $t0=A[3]
add t0,s2,t0 # $t0=A[3]+a
sw t0,40(s3) # A[10]=A[3]+a

Remember! Pointer arithmetic not done for you in assembly

–Must take data size into account yourself
 CHECK YOURSELF

• How the addressing in the previous example will change if

we assume double-word memory?
Data Transfer Instructions Cont.…
 TRADING BYTES WITH MEMORY
(2 APPROACHES)

• Method 1: Move words in and out of memory using bit-masking

and shifting
lw s0,0(s1)
andi s0,s0,0xFF # lowest
byte
• Method 2: Load/store byte instructions
lb s1,1(s0)
sb s1,0(s0)
*(s0) = 0x00000180
00 00 01 80
 Endianness
• Big Endian: Most-significant byte at least
address of word
– word address = address of most
significant byte

• Little Endian: Least-significant byte at

least address of word
– word address = address of least
significant byte
*(s0) = 0x00000180
big endian 0(s0) 1(s0) 2(s0) 3(s0)

msb 00 00 01 80 lsb

3(s0) 2(s0) 1(s0) 0(s0) little endian

• RISC-V is Little Endian

 Byte Instructions
• lb/sb utilize the least significant
byte of the register
– On sb, upper 24 bits are ignored
– On lb, upper 24 bits are filled by
sign-extension
• For example, let *(s0) =
0x00000180:
lb s1,1(s0)# s1=0x00000001
lb s2,0(s0)# s2=0xFFFFFF80
sb s2,2(s0)# *(s0)=0x00800180
 HALF-WORD INSTRUCTIONS

UNSIGNED INSTRUCTIONS

• lh reg, off(bAddr) “load half”

• sh reg, off(bAddr) “store half”
– On sh, upper 16 bits are ignored
– On lh, upper 16 bits are filled by
sign-extension
• lhu reg, off(bAddr)“load half unsigned”
• lbu reg, off(bAddr)“load byte unsigned”
– On l(b/h)u, upper bits are filled by zero-extension
• Why no s(h/b)u? Why no lwu?
Decision Making Instructions
 COMPUTER DECISION MAKING

• In C, we had control flow

– Outcomes of comparative/logical statements
determined which blocks of code to execute

• In RISCV, we can’t define blocks of code; all we

have are labels
– Defined by text followed by a colon (e.g. main:)
and refers to the instruction that follows
– Generate control flow by jumping to labels
– C has these too, but they are considered bad style
 DECISION MAKING
INSTRUCTIONS

• Branch If Equal (beq)

–beq reg1,reg2,label
–If value in reg1 = value in reg2, go to label
• Branch If Not Equal (bne)
–bne reg1,reg2,label
–If value in reg1 ≠ value in reg2, go to label
• Jump (j)
–j label
–Unconditional jump to label
 BREAKING DOWN THE IF ELSE

 C code:
if (i==j) f = g+h;
else f = g-h;
 f, g, … in x19, x20, …
 Compiled RISC-V code:
bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit // unconditional
Else: sub x19, x20, x21
Exit: …
Assembler calculates addresses
 BREAKING DOWN THE IF ELSE

C Code: RISCV (beq):

if(i==j) { # i→s0, j→s1
a = b /* then */ # a→s2, b→s3
} else {
beq s0,s1,then
???
a = -b /* else */
else:
??? This label unnecessary
}
sub s2, x0, s3
In English: j end
• If TRUE, execute the THEN then:
block add s2, s3, x0
• If FALSE, execute the ELSE end:
block
 BREAKING DOWN THE IF ELSE

C Code: RISCV (bne):

if(i==j) { # i→s0, j→s1
a = b /* then */ # a→s2, b→s3
} else {
bne s0,s1,else
???
a = -b /* else */
then:
???
}
add s2, s3, x0
In English: j end
• If TRUE, execute the THEN else:
block sub s2, x0, s3
• If FALSE, execute the ELSE end:
block
 BRANCHING ON CONDITIONS
OTHER THAN (NOT) EQUAL

• Branch Less Than (blt)

– blt reg1,reg2, label
– If value in reg1 < value in reg2, go to label
• Branch Greater Than or Equal (bge)
– bge reg1,reg2, label
– If value in reg1 >= value in reg2, go to label
• Example
• if (a > b) a += 1;
• a in x22, b in x23

bge x23, x22, Exit // branch if b >= a

addi x22, x22, 1
Exit:
 SIGNED VS. UNSIGNED

• Signed comparison: blt, bge

• Unsigned comparison: bltu, bgeu

• Example

• x22 = 1111 1111 1111 1111 1111 1111 1111 1111

• x23 = 0000 0000 0000 0000 0000 0000 0000 0001
• x22 < x23 // signed
• –1 < +1
• x22 > x23 // unsigned
• +4,294,967,295 > +1
 BRANCHING ON CONDITIONS
OTHER THAN (NOT) EQUAL

• Set Less Than (slt)

– slt dst, reg1,reg2
– If value in reg1 < value in reg2, dst = 1,
else 0

• Set Less Than Immediate (slti)

– slti dst, reg1,imm
– If value in reg1 < imm, dst = 1, else 0
 RECOMMENDED READING

• RISC-V Edition - Computer Organization and Design_ The

Hardware Software Interface - David A. Patterson, John L.
Hennessy:
• Chapter-2
 ACKNOWLEDGEMENTS

• The slides in this lecture contain materials and illustrations developed and
copyright by:
• Prof. David A. Patterson and Prof. John L. Hennessy [UC Berkely]
• Prof. Onur Mutlu [ETH Zurich]
• Steven Ho and Nick Riasanovsky[UC Berkely]
• Arvind (MIT)
• Krste Asanovic (MIT/UCB)
• Joel Emer (Intel/MIT)
• James Hoe (CMU)
• John Kubiatowicz (UCB)
• Lavanya Ramapantulu (NTU)
THANK YOU