VERILOGHDL LAB PRACTICAL

URUKSHETR UNVERSID

UNIVERSITY INSTITUTE OF ENGINEERING &

TECHNOLOGY,

KURUKSHETRA UNIVERSITY, KURUKSHETRA

Submitted To: Submitted By:

Dr.Deepti BHAVYA BHARDWAJ
ECE-A'4TH SEM
Assistant Professor
252301016
Dept. of Electronics &
INTRODUCTION TO MODELSIM SE-64 10.5

The purpose of this paper is to provide a personalized (arnd therefore limited)

history ofsimulation modeling as it has been largely popularized through the
Winter Simulation Conference. Using simulation in a problem-solving
context requires several proficiencies:

Defining the problem correctly and setting the objects.

Using modeling concepts for abstracting the essential features of the
system intoa model.

Collecting and compiling data and input for the model.

Converting the model into computer readable code that is capable of
simulatingthe system. Instructing the computer to perform the
simulation correctly and efficiently forvarious scenarios.
Summarizing and analyzing the simulation output into performance
measures.

Kiviat (1967) was among the first to describe the modeling process and the
proficiencies needed. A user with in-depth knowledge of almost any
general purpose programming language can provide most of these
proficiencies. However, the burdenof achieving a final simulation is
formidable as the programmer needs to provide software to accomplish all
the needed components including random number generation, random
variate generation, status updating and time advance, statistical collection
and display, etc. To accomplish all this for a single model is generally
prohibitive and there are simulation languages and simulation libraries to
ease the burden of creating simulations.
WHAT IS MODELSIM SE-64 10.5?

ModelSIM SE-64 10.5 is a multi-language environnment by Mentor graphics

for simulation hardware simulation deseription such as VHDL or Verilog and
system C
and includes a built-in C debugger. ModelSIM SE-64 10.5 can be used
independently,or in conjunction with Intel Quartus Prime. Simulation is
performed using the Graphical user interface (GUI), or automaticallyusing
scripts.

ModelSIM SE-64 10.5 is an easy-to-use yet versatile

VHDL/(System)Verilog/SystemCsimulator by Mentor Graphics. It supports
behavioral, register transfer level, and gate- level modeling. ModelSIM SE
64 10.5 supports all platforms used here at the Department of Pervasive
Computing (i.e. Linux, Solaris and Windows) and many others too. On Linux
and Solaris platforms ModelSIM SE-6410.5 can be found preinstalled on
Department's computers. Windows users, however, must install it by
themselves.

This tutorial is intended for users with no previous experjonte with ModelSIM SE
64
10.5 simulator. It introduces you with the basic flow how to set up ModelSIM SE
64
10.5 simulator, compile your designs and the simulation basics with ModelSIM SE
-64
10.5 SE. The example used in this tutorial is a small designwritten ja VHDL
and onlythe most basic commands will be covered in this tutorial. This
tutorial was made by using version 6.1b of ModelSIM SE-64 10.5 SE on
Linux.
 EXPERIMENT: -1

Aim: Write a program to implement Half adder.

Apparatus required: Modelsim software
Theory: -
The Half-Adder is a basic building block of adding two numbers as two inputs and prod
two outputs. The adder is used to perform OR operation of two single-bit binary numbe
augend and added bits are two input states, and 'carry' and 'sum 'are twO output states
half adder.

In the above table,

1. 'A' and B' is the input states, and 'sum' and 'carry' are the output states.
2. The least significant bit of the sum is defined by the 'sum' bit.

Inputs Outputs
A B SUM CARRY

1 1

-s
B

c
Program to implement a half adder:
module halfadder(sum,cout,a, b);
input a b;
output sum,cout;
Xor x1(sum, a,b);
and at(cout,a,b);
endmodule

Output Window:
Wave -Defait

hadder e 0Data
haddert o Dat
Wadder No Data
haddere oData

800 ns
 EXPERIMENT: -2

Aim: - Write a program to implement Full adder.

Apparatus required: - Modelsim software
Theory: -
The half-adder is used to add only two numbers. To overcome this problem, the fulladder
was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C.
The full adder has three input states and two output states le., sum and carry.
In the above table:
1. 'A' and B' are the input variables. These variables represent the two significant bits
that are going be added.
2. 'Cin' in the third input which represents the carry from the previous loser important
position, in carry bit is fetched.
3. The "Sum' and 'Carry output variables define the output values.
4. The eight rows adder the input variable designates all possible combinations of 0
and 1that can occur in these variables.
Block Diagram:

SUM

Full Adder
B

C in C_out

Truth Table:

INPUT OUTPUT
SUM Carry
A B Cin
Out
0 0
1 1 0
1 1
1 1 1

1 1 0
1
1
1
elel
1
1
1

1
0 1
1
1
Program to implement full adder:
module full adder (sum, cout, A, B, Cin);
input A,B,Cin;
output sum,
cout;wire wl,
w2, w3;
Xor x1 (sum,A, B), x2(sum,w,Cin);
and at(w2,w1,Cin),
a2(w3,A,B);or
o1(Cout,w2,w3);
endmodule

Output Window:
We-Defut

tadoeA

der5
ado CI
fedóer w2

800ps

Viave fade
 EXPERIMENT: 3

Aim: -Write a program to implement 4x1 Multiplexer.

Apparatus required: Modelsim software.
Theory: -
Multiplexer is a combinational circuit that has a maximum of 2 data inputs,
'n' selection lines, and a single output line. One of these data inputs will be
connected tothe output based on the values of the selection lines.
Since there are 'n' selection lines, there willbe 2" possible combinations of
zeros and ones. So, each combination will select only one data input.
Multiplexer is also calledMux.
4x1 Multiplexer:
4x1 Multiplexer has four data inputs I3, 12,1,|0 two selection lines st & so and
one output Y. The block diagram of the 4x1 Multiplexer is shown in the
following figure.
One of these 4 inputs will be connected to the output based on the
combination ofinputs present at these two selection lines.
Block Diagram:

I3
I2 4x1 ’Y
Multiplexer

Io

11
S1 So
Circuit Diagram:
S1
So

Io

Program to implement Multiplexer: -

module
mux4to1()Y,So,S1,I0,1,12,/3);input
I0,1,12,/3,So,S1;
output Y;
wire wt,w2 ,w3 ,w4, SObar,
Stbar;not n1(S1bar ,S1),
n2(SObar, SO);
and af(wt,13,S0,S1), a2(w2,12,S1,SObar), a3(w3,11.S1bar,SO),
a4(w4,/0,sObar,S1b
ar); or

o1(Y,w1,w2,w3, w4);
endmodule
Output:
Wave-Defaut

4 ma42

tiow 600

ATransotot Project Wave

 EXPERIMENT-4
Aim: Write a Program to implement De-multiplexer.

Apparatus required: Modelsim software.

Theory:
A De-multiplexer is a combinational circuit that has only 1 input line and 2 output lines.
Simply, the multiplexer is a single input and multi-output combinational circuit. The
information is received fromthe single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these
outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2 outputs. So, there is a
total of 2'possible combinations of inputs. De-multiplexer is also treated as De-mux.

Circuit Diagram:
electraniclinic.com
DO

E D1
1 to 4
Demultiplexer D2
Input
D3

A B-0

Truth Table:

E A B DO D1 D2 D3

X 1 1 1 1
1 1 1
1 1 1 1

1 1 1 1

1 1 1 1 1
Program For De
multiplexer: module

demux_df1(at,a2,a3,a4,a,f);
output[3:0]a1,a2,a3, a4;
input[3:0]a;
input[1:0]f;,
parameter
d=4'hz;
assign
at=(f==2bO0)?a:d;
assign
a2=(f==2'b01)?a:d;
assign
a3=(f==2b10)?a:d;
assign
a4=(f==2'b11)?a:d;
endmodule

Output window: