Scribd
Upload
3 views10 pages

Lecture_05

The document discusses the Von Neumann Architecture, which serves as a foundational model for designing computers, comprising four main subsystems: Memory, ALU, Control Unit, and Input/Output System. It explains how programs are stored in memory and executed sequentially, along with details about memory subsystems, including access time, size, and operations like fetch and store. Additionally, it highlights the characteristics of RAM and its role in the overall architecture.

Uploaded by

252370019
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3 views10 pages

Lecture_05

The document discusses the Von Neumann Architecture, which serves as a foundational model for designing computers, comprising four main subsystems: Memory, ALU, Control Unit, and Input/Output System. It explains how programs are stored in memory and executed sequentially, along with details about memory subsystems, including access time, size, and operations like fetch and store. Additionally, it highlights the characteristics of RAM and its role in the overall architecture.

Uploaded by

252370019
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

Application of Information and

Communication Technology
(CS-143)
Lecture-05
Instructor: Faizan Bashir
The Von Neumann Architecture

Von
Neumann
Architecture
Designing Computers
• All computers more or less based on the same basic
design, the Von Neumann Architecture!

3
The Von Neumann Architecture
Model for designing and building computers, based on
the following three characteristics:
1) The computer consists of four main sub-systems:
• Memory
• ALU (Arithmetic/Logic Unit)
• Control Unit
• Input/Output System (I/O)
2) Program is stored in memory during execution.
3) Program instructions are executed sequentially.

4
The Von Neumann Architecture
Bus

Processor
(CPU)
Memory Control Input-Output
Unit

ALU
Communicate with
Store data and program
"outside world", e.g.
• Screen
Execute program • Keyboard
• Storage devices
Do arithmetic/logic operations • ...
requested by program
5
Memory Subsystem
• Memory, also called (Random Access Memory),
• Consists of many memory cells (storage units) of a fixed size.
Each cell has an address associated with it: 0, 1, …
• All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a complete cell).
• The time it takes to fetch/store a cell is the same for all cells.
• When the computer is running, both
• Program
• Data (variables)
are stored in the memory.

6
RAM
• Need to distinguish between N
• the address of a memory cell and 0000000000000001
the content of a memory cell 1 bit
• Memory width (W): 0
• How many bits is each memory 1
cell, typically one byte (=8 bits) 2
• Address width (N):
2N
• How many bits used to represent
each address, determines the ...
maximum memory size = address
space
• If address width is N-bits, then
2N-1
address space is 2N (0,1,...,2N-1)

W 7
Memory Size / Speed
• Typical memory in a personal computer (PC):
• 64MB - 256MB
• Memory sizes:
• Kilobyte (KB) = 210 = 1,024 bytes ~ 1 thousand
• Megabyte(MB)= 220 = 1,048,576 bytes ~ 1 million
• Gigabyte (GB) = 230 = 1,073,741,824 bytes ~ 1 billion
• Memory Access Time (read from/ write to memory)
• 50-75 nanoseconds (1 nsec. = 0.000000001 sec.)
• RAM is
• volatile (can only store when power is on)
• relatively expensive

8
Operations on Memory
• Fetch (address):
• Fetch a copy of the content of memory cell with the specified
address.
• Non-destructive, copies value in memory cell.
• Store (address, value):
• Store the specified value into the memory cell specified by
address.
• Destructive, overwrites the previous value of the memory
cell.
• The memory system is interfaced via:
• Memory Address Register (MAR)
• Memory Data Register (MDR)
• Fetch/Store signal

9
Structure of the Memory Subsystem
• Fetch(address)
MAR MDR • Load address into MAR.
F/S • Decode the address in MAR.
Memory Fetch/Stor
decoder e
• Copy the content of memory cell
circuit controller with specified address into MDR.
• Store(address, value)
• Load the address into MAR.
• Load the value into MDR.
...
• Decode the address in MAR
• Copy the content of MDR into
memory cell with the specified
address.
10

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy