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Lesson 3 Intro To Intel MP Architecture

The document provides an overview of Intel's microprocessor architecture, detailing the evolution from early computers like ENIAC to modern CPUs. It discusses key concepts such as Moore's Law, the stored program computer model by John von Neumann, and the significance of the x86 instruction set architecture. Additionally, it covers the components and functions of a CPU, including its pipeline stages, memory registers, and the importance of caching.

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0% found this document useful (0 votes)
5 views46 pages

Lesson 3 Intro To Intel MP Architecture

The document provides an overview of Intel's microprocessor architecture, detailing the evolution from early computers like ENIAC to modern CPUs. It discusses key concepts such as Moore's Law, the stored program computer model by John von Neumann, and the significance of the x86 instruction set architecture. Additionally, it covers the components and functions of a CPU, including its pipeline stages, memory registers, and the importance of caching.

Uploaded by

patrickmontero61
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Intel MP Architecture

CPU

Central Processing Unit


The ‘Brain’
Handles all the computation needed to turn
inputs from memory (like photos from hard
drives) into outputs on your peripherals (image
on your monitor)
Runs your OS
Moore’s Law

the observed trend


showing that we can
double the number of
transistors per unit area
about every two years
CPU Architecture History
The birth of digital computing
1945 computers.
ENIAC - first general-purpose
Electronic Numerical
Integrator and Computer
computer (1946) -

covers 1800 square feet


(size of a modern home)
weighs about 30 tons.
used Vacuum Tubes
John von Nuemann
popularized a new kind of computer architecture
that simplified computer design and
programming.
‘Stored Program Computer’ - reimagined the
general purpose computer as three separate
systems.
John von Nuemann
‘Stored Program Computer’ - reimagined the
general purpose computer as three separate
systems.

CPU
Main Memory Data Path Control FSM I/O Interface

Storing data & Decoding and Executing Instructions Set of


instructions interfaces
1959 Robert Noyce patented first monolithic
integrated circuit.
1971 Intel’s 4004
Fetch Decode 1974 Intel’s 8080
Write Execute 1978 foundational 8086
11th Gen Intel Core
Back
Robert Noyce and Gordon Moore
teamed out and founded Intel.

Intel = Integrated Electronics


4004
1971
2300 transistors
Clock Speed of 740kHz
First general purpose programmable
processor and pack all of the
computational power of the ENIAC
into one tiny device.
Robert Noyce and Gordon Moore
teamed out and founded Intel.

Intel = Integrated Electronics

1971 unvieled the Intel 4004.

4004
1971 Intel’s 4004
1974 Intel’s 8080
1978 foundational 8086
th
11 Gen Intel Core
8086
released in 1978
with it’s x86 instruction set architecture, it became the foundation for
modern CPU design
Binary System
Computing Abstraction
Layers
Binary System
Digital computers uses 0 and 1
ASCII - American Standard Code
for Information Interchange
Computational Abstraction Layers
Applications

Programming Languages

Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors

Physics (Atoms, Silicon, Metals)


Computational Abstraction Layers
Applications
Atoms put together put together in materials like silicon.
Programming Languages

Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates It has excellent semiconductor properties, allowing precise


control of electrical conductivity.
Transistors It is abundant and cost-effective compared to other
semiconductors.
Physics (Atoms, Silicon, Metals) It supports high-temperature operation and reliable
manufacturing processes.
Computational Abstraction Layers
Applications Acts as switches.
Turns ON/OFF with an application of
Programming Languages electrical current or voltage signal.

Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors

Physics (Atoms, Silicon, Metals)


By connecting switches together in specific
arrangement....
Computational Abstraction Layers
Applications We can form Boolean Logic Operators
for performing calculations: AND, OR, NOT = Logic
Programming Languages Gates
Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors Using transistors as switches and connecting the output


of one into an input of another, we can build a variety of
Physics (Atoms, Silicon, Metals)
logic circuit or functional blocks.
Computational Abstraction Layers
Applications Using transistors as switches and connecting the output
of one into an input of another, we can build a variety of
Programming Languages logic circuit or functional blocks.
Such as:
Operating Systems Adders
Multiplexers
Instruction Set Architecture (ISA)
Decoders
Latches
Microarchitecture
Flip-Flops
Execution Units Registers
Counters etc.
Functional Units

Logic Gates

Transistors
Chaining functional blocks together...
Physics (Atoms, Silicon, Metals)
Computational Abstraction Layers
Applications Chaining functional blocks together allows even more
complex logical functions.
Programming Languages
Builds custom execution units for specific functions.
Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors

Physics (Atoms, Silicon, Metals)


Computational Abstraction Layers
Applications Custom execution units for specific calculations.
Programming Languages ALU Arithmetic Logic Unit
Operating Systems
Designing CPU comes down with building specialized
processing elements and connecting them together that
Instruction Set Architecture (ISA) allows complex computation to be done.

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors

Physics (Atoms, Silicon, Metals) Combination of Processing Elements


Computational Abstraction Layers
Applications
Combination of Processing Elements
Programming Languages is called the Microarchitecture

Operating Systems

Instruction Set Architecture (ISA)

Microarchitecture

Execution Units

Functional Units

Logic Gates

Transistors

Physics (Atoms, Silicon, Metals) How do we get from hardware to software?


Computational Abstraction Layers
Applications How do we get from hardware to software?
Programming Languages Set of instructions that defines what kind of operations
can be performed in hardware.
Operating Systems
Language of a computer.
ISA is an abstract model of a computer.
Instruction Set Architecture (ISA)
AKA as Architecture or Computer Architecture.
Microarchitecture ISA describes:
Memory Model
Execution Units Supported Data Types
Registers
Functional Units Behavior of Machine Code
Sequences of 0's & 1's that the CPU must execute.
Logic Gates

Transistors

Physics (Atoms, Silicon, Metals)


Computational Abstraction Layers
Applications How do we get from hardware to software?
Programming Languages Acts like a bridge between software and hardware
Operating Systems
Software Side: A compiler uses the ISA to
Instruction Set Architecture (ISA) transform code in a high level language into a
machine code instructions/language that a CPU
Microarchitecture
can process.
Execution Units
ISA is the dictionary of instructions/data types that the CPU
Functional Units adhering to that ISA must execute.

Logic Gates
Hardware Side: ISA is used as a design spec.
Transistors Tells what operations it needs to execute.

Physics (Atoms, Silicon, Metals)


Software Side: A
compiler uses the
ISA to transform
code in a high level
language into a
machine code
instructions/langua
ge that a CPU can
process.

EAX - Extended
Accumulator Register

Accumulator
Registers (e.g.,
EAX): Used for
arithmetic operations,
often storing
intermediate results.
Microarchitecture
Specific design of Instruction Set
Architecture (ISA)
Fetch Stage
Retrieve the instruction from
memory

Fetch Decode
Write Execute
Back
Decode Stage
Decode the fetch
instructions into native
operations.

Fetch Decode
Write Execute
Back
Execute Stage
Once the instructions have
been decoded, the CPU will
execute them.
Add, Subtract, Mul, Div,
Fetch Decode AND, OR, NOT
Write Execute Compares data (decisions
Back on where to go next based
on the code.) called
Branches.
Write Back
Will store the result:
locally: Registers
Memory

Fetch Decode
Write Execute
Back
CPU’s Pipeline
Sequential stages in a CPU
where instructions pass through
fetch, decode, execute, write-
back stages
Basics of x86
Architecture
1 3

2 4
BUSES

communication
pathways that
connect the CPU with
memory and I/O
devices.
They transfer data,
addresses, and
control signals.
Control Bus
Synchronizes actions between
devices, indicating whether
data is being read or written.
Address Bus
Carries the address of the
data or instruction to be
accessed, acting like a pointer
to locations.
Data Bus
Transfers the actual data or
instructions between CPU,
memory, and I/O devices.
CPU Contains the ff:

High Frequency Clock


Control Unit
ALU
Registers
Memory Registers
A type of computer close to the CPU
Fastest way to access data.
They hold data and instructions
temporarily for quick access during
processing, much faster than
accessing external memory like RAM
CPU Clock
A clock cycle, also known as a
machine cycle or a clock tick, is the
basic unit of time in a computer's
central processing unit (CPU).
It represents one complete operation
of the CPU, including fetching,
decoding, executing, and storing
data.
During each clock cycle, the CPU
performs a series of tasks to execute
instructions and process data.
Measured in oscillation per second.
1GHz = 1 Billion times per sec.
Control Unit
decodes instructions and directs operations to other parts like the ALU,
memory, or I/O devices.
It manages and controls the execution of instructions, ensuring
everything happens in the right order.
Reading from Memory
Memory access is slower than register
access.
1.Place the address of the value you
want to read on the address bus.
2.Changes the processor’s Read pin
(RD) called assert.
3.Wait one cycle for memory to respond.
4.Copy data from data bus to the
destination
Caching
To reduce read/write time for memory, caches are used.
in x86:
Level 1 cache: stored on CPU
Level 2 cache: stored outside and accessed by high
speed data bus.
Intel Architecture
What exactly is an Intel Architecture?
is renowned as the most popular
architecture in personal computers
since its introduction in 1978.
The original Intel® architecture
microprocessors were built on what was called a CISC
(complicated instruction set computer) instruction set
architecture.
Intel Architecture

The key to the longevity of Intel®


architecture is that every newly
introduced product remains backward
compatible to all previous Intel®
architecture CPU’s

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