Lesson 3 Intro To Intel MP Architecture
Lesson 3 Intro To Intel MP Architecture
CPU
CPU
Main Memory Data Path Control FSM I/O Interface
4004
1971 Intel’s 4004
1974 Intel’s 8080
1978 foundational 8086
th
11 Gen Intel Core
8086
released in 1978
with it’s x86 instruction set architecture, it became the foundation for
modern CPU design
Binary System
Computing Abstraction
Layers
Binary System
Digital computers uses 0 and 1
ASCII - American Standard Code
for Information Interchange
Computational Abstraction Layers
Applications
Programming Languages
Operating Systems
Microarchitecture
Execution Units
Functional Units
Logic Gates
Transistors
Operating Systems
Microarchitecture
Execution Units
Functional Units
Operating Systems
Microarchitecture
Execution Units
Functional Units
Logic Gates
Transistors
Microarchitecture
Execution Units
Functional Units
Logic Gates
Logic Gates
Transistors
Chaining functional blocks together...
Physics (Atoms, Silicon, Metals)
Computational Abstraction Layers
Applications Chaining functional blocks together allows even more
complex logical functions.
Programming Languages
Builds custom execution units for specific functions.
Operating Systems
Microarchitecture
Execution Units
Functional Units
Logic Gates
Transistors
Microarchitecture
Execution Units
Functional Units
Logic Gates
Transistors
Operating Systems
Microarchitecture
Execution Units
Functional Units
Logic Gates
Transistors
Transistors
Logic Gates
Hardware Side: ISA is used as a design spec.
Transistors Tells what operations it needs to execute.
EAX - Extended
Accumulator Register
Accumulator
Registers (e.g.,
EAX): Used for
arithmetic operations,
often storing
intermediate results.
Microarchitecture
Specific design of Instruction Set
Architecture (ISA)
Fetch Stage
Retrieve the instruction from
memory
Fetch Decode
Write Execute
Back
Decode Stage
Decode the fetch
instructions into native
operations.
Fetch Decode
Write Execute
Back
Execute Stage
Once the instructions have
been decoded, the CPU will
execute them.
Add, Subtract, Mul, Div,
Fetch Decode AND, OR, NOT
Write Execute Compares data (decisions
Back on where to go next based
on the code.) called
Branches.
Write Back
Will store the result:
locally: Registers
Memory
Fetch Decode
Write Execute
Back
CPU’s Pipeline
Sequential stages in a CPU
where instructions pass through
fetch, decode, execute, write-
back stages
Basics of x86
Architecture
1 3
2 4
BUSES
communication
pathways that
connect the CPU with
memory and I/O
devices.
They transfer data,
addresses, and
control signals.
Control Bus
Synchronizes actions between
devices, indicating whether
data is being read or written.
Address Bus
Carries the address of the
data or instruction to be
accessed, acting like a pointer
to locations.
Data Bus
Transfers the actual data or
instructions between CPU,
memory, and I/O devices.
CPU Contains the ff: