ARM® AMBA®3 AHB-Lite

Overview

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ARM® AMBA® Open Specification
 Open standard (No License required)

 The de facto standard for on-chip communication

 Used as on-chip interconnect for connecting and managing functional blocks in a

System-on-Chip
 Promotes design re-use by defining common interface standards for SoC modules

 AMBA Family: AMBA 5, AMBA 4, AMBA 3 & AMBA 2

 AMBA 5 CHI (Coherent Hub Interface) specification is the latest addition to the AMBA
(mainly used for server and networking SoCs)
 More info: http://www.arm.com/products/system-ip/amba/amba-open-specifications.php
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AMBA Acronyms

 Acronyms

 AMBA®  Advanced Microcontroller Bus Architectures

 AXI  Advanced eXtensible Interface
 ACE  AXI Coherency Extensions
 AHB  Advanced High-Performance Bus
 APB  Advanced Peripheral Bus
 ATB  Advanced Trace Bus
 ASB  Advanced System Bus

Image Source: Google.com

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How to access the full specification?
 Go to http://infocenter.arm.com/

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AMBA 3 AHB-Lite
 Original AHB Specification was part of AMBA 2

 Subset of original AHB

 Reduced interconnect logic

 Simplifies slave design

 Master slave architecture

 Most of the designs have single master in the system

 Multiple masters still possible on multi-layer interconnect

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 AMBA 3 AHB-Lite

Image Source: Walt Disney

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 AMBA 3 AHB-Lite
Master 0

Slave Slave Slave Slave

#1 #2 #3 #4

 Single Master

 Simple slaves

 Easier module design/debug

 No arbitration issues

Image Source: Walt Disney

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 AHB-Lite transactions
 Master
 Register Read
 Register Write
 Burst Read
 Burst Write

 Slave/Peripheral
 Can make Master wait
 Can give error response

Image Source: Walt Disney

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 AHB-Lite Features
 Single Clock Edge operation
 Uni-directional busses
 No tri-state signals
 Good for synthesis
 Pipelined Operation

Image Source: Walt Disney

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 A system based on AHB-Lite

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Components of AHB-Lite System
 Master
 Slaves/Peripherals
 Address Decoder
AHB-Lite Interconnect
 Multiplexor

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AHB-Lite Master

Transfer Response
Address and
AHB-Lite
AHB-Lite Control
Master
Master
Read Data Write Data

Global Signals

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AHB-Lite Slave

Slave Select
Transfer Response
Address and AHB-Lite
AHB-Lite
Control Slave
Slave

Write Data Read Data

Global Signal

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 AHB-Lite Master & Slave
Slave Select

Address and Control

Write Data

AHB-Lite AHB-Lite
Master Slave

Transfer Response

Read Data

Global Signals

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 Decoder & MUX
Address & Control Wdata
AHB-Lite
Transfer Response Slave
ADDR
AHB-Lite
Master SEL1
Read Data
Memory Map SEL2 AHB-Lite
(Address) Slave
Decoder
SEL3

MUX SEL
AHB-Lite
Slave
FF
MUX SEL

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX

Transfer Response, Rdata 2

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 Pipelined Transactions (Conceptual Level)
Data phase
Address phase
N cycles

HCLK

Address &
Control
A

Data
A
& Response

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 AHB-Lite Signals

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AHB-Lite Master Signals
Transfer Response
Address and
AHB-Lite
AHB-Lite Control
Master
Master
Read Data Write Data

Global Signals

AHB-Lite
Master

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AHB-Lite Slave Signals
Slave Select
Transfer Response
Address and AHB-Lite
AHB-Lite
Control Slave
Slave

Write Data Read Data

Global Signal

AHB-Lite
AHB-Lite
Slave
Slave

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AHB-Lite Master & Slave

AHB-Lite
Master

AHB-Lite
Slave

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AHB-Lite Master & Slave

AHB-Lite
Master

AHB-Lite
AHB-Lite
Slave
Slave

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Cortex M0 doesn’t speak the entire language !
 Cortex M0 does not support BURST transaction
 HBURST[2:0] is always 3’b000

 Cortex M0 does not support locked transactions

 HMASTLOCK is always 1’b0

 Cortex M0 issues only non-sequential transfers

 HTRANS[1:0] is either 2’b00 (IDLE) or 2’b10 (Non Sequential)

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AHB-Lite Master & Slave

AHB-Lite
Master

AHB-Lite
AHB-Lite
Slave
Slave

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HTRANS[1:0]
HTRANS Type Description

00 IDLE Master does not wish to perform a transfer

01 BUSY Bus Master is in the middle of a

burst but cannot immediately continue
with the next transfer

10 NON-SEQ Indicates the first transfer of a burst or a

single transfer

11 SEQ The remaining transfers in the burst are

sequential address steps from the previous
transfer. Step size is that of data width of
transfer (which is shown by HSIZE)

Cortex M0 Always generates NON-SEQ Transactions

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HSIZE[1:0]

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HPROT[3:0] Protection Signal Encoding

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Transactions

Data Access

Instruction Fetch

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Control Signals Recap
HTRANS[1:0] HBURST[2:0] HMASTLOCK

IDLE SINGLE UNLOCKED

BUSY INCR LOCKED
NONSEQ WRAP[4|8|16]
SEQ INCR[4|8|16]

HSIZE[2:0] HPROT[3:0]

Byte Data/Opcode
Halfword Privileged/user
Word Bufferable
Doubleword Cacheable
...

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Transfer Response Signals

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 AHB-Lite Transactions

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 Basic transfer - Write
Address phase Data phase

HCLK

HADDR [ 31 : 0 ] A B

HWRITE

HWDATA [ 31 : 0 ] Data (A )

HREADY

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 Basic transfer - Read
Address phase Data phase

HCLK

HADDR [ 31 : 0 ] A B

HWRITE

HRDATA [ 31 : 0 ] Data (A )

HREADY

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AHB Pipelined Transaction
Address Phase A Data Phase A
Address Phase B Data Phase B
Address Phase C Data Phase C
Address Phase ….

HCLK

HADDR A B C

HWRITE A B C

HWDATA A B

HRDATA A B

HRESP OKAY A OKAY B

HREADY

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 Pipelined Operation
Address & Control Wdata
AHB-Lite
Transfer Response Slave
ADDR
AHB-Lite
Master SEL1
Read Data
Memory Map SEL2 AHB-Lite
(Address) Slave
Decoder
SEL3

MUX SEL
AHB-Lite
Slave
FF
MUX SEL

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX

Transfer Response, Rdata 2

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AHB basic signal timing – Adding wait states

Address Phase Data Phase A

A Address Phase B

HCLK

HADDR A B

HWRITE A B

HWDATA A

HREADY A A

HRDATA A

HRESP OKAY A OKAY A

Master will extend Address Phase B

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HREADY (Inform all)
AHB-Lite
Slave 1

AHB-Lite
Master
HREADY
AHB-Lite
Slave 2

AHB-Lite
Slave 3
FF
MUX SEL

HREADYOUT 1

HREADYOUT 2
MUX

HREADYOUT 3

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HRESP – Slave Response

HRESP Event Bus Master operation

OKAY Access completed normally

ERROR Slave aborts access, Master has option of continuing or

(2 cycle response) terminating a burst containing an
ERROR

It is permissible to continuously drive HRESP Low in a system which

does not wish to generate any errors.

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ERROR Response

HCLK

HTRANS NONSEQ SEQ

HADDR A A+4 undef

HREADY

HRESP ERROR ERROR

 If HRESP = ERROR, CM0-DS takes an exception and you should implement appropriate
exception handler to catch the error

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 A simple AHB-Lite Slave

AHB2LED.v

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 AHB2LED TOP LEVEL
Slave Select
Transfer Response
Address and
AHB2LED
Control
Read Data
Write Data
LED
Global Signal

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Sampling Address & Control
Address Phase Data Phase A Data Phase B
A Address Phase B

HCLK

HADDR A B C

HSEL_A

HWRITE

HTRANS A NONSEQ B NONSEQ C NONSEQ

HREADY

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Sampling Address & Control
Data Phase A
Address Phase Data Phase B
Address Phase B
A

HCLK

HADDR A B C

HSEL_A

HWRITE

HTRANS A NONSEQ B NONSEQ C NONSEQ

HREADY

HWDATA A B

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Lab
 Analyse the AHB2LED.v file provided

 In the next lab, we will look into system integration, simulation and implementation of a
complete AHB-Lite System using Cortex M0 Design Start core

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