Guideline

SDC Description Guideline

Document No.: LLWEB-10067594

Date of publication: November 25, 2019
Export control number:
EDA18-RELG-T01-D-1086
EDA18-RELG-T01-D-1087
EDA18-RELG-T01-D-1088
EDA18-RELG-T01-D-1089
EDA18-RELG-T01-D-1090
EDA18-RELG-T01-D-1091
EDA18-RELG-T01-D-1092
EDA18-RELG-T01-D-1093
EDA18-RELG-T01-D-1094
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Contents
1. Overview ........................................................................................................................................................ 5
2. Target Readers .............................................................................................................................................. 6
3. Notice ............................................................................................................................................................. 8
4. Limitations ..................................................................................................................................................... 11
5. How to Read This Document ....................................................................................................................... 12
5.1. Configuration of This Document ........................................................................................................... 12
5.2. Check Rules to Be Applied to Each Design Phase ............................................................................... 12
5.3. Category ................................................................................................................................................ 13
5.4. Severity Levels ...................................................................................................................................... 13
5.5. Recommended Descriptions ................................................................................................................. 14
5.6. Description of Rules .............................................................................................................................. 14
6. Quick Guide to Recommended SDC Descriptions ...................................................................................... 15
7. Recommended SDC Command Descriptions and Check Rules ................................................................ 18
7.1. For All SDC Commands ........................................................................................................................ 18
7.1.1. Common to all SDC commands ..................................................................................................... 18
7.1.2. Check rules .................................................................................................................................... 19
R0001 Prohibition of set_case_analysis definition for the middle hierarchical pin ............................... 19
R0007 Prohibition of create_clock/create_generated_clock definition for the middle hierarchical pin 20
R0017 Prohibition of create_generated_clock definition for the middle hierarchical pin ...................... 21
R0024 Prohibition of set_clock_latency definition for the middle hierarchical pin ................................ 22
R0033 Prohibition of set_clock_uncertainty definition for the middle hierarchical pin .......................... 23
R0037 Prohibition of set_input/output_delay definition for the middle hierarchical pin ........................ 24
R0060 Prohibition of set_disable_timing definition for the bi-directional middle hierarchical pin ......... 26
R0073 Prohibition of set_false_path definition for the middle hierarchical pin ..................................... 27
R0089 Prohibition of set_min/max_delay definition for the middle hierarchical pin ............................. 28
R0097 When an Object Is Specified, the Object Type Is Explicitly Specified ....................................... 29
R0123 Prohibition of set_disable_timing definition for the middle hierarchical cell .............................. 30
7.2. Constants .............................................................................................................................................. 31
7.2.1. set_case_analysis .......................................................................................................................... 31
7.2.2. Check rules .................................................................................................................................... 33
R0002 Prohibition of specification of constant for all data pins of multiplexer ..................................... 33
R0003 Clock driven by a constant value or hanging ............................................................................ 36
R0004 set_case_analysis Settings Are Not Made to Conflict with Each Other. ................................... 38
S0001 The value specified as a Constant logic value must match the actual behavior ....................... 40
7.3. Clock ..................................................................................................................................................... 41
7.3.1. create_clock ................................................................................................................................... 41
7.3.2. create_generated_clock ................................................................................................................. 44
7.3.3. set_propagated_clock .................................................................................................................... 49
7.3.4. set_clock_uncertainty .................................................................................................................... 51
7.3.5. set_clock_latency ........................................................................................................................... 55
7.3.6. set_clock_sense / set_sense ......................................................................................................... 59
7.3.7. set_clock_groups ........................................................................................................................... 60
7.3.8. Check rules .................................................................................................................................... 63
R0005 Constrained clock not used as a clock ...................................................................................... 63
R0006 Multiple paths exist from the clock pin of a sequential cell to different clock sources .............. 67
R0008 A Clock Constraint Is Set to All Register Clock Pins ................................................................. 69
R0010 It Is Specified That All Clocks Are Treated as Ideal (before CTS Execution)............................ 73
R0011 It Is Specified That All Clocks Are Treated as Propagated (after CTS Execution) .................... 75
R0012 A Clock Does Not Converge through More Than One Path ..................................................... 76
R0013 A Clock Is Set to the Point at Which the Clock Signal Is Generated ........................................ 77
R0014 Prohibition of overlap between create_clock commands on the same clock network. ............. 79
R0016 Clock Waveform Definitions Are Set as Clock Constraints ....................................................... 82
R0018 Prohibition of specification of the -invert option in create_generated_clock that is incompatible
with the circuit configuration ................................................................................................................. 84
R0019 Do not specify different value with –divide_by option of create_generated_clock command from
divide ratio which is decided by the circuit ............................................................................................ 87
R0020 A Correct Source Clock Is Specified for a Generated Clock ..................................................... 92
R0023 There Is One Delay Calculation Path for a Generated Clock ................................................... 96
R0025 Detection of the clock pin in which clock latency is not defined (Before CTS) ......................... 99
R0026 Source or network latency not defined for a virtual clock ....................................................... 100
R0027 Necessary Conditions Are Defined for Latency ...................................................................... 102
R0028 A Clock Latency is Set (Before CTS) ...................................................................................... 103
R0029The Source Latency Is Set for a Generated Clock. (Before CTS) ........................................... 104
R0030 set_clock_transition should not be set on clock in postlayout (After CTS) ............................. 105
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R0031 Clock transition value set by using set_clock_transition is outside technology bounds ......... 106
R0032 Clock should be set transition time (Before CTS) ................................................................... 108
R0034 Uncertainty Is Defined for Clock Constraints .......................................................................... 109
R0035 Confirm the lack of conditions in the definition of uncertainty .................................................. 111
R0056 set_input_transition must be defined on clock ports in postlayout stage (After CTS) ............. 113
R0099 Prohibition of specification for clock definition to the select pin of MUX .................................. 114
R0112 A Clock Does Not Converge through More Than One Path. .................................................... 116
R0119 Wildcard Which Matches Object Besides Clock Is Prohibited for set_clock_latency .............. 117
R0120 Prohibition of specification of a clock port for a set_clock_uncertainty multi-clock.................. 119
R0124 A generated clock that has two or more clock sources with branches must not be present... 121
R0125 A generated clock of which the master clock is a multi-clock must not be present ................ 122
R0126 Generated clocks must be defined for all master clocks ........................................................ 124
R0127 Care must be taken with respect to duplicated -name options for a clock definition .............. 126
R0135 Note the size relation of skew when using set_clock_uncertainty .......................................... 127
R0136 Specified point should not be set to jump over the frontward of the generated clock definition
............................................................................................................................................................ 130
R0137 Defining constraints in pair (set_clock_latency) ...................................................................... 132
R0138 Defining constraints in pair (set_clock_uncertainty) ............................................................... 133
R0139 Generated Clocks from the same master clock must be declared exclusive ......................... 134
R0140 The definition of clock exclusive relationship between parent and child clocks should be
eliminated due to over-setting............................................................................................................. 135
R0141 Set up an exclusive relationship between non-interfering clocks ........................................... 136
R0142 Confirm that there is no shortage in the setting of exclusive relationship between clocks ..... 137
R0143 Confirm that there is no error in using the set_clock_groups option....................................... 138
R0144 Use the -physically_exclusive option between clocks that do not physically interfere ........... 139
R0145 Confirm that the set_clock_groups command is set between clocks of the same definition
location. ............................................................................................................................................... 140
R0146 Use the set_clock_groups command to set the false value between clocks .......................... 141
R0147 STA tool accuracy is difficult to guarantee .............................................................................. 142
R0148 Attention to the multiple specification order of the -through option of the timing exception
command. ........................................................................................................................................... 144
R0150 Do not mix ideal clock and propagate clock (after CTS execution) ........................................ 145
S0002 Confirm that the pin specified as ClockSense does not transition .......................................... 147
S0003 Confirm that the settings specified in the derived clock (items that can be checked with SVA)
match the actual operation. ................................................................................................................ 149
7.4. Clock Gating ........................................................................................................................................ 152
7.4.1. set_clock_gating_check ............................................................................................................... 152
7.4.2. Check rules .................................................................................................................................. 157
R0061 Specification for cells except simple function cell like AND, NAND, OR or NOR, etc ............ 157
R0062 Prohibition of specification for the different value to the same cell ......................................... 160
R0063 Prohibition of specification for cell for exclusive use of clock gating....................................... 162
7.5. Input/Output Constraints ..................................................................................................................... 163
7.5.1. set_input_delay/set_output_delay ............................................................................................... 163
7.5.2. Check rules .................................................................................................................................. 168
R0038 Input/Output constraints are incorrect relative to a range of clock period .............................. 168
R0040 Necessary Conditions Are Defined for an External Port Constraint Definition ....................... 169
R0042 Input/output port not constrained by set_input_delay/set_output_delay ................................ 170
R0052 Check conflicts in the external terminal constraint values ...................................................... 175
R0054 A Required Input or Output Delay Is Set for All Connected Clock Domains. .......................... 177
R0057 No input transition constraints defined for inputs/inouts ......................................................... 180
R0058 Load on output or inout ports not set or zero .......................................................................... 181
R0128 Defining constraints in pair ................................................................................................... 183
R0129 Inconsistency between min/max option values ....................................................................... 184
7.6. Exceptions ........................................................................................................................................... 186
7.6.1. set_false_path .............................................................................................................................. 186
7.6.2. set_multicycle_path ..................................................................................................................... 190
7.6.3. set_max_delay, set_min_delay .................................................................................................... 195
7.6.4. Check rules .................................................................................................................................. 198
R0064 Prohibition of overlap between timing exceptions commands ................................................ 198
R0067 Prohibition of specification for the asynchronous set or reset of register ............................... 201
R0068 Option -from/-to not specified for set_false_path/set_multicycle_path command .................. 202
R0069 False/multi-cycle path reference points are not connected .................................................... 204
R0071 -through Is Not Used for an Object for Which -from/-to Can Be Used in a Timing Exception
Constraint. ........................................................................................................................................... 209
R0072 Prohibition of specification for the asynchronous set or reset of register ................................ 211
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R0074 set_false_path constraint is specified and there exists a crossing among the clocks ............ 213
R0075 Paths between Clock Domains Are Specified as a False Path ............................................... 214
R0077 Prohibition of specification for different values to the same path in set_multicycle_path ....... 215
R0078 set_multicycle_path setup or hold over or under defined ....................................................... 217
R0080 Prohibition of specification for the output pin of cell on clock line ........................................... 218
R0082 Reporting any set point that is specified in set_min/max_delay as the start point with an object
other than the clock to an FF/Latch/hard module or external input .................................................... 219
R0084 When the ending point of the timing constraint path is set to besides a data pin of FF and an
output port, the setting point specified by -to option is reported. ........................................................ 220
R0086 Inconsistent set_max_delay and set_min_delay commands .................................................. 220
R0087 set_min/max_delay reference points are not connected ........................................................ 222
R0092 Timing Constraints Are Given to Paths Consisting Only of Combinational Logic ................... 223
R0093 No Inconsistent Constraint Is Given to Paths Consisting Only of Combinational Logic ......... 224
R0095 A Combinational Circuit Contains No Timing Loop. ................................................................ 226
R0121 set_false_path Must Not Be set to Net With ‘-through’ ........................................................... 228
R0122 Set Value to Cell and Clock Pin for set_mux_delay or set_min_delay Must Be Same .......... 229
R0130 Prohibition of specification such that both of -from/-to options are not specified in
set_min_delay/set_max_delay_path .................................................................................................. 230
R0131 Prohibition of specification of set_min/max_delay that affects other paths by being specified for
a point other than start/end points ...................................................................................................... 231
R0132 Exclusive setting must be made for convergence clocks ....................................................... 232
R0133 Prohibition of duplicate objects in the -through timing exception option ................................. 234
R0134 The -start/-end options must be specified explicitly for a multicycle path between clocks of
different frequencies ........................................................................................................................... 235
S0004 The pin specified in FalsePath must not transition to <cycle number -1> .............................. 237
S0005 The pin specified in MultiCyclePath must not transition to <cycle number -1> ....................... 239
7.7. Others ................................................................................................................................................. 241
7.7.1. set_disable_timing ....................................................................................................................... 241
7.7.2. Check rules .................................................................................................................................. 245
R0059 Prohibition of specification for the data pin of register ............................................................ 245
8. Appendix .................................................................................................................................................... 246
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1. Overview
The SDC (Synopsys Design Constraints) format, defined by Synopsys, is used to specify timing constraint
conditions. It is already a de facto standard and supported by many EDA tools.
If the SDC description is insufficient, the following problems occur. Verification does not proceed as expected,
and different interpretations of timing constraints by EDA tools lead to failures to fix timing. Therefore, prior
checking is required to see if constraints defined in the SDC file are appropriate and match intended designs.
It is also required to define how to describe SDC commands and prevent misleading descriptions that may
cause product defects.
To meet such requests, we have merged the SDC Check Rule User’s Guide and the SDC Description
Guideline (this document), making it easy to check recommended descriptions, notice, and SDC rules. In
addition to the conventional way of checking against rules, we have introduced the SVA checker that verifies
the validity of the SDC using logic simulation.

For details of the SDC (Version 2.1), refer to the following document released by Synopsys.
Using the Synopsys® Design Constraints Format Application Note Version 2.1, December 2017
http://edasite.eda.renesas.com/cgi-bin/lv2in/tools/REL/data/manual/manual_4265.pdf

For types and positioning of the SDC checking tools from Renesas and design phases where checking against
rules is required, refer to the following document.
タイミング制約検証フローガイド (LLWEB-10004653)
*This document is described in Japanese

For priority of timing exception constraints, refer to the following document.

EDA ツールのタイミング例外の優先順位
http://edasite.eda.renesas.com/cgi-bin/lv2in/tools/REL/data/document/document_2266.pdf
*This document is described in Japanese
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2. Target Readers
This document is targeted at engineers who create and verify SDC files using the GCA, PTC, and ConCert
tools.
This document supports SDC version 2.1 and earlier versions.
The following SDC commands are supported in this document. Note that other commands are not checked
against SDC rules.

set_case_analysis
create_clock
create_generated_clock
set_propagated_clock
set_clock_uncertainty
set_clock_latency
set_clock_sense
set_sense
set_clock_groups
set_clock_gating_check
set_input_delay
set_output_delay
set_false_path
set_multicycle_path
set_max_delay
set_min_delay
set_disable_timing

The purpose of SDC checking is to improve the quality of SDC files.

There are five types of SDC checking as shown below. This document describes types 1 and 2 below. For
details of type 3, refer to the EDA tool manual. For types 4 and 5, refer to the タイミング制約検証フローガイ
ド.
*This document is described in Japanese

1. SDC semantics checking

This type of checking is intended to detect any problem with SDC command descriptions (regardless of
designs) when there is no problem with SDC syntax.
When there is no problem with syntax, EDA tools run according to set constraints even if the descriptions
of those constraints are not appropriate. Unclear constraints may also be interpreted differently by EDA
tools. Eliminating such unclear constraints will prevent layout-sign-off STA iterations.

2. Timing exception validity checking

This type of checking is intended to confirm that timing exception constraints (set_false_path and
set_multicycle_path) described in the SDC format match the netlist (created based on the specifications)
and the logic simulation result (using the test bench) by using the SVA checker.
Even if there is a problem with a timing exception constraint, EDA tools run according to that constraint,
leading to a possible omission of verification. For this reason, the validity of timing exception constraints
needs to be checked.

3. Consistency checking between SDC and netlist

This type of checking is intended to confirm that all objects (instance name, pin name, and net name)
specified for SDC exist in the netlist. The consistency between SDC and netlist needs to be checked so
that EDA tools will correctly interpret the SDC descriptions (including object specification using a wildcard).
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4. Consistency checking between SDC commands
This type of checking is intended to confirm consistency between multiple SDC commands prepared for
the same design or same design phase. To be specific, it applies to the following SDC descriptions:

⚫ SDC description for multi-corner verification

⚫ SDC description for multi-mode verification
⚫ SDC descriptions for a single chip and that for a specific block
If there is inconsistency among SDC commands, EDA tools may not behave as expected. For this reason,
consistency needs to be checked.

5. SDC equivalence checking between design phases

This type of checking is intended to check if SDC descriptions used in different design phases are logically
equivalent to one another.
SDC descriptions are modified in individual design phases. If there is an error in a modification, SDC
inconsistency may arise among design phases, leading to a possible big backslide. For this reason,
equivalence needs to be checked.
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3. Notice

Important
1. Contact information regarding GCA, PTC, ConCert, check rules, and SVA:
Please access the websites below.
General GCA/PTC, native rules Synopsys, Inc.
https://solvnet.synopsys.com/
ConCert (SVA), custom rules Inquiry about EDA tool
http://edasite.eda.renesas.com/cgi-bin/support/top.cgi

How to distinguish the custom rules

GCA/PTC: Rule names that begin with “UDEF_”

2. Mismatch in specifications of the set_clock_sense command between PrimeTime and Design Compiler/ICC
There is a problem with the set_clock_sense command, that is, it behaves differently depending on tool
versions. To solve this problem, you can have the tools read the tbc file (clock_sense_compatibility.tbc) and
change the specifications of the command. In this case, however, note the differences from the vendor-
supplied documentation. For the behavior of tools after the change in specifications, refer to the following
table.

"set_clock_sense –stop_propagation" in individual tools

Tool Version Clock as clock Clock as data Related command/variable

DC - 2013.12 stop stop ―

2014.09 - stop propagate Reading the

clock_sense_compatibility.tbc file will
apply the former specification.
ICC - 2013.12 stop stop ―

2014.09 - stop propagate Reading the

clock_sense_compatibility.tbc file will
apply the former specification.
ICC-2 All stop propagate Setting “set_sense -type data -
stop_propagation” will apply the
former specification of ICC.
PrimeTime - 2011.12 stop stop ―

2012.06 - stop propagate Reading the

clock_sense_compatibility.tbc file will
apply the former specification.
ConMan/ 3.32.x - stop stop Specification of the command in
ConCert
version 3.34.x will be equivalent to
that of PrimeTime.
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○ Renesas in-house specifications
Specifications between the PrimeTime and Design Compiler/ICC tools can be made consistent as shown
below by reading the tbc file. Whether it is necessary to read the tbc file depends on semiconductor products.
When the tbc file is to be applied to PrimeTime, also apply this file to GCA or PTC before SDC verification.

PrimeTime Design Compiler/ICC Specification consistent /

Version clock as data Version clock as data inconsistent
2012.06 stop 2013.03 stop consistent
2013.12 stop 2013.12 stop consistent
2015.12 stop 2015.06 stop consistent

Note that whether reading of tbc file is necessary varies with the version of the set of Renesas custom rules.

Version of Will the tbc file be automatically

Renesas custom read when the rules are
rules applied?
V01.05.01 No
V01.06.01 No
V01.07.00 Yes
V01.08.00 Yes
V01.09.00 Yes
V02.00.00 Yes
V02.01.00 Yes
V02.01.01 No

The tbc file must be read before the SDC file.

* How to set
source /common/appl/Synopsys/primetime/<Tool_version>/clock_sense_compatibility.tbc

3. Dependency between versions of tool and set of Renesas custom rules

There is a dependency between the versions of GCA/PTC tool and set of Renesas custom rules. When
using PrimeTime-GCA 2012.12-SP2, for example, use “V01.07.00” of Renesas custom rules. Use available
versions in the figure below.

Renesas Custom Rules

V01.06.00 V01.07.00 V01.08.00 V01.09.00 V02.00.00 V02.01.00
V01.09.01 V02.00.01 V02.01.01
Version
V02.01.02
V02.01.03
2012.06 ✓ - - - - -
2012.12-SP2 - ✓ - - - -
2013.06-SP1 - - ✓ - - -
GCA 2013.12-SP1 - - - ✓ - -
Support 2014.06-SP1 - - - - ✓ -
2014.12-SP3-1 - - - - ✓ -
2015.12-SP1 - - - - - ✓
2015.12-SP3 - - - - - ✓

* Do not use V01.09.00, V02.00.00, V02.01.00, or V02.01.01 since they have problems.

For details, refer to the following:

<http://edasite.eda.renesas.com/cgi-bin/lv1ww/tools/cgi/to_sel_menuframe.cgi?lang=en>
[Digital Design] / [Timing Design] / [Timing Design Constraint Generation/Verification] / [GCA]

[Synopsys PrimeTime GCA 2015.12-SP3 (Rule V02.01.01)]

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GCA was renamed to PTC in December 2016 and the startup command was changed. The gca_shell
command cannot be used for startup. Use the pt_shell –constraints command instead for startup.

Renesas Custom Rules

Version V02.01.05 V02.01.06
2016.12-sp3- ✓ -
3-t-20180209
PTC
2017.12- - ✓
Support
SP3-3-VAL-
20190404

* V02.01.04 of custom rules does not exist.

4. Setting timing constraints for objects that may be deleted due to logic synthesis or timing optimization
When setting timing constraints for objects that may be deleted due to logic synthesis or timing optimization,
set “set_dont_touch” and “set_size_only” in advance.

5. For error messages regarding syntax analysis (while reading the SDC file) and causes of errors that are not
described in this document, refer to the Message Guide from Synopsys (on SolvNet).
A message correspondence (between PrimeTime and GCA/PTC) table is being created by Synopsys.
STAR 9000884692 (Synopsys has not yet determined when this document is to be released.)
Request document for error code correspondences between GCA and PrimeTime
 Page 11/257

4. Limitations
・ SDC verification in the RTL design phase is excluded.
(Because SpyGlassConstraints is no longer supported by Synopsys.)
・ The “set_clock_groups” check rules are supported by Rule Set v02.01.06 and later versions.
・ SVA is not supported as of the end of March 2019, but will be released in 2019.
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5. How to Read This Document
5.1. Configuration of This Document
This document, in which the SDC Description Guideline is integrated with the SDC Check Rule User’s Guide,
describes recommended descriptions, notice, and check rules for SDC files. When creating a new SDC file or
adding a new SDC command, follow the recommended description. Even in cases where you cannot strictly
follow the recommended description, refer to the notice on the command and ensure that SDC descriptions
will suit the product specifications. Furthermore, when referring to specific SDC commands, also refer to the
recommended description and notice common to all SDC commands (7.1 For All SDC Commands).

5.2. Check Rules to Be Applied to Each Design Phase

In this document, SDC check rules to be applied are classified into the following phases. Use appropriate
check rules according to the design phase. Using a rule intended for a different design phase may lead to
incorrect checking. Template files that have the same names as individual design phases are available. Specify
the template file corresponding to your desired design phase when executing GCA or PTC.

Design Phase Description

RTL Not described in this document
IP Check rules used for IP design
Layout I/F Check rules used for timing driven layout (TDL)
These rules are assumed to apply to the following cases:
⚫ Timing driven layout for which single-mode merged SDC descriptions
contained in one file are used and only setup timing and no clock delay
are considered when multiple operating modes are available
⚫ SDC descriptions specifically for optimizing critical paths (setup
optimization) without considering hold timing
For more sophisticated TDL such as when clock delays, setup timing, hold
timing, and OCV are considered, apply a rule set with "design-phase=STA"
specified.
STA Rules used for Sign-Off STA
Use STA for gate level checking (after execution of CTS).
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5.3. Category
Types of check rules are classified as follows.
In the chapters of check rules, shortened forms are used for representing categories.

Category Description
The check in this category is intended to check consistency between
Consistency with designs SDC descriptions and designs.
Example) The source of a generated clock is not an upstream node.
The check in this category is intended to detect any problem with SDC
descriptions (regardless of designs) when there is no problem with
SDC semantics syntax.
Example) The specification of a target object is unclear. (The get_xxx
command is not used.)
Tools may put different interpretations on an unclear constraint. The
check in this category is intended to detect a circuit configuration or
Detection of unclear constraints constraint which may lead to an unclear analysis result.
Example) “set_case_analysis” is specified more than once for the
same network.
Constraint check for timing driven layout.
The check in this category is intended to make sure that each
TDL (Timing Driven Layout)
constraint is specific to critical path optimization.
Example) There is a timing path for which optimization is not required.
The check in this category is intended to make sure that each
SDC Description Guideline description follows the rules written in the SDC Description Guideline.
Example) Set a latency for a clock.

5.4. Severity Levels

The following table lists the severity levels of SDC check rules distributed in this document. According to each
severity level, take appropriate actions such as modifying the SDC descriptions.
The severity levels are the same as the severity labels in reports output by tools.
Severity Note

Rules that must always be observed

・ Check rule that always requires modifications
Error ・ Rule that clearly indicates an error
・ Description which will cause a problem in a subsequent process
・ Item to be required in the SDC Description Guideline
Design style item recommended for better circuit quality (e.g., increased area) and readability
・ Description which may cause a problem in a subsequent process
Warning
・ The description should be modified unless it is verified that the description will cause no
problem.
Reference information or item to be noted for specifying timing constraints
Info
Check item for information required for the execution of SDC checking
n/a Item that is not checked
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5.5. Recommended Descriptions
“◆Recommended usage”, “◆Recommended example of command description”, “◆Notice”, “◆Supplement”,
and “Check rules” are described for each SDC command.

Classification of constraints

SDC command name

Recommended usage of the SDC command

Recommended example of command

description with a circuit diagram

“◆Notice” lists notice on using constraints and prohibitions.

“◆Supplement” gives examples of special cases that are not covered by recommended descriptions.
“Check rules” lists rules to check whether any prohibited usage or unrecommended description is present.
(Refer to “5.6 Description of Rules”.)

5.6. Description of Rules

Indicates an SDC description rule.
Severity for each design phase
Rule

Severity RTL Layout I/F STA

Error
Category □ consistency □ semantics □ unclear □ TDL □
description guideline
Check rule RC_MidHierarchySetCaseAnalysis
Indicates the category of the rule.
Check rule name
Description
Simple description on the rule

Sample circuit configuration and constraints

GCA/PTC message
xxxxxxxx GCA or PTC message displayed if the rule is violated.
Action
Limitations
Limitations when the rule is applied, if any.

“Limitations” is omitted when the rule imposes no limitations.

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6. Quick Guide to Recommended SDC Descriptions
This section provides recommended SDC descriptions. Read this section before describing SDC.
Recommended descriptions are not provided for all commands. For details, refer to “7. Recommended SDC
Command Descriptions and Check Rules”.

● Common to all SDC commands

 When specifying an object in an SDC command, indicate the type of object specified by get_* commands
(including get_pins, get_ports, get_nets, and get_clocks).
 To avoid ambiguity of constraints, do not specify middle hierarchy pins as objects.

● Constant
Description example)
set_case_analysis <0|1> [get_ports <input port name> ]

 As <input port name>, specify the name of an input port of the chip or module for which you are describing
constraints.

● Clock

create_clock
Description example)
create_clock -period 10 -waveform {2 7} -name CLK1 [get_ports CLOCK_PORT1]

 Specify the following options for the create_clock command.

➢ Use the -period option to specify the clock period.
➢ Use the -waveform option to specify the clock waveform.
- If the -waveform option is not specified, a waveform is automatically set with rising edge = 0.0 and
duty = 50%. Specify the -waveform option explicitly.
➢ Use the -name option to specify the clock name.
 Specify clock input ports or output pins of clock generating cells as definition points.
 When creating a virtual clock, set the create_clock command without specifying any definition point.

create_generated_clock
Description example)
create_clock -period 20 -waveform {0 10} -name CLK1 [get_ports P1]
create_generated_clock -name MU_CLK -multiply_by 2 -source [get_ports P1] ¥
-master_clock [get_clocks CLK1] [get_pins MU1/Q]

 Use the -name option to specify the generated clock name.

 To specify the generated clock waveform, use any of the following options.
➢ To generate a divided clock, use the -divide_by option.
➢ To generate a multiplied clock, use the -multiply_by option.
➢ To generate a generated clock with the edge positions of the master clock specified, use the -edges
option.
➢ To generate a generated clock (division ratio = 1), use the -combinational option.
 Use the -source option to specify a master clock propagation point.
 Use the -master_clock option to specify the name of the master clock (reference clock).
 Use the -invert option to invert the waveform of the generated clock.
 To create two or more generated clocks for the same definition point, use the -add option.
Also use the -name option to specify the generated clock name.

set_clock_groups
Description example)
create_clock -period 2 -name CLK_T2 [get_ports CLK1]
create_clock -period 4 -name CLK_T4 [get_ports CLK2]
create_clock -period 6 -name CLK_T6 [get_pins OSC/OUT]
set_clock_groups -asynchronous -group {CLK_T2} -group {CLK_T6}

 Using the -asynchronous option is recommended.

 Use the -group option to specify clock(s) for which you want to set asynchronous transfer relationship.
 To set asynchronous transfer relationship between two or more clocks, specify the -group option twice or
more times.
 Page 16/257
 To set asynchronous transfer relationship between two or more specific clocks and other clocks, specify
two or more clocks for the argument of the -group option.

● Clock gating
Description example)
set_clock_gating_check -setup 1.0 -hold 1.0 [get_cells I1]

 When you are describing constraints for a chip, specify an input port of the chip.
 When you are describing constraints for a module, specify an input port of the module.

● Input/output constraints
Description example)
create_clock -period 5.0 -name CLK -waveform { 1.0 3.0 } [get_ports CLK]
set_input_delay 1.0 -clock [get_clocks CLK] [get_ports DIN]

 For the set_input_delay or set_output_delay command, use the -clock option to define which clock is
synchronized. Be sure to specify the -clock option.
 When making verification using multiple on-chip clocks or off-chip clocks, specify the -add_delay option.
Input delays are affected by blunting of the input waveform and output delays are affected by the output
load capacity. Make settings according to these characteristics as needed.

● Exceptions
set_false_path
Description example)
set_false_path -from [get_clocks {<launch clock name>}] -through [get_pins {<data pin name>}] ¥
-to [get_clocks {< capture clock name>}]
 Indicate the launch clock and the capture clock with the –from option and -to option respectively. (This
item can be checked by R0067.)
 Specify the –from and -to options together. Do not specify the -through option alone. (This item can be
checked by R0068 and R0071.)
 Do not specify the net name using the -through option. (This item can be checked by R0121.)

set_multicycle_path
Description example)
Multicycle path of data line (with higher frequency on the capture clock)
set_multicycle_path –setup <number of cycles for setup> -end -from [get_clocks {<launch clock name>}]
-through [get_pins {<data pin name>}] -to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -end -from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] -to [get_clocks {<capture clock name>}]

Multicycle path of data line (with higher frequency on the launch clock)
set_multicycle_path –setup <number of cycles for setup> -start -from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] -to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -start -from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] -to [get_clocks {<capture clock name>}]

 Set multicycle path constraints for paths with a data flow control circuit.
 Set the -setup multicycle path and the -hold multicycle path in pair.
 Indicate the clock to be the reference of the multicycle path with the –end or -start option.
 Indicate the launch clock and the capture clock with the –from option and -to option respectively.
 Specify the data pin as a midpoint using the -through option.

set_max_delay|set_min_delay
Description example)
set_max_delay -from [get_ports {D0}] -to [get_pins {F0/DATA}] 1.0
set_min_delay -from [get_ports {D0}] -to [get_pins {F0/DATA}] 0.5

 Specify the start point (input port, bidirectional port, or register’s clock pin) of a path by -from option and
specify the end point (output port, bidirectional port, or register’s data pin) of a path by -to option.
 When the route of the path which has constraints is indicated, specify the route by using the -through
option.
 Page 17/257
 When the signal transition states at the start point, end point, and a point in the halfway route of a path
can be indicated, specify the signal transition states using the -rise_from, -fall_from, -rise_to, -fall_to, -
rise_through, -fall_through options respectively instead of the -from, -to, and -through options.

● Others
set_disable_timing
Description example)
set_disable_timing [get_pins <pin name>]

・ Specify the name of the pin on which you wish to disconnect the timing arc.
 Page 18/257

7. Recommended SDC Command Descriptions and Check Rules

7.1. For All SDC Commands

Rules are applicable to all SDC commands.

7.1.1. Common to all SDC commands

The following settings are applicable to basic commands (such as get_pins and get_ports used in SDC
commands) and SDC commands used for setting constraints for hierarchy pins.

◆ Recommended usage
The following description methods are recommended as settings for all commands.
 When specifying an object in an SDC command, indicate the type of object specified by get_* commands
(including get_pins, get_ports, get_nets, and get_clocks).
 To avoid ambiguity of constraints, do not specify middle hierarchy pin as objects.

◆ Recommended example of command description

To indicate the object type (D0 of port or F0/DATA of pin), get_ports is used.
set_max_delay -from [get_ports D0] -to [get_pins F0/DATA] 1.0
set_min_delay -from [get_ports D0] -to [get_pins F0/DATA] 0.5

Constraints are set for the cell pin instead of the middle hierarchy pin.
set_case_analysis 0 [get_pins BLOCK/buf/Y]

BLOCK

D Q
buf CK
D Q Y D Q
CK CK
clk
Constraints are set
for the cell pin

◆ Notice
 When you choose not to indicate the object type for some reasons, use the timing report command to see
to which object the tool handling SDC has applied constraints.
 When you choose to set constraints for a hierarchy pin for some reasons, use the timing report command
to see for which object the tool handling SDC has enabled constraints.

 Page 19/257
7.1.2. Check rules

R0001 Prohibition of set_case_analysis definition for the middle hierarchical pin

Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC HIER_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_case_analysis for a hierarchical pin because, in that case, the constraint point is
extinguished by hierarchical expansion. If the command is specified for a hierarchical output pin, the range in
which the value propagates may vary depending on the tool that is used. This rule displays the name of
hierarchical pin for which set_case_analsys is specified.
PrimeTime propagates the value only to output direction. However, ICC propagates the value to both output
and input 19irection.

◼ Sample circuit configuration and constraints

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

set_case_analysis 1 [get_pins BLOCK/OP1]

the middle hierarchical pin

the path ‘1’ propagates BLOCK

BLOCK
OP2 OP2
D Q the path ‘1’ propagates D Q
CK CK
D Q D Q D Q D Q
CK OP1 CK OP1
CK CK
clk clk
constraint point constraint point

Interpretation of PrimeTime Interpretation of ICC

GCA Message

HIER_001:
Hierarchical pin pin has constraints defined on it.

HIER_001 detects the timing exceptions (set_false_path, set_multicycle_path, set_min_delay,

set_max_delay) and set_disable_timing in addition to the set_disable_timing.
 Page 20/257
R0007 Prohibition of create_clock/create_generated_clock definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC CLK_0015
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify create_clock/create_generated_clock for a hierarchical pin because, in that case, the
constraint point is extinguished by hierarchical expansion. If create_clock/create_generated_clock is specified
for a hierarchical pin, PrimeTime handles the specified hierarchical pin as a clock set point as it is but ICC
replaces it with the preceding or following instance pin. In this way the behavior differs between PrimeTime
and ICC. Therefore, setting create_clock / create_generated_clock for hierarchical pins (including bi-directional
pins) is inhibited.

◼ Sample circuit configuration and constraints

① Specification for the middle hierarchical pin

create_clock -period 10 -waveform {0 5} -name CK [ get_pins mod1/m1 ]

the middle hierarchical pin

create_ create_
mod1 mod1
clock clock
setting setting
point point

m1 m1 This path is
recognized
as a clock.

Interpretation of PrimeTime Interpretation of ICC

GCA Message

CLK_0015 :
Clock clock is created on a hierarchical pin.
 Page 21/257
R0017 Prohibition of create_generated_clock definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC UDEF_GclockMasterPinOnHierPin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify the -source option of create_clock for a hierarchical pin because, in that case, the
constraint point is extinguished by hierarchical expansion. While PrimeTime handles the specified hierarchical
pin as a clock set point as it is, ICC replaces it with the preceding or following instance pin. In this way the
behavior differs between PrimeTime and ICC. Therefore, setting the -source option of create_clock for
hierarchical pins (including bi-directional pins) is inhibited.

◼ Sample circuit configuration and constraints

Specification for the middle hierarchical pin

create_clock -period 10 -waveform {0 5} -name CK1 [get_pins mod1/m1]

create_generated_clock -name CK_G1 -source [get_pins mod1/m1] -divide_by 2 [get_ports clk]

the middle hierarchical pin

create_gener mod1 create_gener mod1

ate_clock ’ s ate_clock ’ s
source source
setting point setting point

m1 m1

create_clock create_clock This path is

setting point setting point recognized as a
clock.

Interpretation of PrimeTime Interpretation of ICC

GCA Message

CLK_0015 :
Clock clock is created on a hierarchical pin.
 Page 22/257
R0024 Prohibition of set_clock_latency definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC UDEF_ClkLatOnHierPin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_clock_latency for a hierarchical pin because, in that case, the constraint point is
extinguished by hierarchical expansion. If the clock latency is specified, PrimeTime holds the hierarchical pin
and sets the clock latency, but ICC replaces it with the preceding or following instance pin when setting the
clock latency. Therefore, setting a hierarchical pin in this case is inhibited when ICC is to be used.

◼ Sample circuit configuration and constraints

Specification for the middle hierarchical pin

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

set_clock_latency 1.0 [get_pins mod1/m1]

the middle hierarchical pin

set_clock_lat mod1 set_clock_lat mod1

ency ency
setting point setting point
Clock
clk latency: clk
Clock
1ns
m1 m1 latency:
1ns
create_clock create_clock
Clock
setting point setting point
latency:
0ns

Interpretation of PrimeTime Interpretation of ICC

GCA Message

UDEF_ClkLatOnHierPin :
set_clock_latency is wrongly set on hierarchical module pin ('hier_pin'). Please set_clock_latency is set
clock with get_clocks.
 Page 23/257
R0033 Prohibition of set_clock_uncertainty definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC UDEF_ClkUncOnHierPin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_clock_uncertainty for a hierarchical pin because, in that case, the constraint point
is extinguished by hierarchical expansion. In this case, PrimeTime holds the hierarchical pin and sets the skew
but ICC replaces it with an instance pin when setting the skew. PrimeTime and ICC make different
interpretations in this case and therefore, it is inhibited to specify set_clock_uncertainty for any hierarchical pin.

◼ Sample circuit configuration and constraints

Specification for the middle hierarchical pin

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

set_clock_uncertainty 1.0 [get_pins mod1/m1]

the middle hierarchical pin

mod1 mod1
set_clock_un set_clock_un
certainty certainty
setting point setting point
clk Clock clk
skew: 1ns Clock
m1 m1 skew: 1ns
create_clock
create_clock Clock setting point
setting point skew: 0ns

Interpretation of PrimeTime Interpretation of ICC

GCA Message

UDEF_ClkUncOnHierPin :
set_clock_uncertainty is wrongly set on hierarchical module pin ('hier_pin'). Please
set_clock_uncertainty is set clock with get_clocks.
 Page 24/257
R0037 Prohibition of set_input/output_delay definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC EXD_0008
UDEF_EXD_0008_NoSeqPin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_input_delay/set_output_delay for a hierarchical pin because, in that case, the
constraint point is extinguished by hierarchical expansion. If the set_input_delay/set_output_delay command
is specified for a hierarchical pin, PrimeTime holds the hierarchical pin and sets the input delay but ICC
replaces it with an instance pin when setting the delay. For this reason, do not specify a hierarchical pin in the
object list.

◼ Sample circuit configuration and constraints

Specification for the middle hierarchical pin

set_input_delay 2 [get_pins mod1/m1]

the middle hierarchical pin input delay:

input delay:
2.0ns 2.0ns

mod1 mod1

D Q D Q
The
CK CK
instances
D Q that the input D Q The
delay is set instances
m1 CK m1 CK
that the input
D Q delay is set
D Q
set_input_delay set_input_delay
setting point CK CK
setting point

Interpretation of PrimeTime Interpretation of ICC

GCA Message

EXD_0008 :
The input delay at pin pin is forcing a start point that blocks paths through this pin.
The output delay at pin pin is forcing a end point that blocks paths through this pin.

Specified set_input/output_delay as midle hierarchical pin.

EXD_0008 also reports when pin objects in the design are specified.
This rule is a custom rule that filters out non-sequential cell pins from violations of EXD_0008.
Added in Rule Set V02.01.06.
GCA/PTC MESSAGE
UDEF_EXD_0008_NoSeqPin :
"set_’inoutput’_delay command is NOT set on the sequential cell pin ‘obj_name’

Among violations of EXD_0008, set_input_delay or set_output_delay is specified as a pin that is not a

sequential cell pin.
 Page 25/257

Limitations

・Duplicate reports for UDEF_EXD_0008_NoSeqPin and EXD_0008

After filtering with UDEF_EXD_0008_NoSeqPin, violations for the same pins with the same set_input_delay
and set_output_delay are still shown in EXD_0008.
UDEF_EXD_0008_NoSeqPin is related to the original start pin (eg, register clock pin) and endpoint (eg,
register data pin) and does not report if it is a sequential cell pin.
 Page 26/257
R0060 Prohibition of set_disable_timing definition for the bi-directional middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC HIER_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When set_disable_timing is specified to bi-directional middle hierarchical pin, the operation is different in
Prime Time and ICC. PrimeTime invalidated both input and output timing paths. However ICC invalidated
output timing path but does not input timing path. Therefore, this rule reports the middle hierarchical pin name
when set_disable_timing is specified to bi-directional middle hierarchical pin.

◼ Sample circuit configuration and constraints

① Specification for the middle hierachical pin.

bi-directional middle hierarchical pin
set_disable_timing [get_pins BLOCK1/INOUT]

BLOCK
disabled timing path
Interpretation
of PrimeTime QD IOP D Q
CK CK

（INOUT） QD
D Q
CK CK
disabled timing path

BLOCK
Interpretation
of ICC not disabled timing D
path
Q
QD IOP
CK CK

D Q （INOUT） QD
CK CK
disabled timing path

GCA Message

HIER_001 :
Hierarchical pin pin has constraints defined on it.
 Page 27/257
R0073 Prohibition of set_false_path definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC HIER_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify the -through option of set_false_path for a hierarchical pin because, in that case, the
constraint point is extinguished by hierarchical expansion. It must also be noted that ICC is likely to add a
logical port to the hierarchy for fanout net optimization, resulting in a path for which the constraints applied to
the original port become invalid. This rule detects the condition in which the -through option of set_false_path
is specified for a hierarchical pin.

◼ Sample circuit configuration and constraints

① Specification for the middle hierachical pin.

set_false_path -through [get_pins mod1/m1]

the middle hierarchical pin

mod1 mod1

exceptoin
D Q pass D Q exceptoin
m1 m1 pass
CK CK

Interpretation of PrimeTime Interpretation of layout tool

GCA Message

HIER_001 :
Hierarchical pin pin has constraints defined on it.
 Page 28/257
R0089 Prohibition of set_min/max_delay definition for the middle hierarchical pin
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
PTC HIER_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_min_delay/set_max_delay for a hierarchical pin because, in that case, the
constraint point is extinguished by hierarchical expansion. If the constraint by set_min_delay/set_max_delay
is specified for a hierarchical pin which is likely to be removed from the design during optimization, the expected
constraint may not be applied. Therefore, setting set_min_delay/set_max_delay for a hierarchical pin is
inhibited. Specifying any of -from, -to, and -through is inhibited.

• Specification for the middle hierarchical pin

• Pin specified logic gate cell

◼ Sample circuit configuration and constraints

① Specification for the middle hierarchical pin

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

set_min_delay 0.5 –to [get_pins mod1/m1]

the middle hierarchical pin

mod1
set_input_del
ay setting
point
clk

m1
create_clock
setting point

GCA Message

HIER_001 :
Hierarchical pin pin has constraints defined on it.
 Page 29/257
R0097 When an Object Is Specified, the Object Type Is Explicitly Specified
Severity RTL Layout I/F STA IP
n/a Error Error Warning
Category consistency ◼semantics unclear TDL check rule user's manual
PTC UIC-067
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When specifying an instance name, external pin name, pin name, net name, clock name, or the like, use the
get_xxx command to explicitly specify the type of the target object. For example, an external pin and the net
connected to the pin have the same name, so the constraint target becomes unclear if a type is not
specified.

◼ Sample circuit configuration and constraints

set_false_path -from uff_1_1

GCA Message

UIC-067：
Option '%s' contains implicit reference to objects, use '[get_* %s]' instead.

Confirmation method
UIC-067 outputs to the log as shown below.
but you cannot check the corresponding SDC command in the log.
Error: Option '' contains implicit references to objects, use '[get_* ]' instead. (UIC-067)

The violated constraint can be confirmed with UserMessageBrower ont the GUI.
In the list on the left side of the figure below, violated constraints are not displayed.
Please select one violation message. Then click on the blue text in "Reference" on the right window.
You can see the violated constraints.

Action (common)

Explicitly specify the target object.

set_false_path -from [get_cells uff_1_1]

Limitations (GCA/PTC)

UIC-067 and UIC-068 are used when reading SDCs. But these rules are also detected when rule checking
after reading SDCs. So ‘Renesas_sdc_start’ and ‘Renesas_sdc_end’ command is prepared to suppress
messages by their rules. Using these commands before and behind ‘read_sdc’ make suppress detection of
unnecessary message about UIC-067 and UIC-068. Please refer to the following sample to use them.

<install directory>/Renesas/GCA/RULES/<rule version>/sample/gca_run/script.tcl

 Page 30/257
R0123 Prohibition of set_disable_timing definition for the middle hierarchical cell
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category consistency ◼semantics unclear TDL check rule user’s manual
PTC HIER_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

It is inhibited to specify set_disable_timing for a hierarchical pin because, in that case, the constraint point is
extinguished by hierarchical expansion.
PrimeTime disables all paths through output pins of hierarchical cell. ICC (DC) does not disable any paths.
This causes discrepancy between PrimeTime and ICC (DC) timing results.

Hierarchical cell
U1

q1
Disabled timing paths in PrimeTime

q2

set_disable_timing [get_cells U1]

GCA Message

HIER_001:
Hierarchical pin 'U1/q1' has constraints defined on it.
Hierarchical pin 'U1/q2' has constraints defined on it.
 Page 31/257

7.2. Constants

7.2.1. set_case_analysis

The set_case_analysis command is used to set a constant value (1, 0) for a specific point.

◆ Recommended usage
The following description methods are recommended for setting the set_case_analysis command.
 When you are describing constraints for a chip, specify an input port of the chip.
 When you are describing constraints for a module, specify an input port of the module.

◆ Recommended example of command description

Setting a constant
set_case_analysis <0|1> [get_ports <input port name> ]

Example: set_case_analysis is specified for either input to a dual-input AND cell.

◆ Notice
 If two or more constants are set on the same timing path, a conflict may occur. Do not set two or more
constants. (This item can be checked by R0004, but rising and falling are not checked by the check rule.)
 When set_case_analysis is used, timing arc related to constant propagation is disabled and thus not
applicable to timing analysis.
 If a constant is set for a register input pin, timing analysis is not performed. The constant is not propagated
to the output pin.
 If a constant is set for an input pin in the halfway route of the circuit, the constant is not set for other
input pins of the same net. In the example below, 0 is not propagated to A of I2 by PrimeTime. When
setting a constant in the entire net, set it for Q of F1.

set_case_analysis 0 [ get_pins I1/B ]

F1 I1
A
Q B 0 is propagated
0
I2
A
B 0 is not propagated
 Page 32/257
◆ Supplement
The following description is possible with the set_case_analysis command though it is not recommended.
Example 1: Signal transition (rise/fall) setting
A constant (0 or 1) is usually set for the set_case_analysis command. However, signal transitions can also
be specified by rising/falling. F1/Q is an output from a register and has rising and falling transitions. Setting
rising for A of I1 disables a falling transition and enables only a rising transition.
 Page 33/257

7.2.2. Check rules

R0002 Prohibition of specification of constant for all data pins of multiplexer

Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
PTC UDEF_FixedMuxSetCaseAnalysis
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When constant is specified for all data pins of multiplexer by set_case_analysis, the operation is different
between Prime Time and ICC. ICC disables timing arc from selector pin to output. However, ICC does not
disable its timing arc. Therefore, this rule reports the instance name of multiplexer as an error when constant
is specified for all the data pins.

◼ Sample circuit configuration and constraints

1. Constant specified for all data inputs.

S1 S0 Y
set_case_analysis 1 [get_pins MX4/D0]
set_case_analysis 1 [get_pins MX4/D1] 0 0 (D0)
set_case_analysis 0 [get_pins MX4/D2] 0 1 (D1)
set_case_analysis 0 [get_pins MX4/D3] 1 0 (D2)
1 1 (D3)

truth table of MX4

data pins specified with constant MX4

1 D0
1 D1
Y
0 D2

0 D3
S1 PrimeTime does not disable this timing arc.
S0
ICC disable this timing arc.

GCA Message

UDEF_FixedMuxSetCaseAnalysis :
All of MUX data signals are fixed by set_case_analysis command (Instance: cell ).

Action

The logic or timing constraints should be modified if possible. But when it’s not impossible, please ignore a
timing calculation result of PrimeTime for paths with the MUXs or cut the timing arc from selector to output of
the MUXs with set_disable_timing command before running PrimeTime.

It is recommended to change the logic or timing constraints.

If neither can be changed:
・Check the validity of the timing path that contains the reported multiplexer.
Or
・Use the set_disable_timing command to disable the timing arc between the selector and multiplexer outputs.
 Page 34/257
This rule detects that a glitch may be output when the selector pin is switched if the same constant is
propagated to all the data pins of the multiplexer.

Therefore, if any of the following conditions is met, it can be judged as a false error.

Condition 1: The case where the selector pin of the multiplexer is used only for data signal selection.

If the timing arc from the selector pin to the output pin is used as part of the logic, and the role is just to pass
the constant of the input data pin to the subsequent stage, it can be a pseudo error.

Condition 2: If condition 1 is not met, a multiplexer that guarantees that no glitch will occur when the selector
pin is switched is used.

Generally, a multiplexer multi is composed of a combination circuit of AND and OR. If the selector pin is
switched and there is a deviation in signal propagation to AND or OR, glitches may occur. It can be a false
error if the corresponding multiplexer is guaranteed not to glitch.

For example, if there is a 3-input AND, and there is a signal propagation deviation between S0 and S1 as
shown on the right side, there is a concern that a glitch will occur in the output Y, affecting the logic of the
subsequent stage.

S0 S0

S1 S1

A A

Y Y

Condition 3: If this condition cannot be handled as a pseudo error in conditions 1 and 2, and there is no problem
with this multiplexer even if the above unintended glitch occurs, this rule can be set as a pseudo error.

◼ Confirmation method

<Violation>
All of MUX data signals are fixed by set_case_analysis command(Instance: BLK2/MUX01).

<Constraint>
set_case_analysis 1 [get_pins BLK2/MUX01/0]
set_case_analysis 1 [get_pins BLK2/MUX01/1]

<Debug method>
The constant of each data pin of the multiplexer can be confirmed by the following method. You can also check
the constant of the output pin of cell BLK2/MUX01 by using the get_attribute command. In the example below,
the constant “1” is propagated to all input data pins.
ptc_shell> get_attribute -quiet [get_pins cell /* -filter "direction==in && is_mux_select_pin==false"] case_value
11

When checking the constant of the output pin

ptc_shell> get_attribute -quiet [get_pins cell /* -filter "direction==out"] case_value
1

Or you can check the Violation Details on the GUI.

 Page 35/257

◼ Limitations
Only inspected if the cell type is a multiplexer (cell type: is_mux = true).
When configured with AND or OR circuit connections, this rule does not detect them. Even if all the inputs of
the multiplexer are constants, each is set to a different value, and when a transition occurs between the selector
and the output due to the transition of the select pin, a timing calculation is required, so there is a difference in
behavior between ICC and PrimeTime I do not. However, even if the transition of the value of the output pin
does not occur at the transition of the select pin, there is a possibility that a glitch may appear, but ICC does
not consider it. Originally, such a hazard is not verified in STA, but PrimeTime verifies that even if a glitch
appears within one cycle, it is considered as a result.

GCA/PTC rules do not detect if the output pin value is a constant.

 Page 36/257
R0003 Clock driven by a constant value or hanging
Severity RTL Layout I/F STA IP
n/a Info Info Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
PTC CLK_0006
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
Since FFs with a fixed clock are not subject to STA, care must be taken to ensure that the results after mounting
are as expected.
Also note that the signal is disconnected in the timing path with latches whose enable is fixed off. This rule
detects when the FF clock or latch enable is fixed at High or Low.
･ constant nets (both supply nets and nets due to set_case_analysis settings)
･ hanging nets
･ output pin or a non-toggling sequential cell (cell whose either data or clock pin is constant)

◼ Sample circuit configuration and constraints

2. Clock driven by a constant value

FF1
OR1
D Q
CLK B
DATA A CK
1

set_case_analysis 1 [ get_ports {DATA}]

create_clock [get_ports {CLK}] –name CLK –period 10 –waveform {0 5}

GCA Message

CLK_0006：
Clock clock source source has a logic constant or case value.

3. Enable driven by a constant value

0 LAT1
AND1
D Q
EN B
DATA A EN

set_case_analysis 0 [ get_ports {DATA}]

GCA Message

CLK_0006：
Clock clock source source has a logic constant or case value.
 Page 37/257

◼ Action
In order not to stop the propagation of the clock, it is necessary to prevent the constant or logic constant from
propagating to the clock pin.
Check if there is an error in the fixed setting or circuit connection.

◼ Confirmation method

<Debug method>
CLK_0006 reports the clock name and the source pin name of that clock. Use the report_case_details
command to determine the fixed source that propagates to that source pin. This constant includes not only
set_case_analysis, but also constants connected to Tri-Hi (pull-up)/Tri-Low (pull-down), power supply and
ground in Netlist.

gca_shell> report_case_details -to [get_pins FF1/Q]

****************************************

Properties Value Pin/Port

---------------------------------------------------------
user case 1 FF1/Q (library_cell_name)

Check whether the constants set in this report and the constants of Netlist are accompanied by product
specifications.
If a constant is propagated to the clock pin, the clock signal becomes invalid, and the STA that is affected by
the clock signal cannot be created, causing verification failure.
 Page 38/257
R0004 set_case_analysis Settings Are Not Made to Conflict with Each Other.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ◼consistency ◼semantics ◼unclear TDL check rule user's
manual
PTC CAS_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

A conflict between case settings refers to a condition in which the value that is set for a path to which a constant
(clamp cell or case setting) is propagated has the state opposite to that of the propagated value. Such a value
makes the intention of the constraint unclear and leads to a verification error. Therefore, any conflict between
case settings must be inhibited.

◼ Sample circuit configuration and constraints

Prohibited. Prohibited.
H

0 setting 1 setting High 0 setting

Clamp

GCA Message

CAS_0003 :
Pin/Port 'buf_1_2/Z' propagated value conflicts with a user case analysis value

◼ Action
Check if the reported pin / port constant is correct and correct if necessary.

◼ Confirmation method
The confict point is reported on the back side when different constants are set on the same timing path.
Therefore, to check the constant in the previous stage for the reported pin / port, check the content of the
conflict with report_case_details -to <confiict point>.
Here is an example.

<violation>
Pin/Port 'buf_1_2/Z' propagated value conflicts with a user case analysis value.

<Constraint>
set_case_analysis 1 buf_1_1/Z
set_case_analysis 0 buf_1_2/Z
<Debug method>
gca_shell> report_case_details -to buf_1_2/Z
****************************************

Properties Value Pin/Port

------------------------------------------------------------------------------
user case 0 buf_1_2/Z (library cell name)

Case fanin report:

Verbose Source Trace for pin/port CGC/CPN:
Path number: 1
 Page 39/257
Path Ref # Value Properties Pin/Port
------------------------------------------------------------------------------
0 user case buf_1_2/Z (library_cell_name)
1 user case buf_1_1/Z (library_cell_name)

If an unnecessary constant is set, delete set_case_analysis specified on the path that though “<conflict point>”.
You can also check the Violation Details on the GUI. You can execute the report_case_details command by
clicking execute in this vibration details.

Click "execute" to display the "ViolationSchemeatic" tab and display the constants on the schematic.

If you don't need a schematic, click "echo command" and add "-text_only" to the displayed command.
report_case_details -to BLK1/FF01/D
↓
ptc_shell> report_case_details -to BLK1/FF01/D -text_only
If you want to check the constant in the latter part, check with “report_case_details -from <confiict point>”.
 Page 40/257
S0001 The value specified as a Constant logic value must match the actual behavior
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category ◼consistency semantics unclear TDL check rule user's
manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert SDC_CASE_ANALYSIS
(Dynamic Simulation）

◼ Description
Verify that the constant of the pin with the Case constraint specified is the same on the logic simulation /
emulation. If there is a discrepancy on the functional simulation / emulation, check the violation report to see
if it is as designed. Note that the SVA Flow utility is used for this verification. Please refer to the reference for
usage.

Case constraint specified pin and logic simulation/emulation constant is different

## test.sdc. in this case violation.

set_case_anaysis 1 [get_pins MUX/S]

The above set_case_anaysis is intended to give a constant of 1 to the pin MUX/S. Is it actually the same
constant at the specified pin?
Or, confirm on logic simulation/emulation that there is no signal change.
SIM/HWE result

SIM(VCS)

[SDC_CASE_ANALYSIS] start check set_case_analysis.

[SDC_CASE_ANALYSIS] Number of set_case_analysis = 1
[SDC_CASE_ANALYSIS] [CASE_ID_0] checking case value of SEL is 1 COMMAND:set_case_analys 1
[get_ports {SEL}] FILE:netlist.sdc LINE:3
[SDC_CASE_ANALYSIS] [CASE_ID_0] [FAIL] SEL is not value 1 at time 950

HWE(Palladium)

Same as VCS.

◼ Action
The expected value of the Case constraint is that the constant of the specified pin does not change on the
logic simulation/emulation. In the case of the above example, there is a period that changes to a constant
different from the Case constraint, so it can be seen that the STA differs from the verification environment on
the logic simulation / emulation. Therefore, check whether the selection of the reset signal is appropriate in the
functional simulation / emulation environment, and whether the file to be input to the SIM / HWE environment
is appropriate, and correct accordingly. In the same way, check whether there is an error in the constant of the
Case constraint and correct it accordingly.
 Page 41/257

7.3. Clock

7.3.1. create_clock

The create_clock command is used to create a clock for a specific point and set its waveform.

◆ Recommended usage
 Specify clock input ports or output pins of clock generating cells as definition points.
 Specify the following options for the create_clock command.
 Use the -name option to specify the clock name.
 Use the -period option to specify the clock period.
 Use the -waveform option to specify the clock waveform.
If the -waveform option is not specified, a waveform is automatically set with rising edge = 0.0 and
duty = 50%.
We recommend that you specify the -waveform option.
 When creating a virtual clock, set the create_clock command without specifying any definition point.

◆ Recommended example of command description

 Specifying clock waveform
The -waveform option is used to specify a clock waveform.

The following shows an example to create CLK1 (period: 10, rising edge: 2, falling edge: 7) for the external
port "CLOCK_PORT1".

create_clock -period 10 -waveform {2 7} -name CLK1 [get_ports CLOCK_PORT1]

When creating CLK3 with a period of 10 for the external port "CLOCK_PORT3", if the -waveform option is
omitted, a clock with a rising edge of 0.0 and a falling edge of 5.0 (1/2 of the period specified by the -period
option) is created.

create_clock -period 10 -name CLK3 [get_ports CLOCK_PORT3]

 Page 42/257
 Inverted clock
The following shows an example to create CLK2 (period: 10, rising edge: 7, falling edge: 11) for the external
port "CLOCK_PORT2".

create_clock -period 10 -waveform {7 11} -name CLK2 [get_ports CLOCK_PORT2]

 Creating a clock for an instance pin

A clock is created for the specified point. The clock propagates from the specified instance pin and a clock
delay to the sequential cells (such as FF, latch, and RAM) is also calculated from the specified instance pin.
When an instance pin is specified as shown below, for example, the clock is supplied to both F1 and F2.

Unlike the above case, when an instance pin is specified as shown below, the clock is supplied to F2 but is not
supplied to F1.
 Page 43/257
 Creating multiple clocks for the same point

To create multiple clocks for the same point, use the -add option as shown below. When using the -add option,
the -name option must be specified together. Furthermore, when multiple clocks are created for the same point,
path timing is analyzed for all possible combinations of clock transmission/reception relationship (CLK1 →
CLK1, CLK1 → CLK2, CLK2 → CLK1, and CLK2 → CLK2).

 Virtual clock

If the create_clock command is used without setting any definition point (source_objects), a virtual clock is
created. The virtual clock can be used as the reference clock of the set_input_delay command and the
set_output_delay command.

create_clock -period 10 -waveform {0 5} -name VIRTUAL_CLK

◆ Notice
 Do not set the create_clock command on the same clock network. (R0014)
 Do not use the create_clock command to define any clock for the selector port of the MUX (selector cell).
(R0099)

◆ Supplement

None
 Page 44/257
7.3.2. create_generated_clock

The create_generated_clock command is used to create a new clock (generated clock) based on the existing
clock (master clock). Using the create_generated_clock command ensures synchronization between the
master clock and a generated clock. When the master clock changes, the generated clock is also automatically
changed.

When the master clock is a propagation clock, the source latency of the master clock and the propagation
delay from the master clock to the generated clock are automatically considered.

When the master clock is an ideal clock, set_clock_latency, set_clock_transition, and set_clock_uncertainty
that were set for the master clock do not affect the generated clock. Set these commands individually.

◆ Recommended usage
 Use the -name option to specify the generated clock name.
 Use the -source option to specify a master clock propagation point.
 Use the -master_clock option to specify the name of the master clock (reference clock).
 Use any the generated clock waveform, to specify of the following options.
➢ To generate a divided clock, use the -divide_by option.
➢ To generate a multiplied clock, use the -multiply_by option.
➢ To generate a generated clock with the edge positions of the master clock specified, use the -edges
option.
➢ To generate a generated clock (division ratio = 1), use the -combinational option.
 Use the -invert option to invert the waveform of the generated clock.
 To create two or more generated clocks for the same definition point, use the -add option.
Also use the -name option to specify the generated clock name.

◆ Recommended example of command description

 Using -source to specify a point to be the reference of the generated clock

When creating a generated clock, use the -source option to specify a master clock propagation point. The
waveform of the generated clock is generated based on the clock waveform at the specified point. The latency
of the generated clock is calculated from the point at which the master clock is set. In the figure below, a
generated clock (CLK1 divided by 2) is specified for Q of DV1. Since P1 is specified by the -source option, the
generated clock waveform is formed based on the non-inverted waveform of clock CLK1 at P1.
 Page 45/257

In the figure below, a generated clock (CLK1 divided by 2) is also specified for Q of DV1, but I1/YB is specified
by the -source option. In this case, the generated clock waveform is formed based on the inverted waveform
of clock CLK1 at I1/YB.

 Creating a divided clock

To specify a simple divided clock, use the -divide_by option. In the figure below, the clock DV_CLK (CLK1
waveform at port P1 divided by 2) is created for Q of DV1.

 Creating a multiplied clock

To specify a simple multiplied clock, use the -multiply_by option. In the figure below, the clock DV_CLK (CLK1
waveform at port P1 multiplied by 2) is created for Q of MU1.

create_clock -period 20 -waveform {0 10} -name CLK1 [get_ports P1]

create_generated_clock -multiply_by 2 -name MU_CLK -source [get_ports P1] [get_pins MU1/Q]
 Page 46/257

When using the -multiply_by option to specify a multiplied clock, the -duty_cycle option can be used to
specify the percentage of the clock period that the clock is high. In the example below, the high-level pulse
width is 8 because a value of 80 is specified for -duty_cycle of the multiplied clock (period: 10).

create_clock -period 20 -waveform {0 10} -name CLK1 [get_ports P1]

create_generated_clock -multiply_by 2 -duty_cycle 80 -name MU_CLK -source [get_ports P1] get_pins MU1/Q]

 Specifying a generated clock with the edge positions of the master clock specified

The -edges option can be used to create a complex generated clock with the edge positions of the master
clock specified. In the figure below, edge positions (1), (3), and (5) on the clock CLK1 waveform at port P1 are
specified to create a generated clock DV_CLK (CLK1 divided by 2) for Q of DV1.

create_clock -period 20 -waveform {0 10} -name CLK1 [get_ports P1]

create_generated_clock -edges {1 3 5} -name DV_CLK -source [get_ports P1] [get_pins DV/Q]
 Page 47/257
As shown below, using the -edges and -edge_shift options together makes it possible to specify the shift time
to be added to edges. The number of -edge_shift to be specified must be the same as the number of -edges.
The shift time is not regarded as clock latency.

create_clock -period 20 -waveform {0 10} -name CLK1 [get_ports P1]

create_generated_clock -edges {1 3 5} -edge_shift {2 3 4} -name DV_CLK -source [get_ports P1] [get_pins DV/Q]

 Creating a generated clock (division factor: 1)

As shown below, specifying 1 for the -divide_by option makes it possible to create the generated clock with
the same waveform as the master clock waveform at the point specified by the source_objects option. The
generated clock latency is calculated from the point of the master clock. Creating a new generated clock that
is the same as the master clock with a different clock name is useful for setting timing exceptions (e.g. by the
set_false_path command) for the master clock and generated clock separately.
 Page 48/257
 Inverting a generated clock

As shown below, using the -invert option inverts the generated clock waveform of the divided clock (-divide_by)
or multiplied clock (-multiply_by). This does not mean generation of a divided clock waveform or multiplied
clock waveform based on the waveform inverted from the master clock at the point specified by the
source_objects option.

 Setting multiple generated clocks for the same point

To create multiple generated clocks for the same point, use the -add option. When using this option, the -name
option must be specified together.
In the figure below, since multiple clocks have reached the generated clock definition point, the master clock
to be referenced must be specified by the -master_clock option.

◆ Notice
 When using the create_generated_clock command to create a generated clock, do not make an option
setting that generates a waveform different from that of the circuit configuration. (This item can be checked
by R0018, R0112, and R0019.)
 Make settings to generate a single delay calculation path from the master clock propagation point
specified by the -source option to the generated clock definition point. (This item can be checked by
R0023.)

◆ Supplement
None
 Page 49/257
7.3.3. set_propagated_clock

The set_propagated_clock command is used to set propagation of delay to the clock network.
If set_propagated_clock is not set for any clock, this will be an ideal clock independent of the delay of both
cells and nets through the clock networks.

◆ Recommended usage
The following description methods are recommended for setting the set_propagated_clock command.
 To propagate the delay to the clock network, set the set_propagated_clock command for all clocks.
 The set_propagated_clock command need not be set for an ideal clock (to propagate no delay to the
clock network).

◆ Recommended example of command description

set_propagated_clock [all_clocks]

◆ Notice
The set_propagated_clock command makes it possible to set a propagation clock by specifying a clock, port,
or pin. Since an ideal clock and a propagation clock do not exist together, make the propagation clock setting
for all clocks as described in “Recommended example of command description”.
 Page 50/257
◆ Supplement

The following provides examples for setting the set_propagated_clock command for a clock, port, and pin.

Since an ideal clock and a propagation clock do not exist together, make the following propagation clock setting.

set_propagated_clock [all_clocks]

 Setting for a clock

The following figure shows an example where the set_propagated_clock command is set for a clock. A delay
propagates to the clock pins of all the sequential cells (including FF, latch, and RAM) within the transition fan-
out of the clock.

 Setting for a port

The following figure shows an example where the set_propagated_clock command is set for a port on which
a clock is created. A delay propagates to the clock pins of all the sequential cells (including FF, latch, and RAM)
within the transition fan-out of the port.

 Setting for a cell

The following figure shows an example where the set_propagated_clock command is set for an instance pin
on which a clock is created. A delay propagates to the clock pins of all the sequential cells (including FF, latch,
and RAM) within the transition fan-out of the instance pin.
 Page 51/257
7.3.4. set_clock_uncertainty

The set_clock_uncertainty command is used to set skew in the clock network.

◆ Recommended usage
 Setting skew between clocks is recommended.
 Use the -from and -to options to specify the clocks for which you want to set skew.
 To specify either rising or falling of the clock or set different skew at rising and falling, use the -rise and -
fall options.
 To change the skew at the setup timing and hold timing, use the -setup and -hold options.

◆ Recommended example of command description

 Setting skew between clocks

When setting skew between clocks, use the -from and -to options as shown below. In the path from CLK1 to
CLK2, a value of 1.0 is set as the skew between clocks. If skew is also required for the path from CLK2 to
CLK1, “-from [get_clocks CLK2] -to [get_clocks CLK1]” must be set.

Skew = 1.0

set_clock_uncertainty 1.0 -from [ get_clocks CLK1 ] -to [ get_clocks CLK2 ]

 Setting skew for rising and falling edges

When setting skew values for rising and falling edges, use the -rise and -fall options as shown below. This
setting is applied to the skew at rising and falling edges of the capture clock. If neither the -rise nor -fall option
is specified, the same skew value is set for both rising and falling edges. When both the -rise and -fall options
are specified, respective skew values are set for rising and falling edges. If only the -rise option is specified
and the -fall option is not specified, the default value 0.0 is set for falling. Similarly, if only the -fall option is
specified, the default value 0.0 is set for rising.

Skew = 1.0 Skew = 0.5

 Page 52/257
set_clock_uncertainty 1.0 -from [ get_clocks CLK1 ] -to [ get_clocks CLK2 ] -rise
set_clock_uncertainty 0.5 -from [ get_clocks CLK1 ] -to [ get_clocks CLK2 ] -fall

 Setting skew in each setup analysis and hold analysis

When setting a skew value in each setup analysis and hold analysis, use the -setup and -hold options. In the
example below, the -setup value is set as the skew of the setup analysis and no skew value is set in the hold
analysis.

Skew = 1.0

set_clock_uncertainty 1.0 -setup [ get_clocks CLK2 ]

In the example below, the -hold value is set as the skew of the hold analysis and no skew value is set in the
setup analysis.

Skew = 1.0

set_clock_uncertainty 1.0 -hold [ get_clocks CLK2 ]

If neither -setup nor -hold option is specified, skew is set in both setup analysis and hold analysis.

◆ Notice
 When using the -setup and -hold options, set constraints for both -setup and -hold.
(This item can be checked by R0035)
 If multiple clock input ports exist, use the set_clock_uncertainty command by specifying the clock name
to be defined for the designated clock input port. Avoid using the set_clock_uncertainty command with
the clock input port specified. (R0120)
 Page 53/257
◆ Supplement

 Specifying objects to which the set_clock_uncertainty command is applied

The set_clock_uncertainty command makes it possible to set the clock skew by specifying a clock, port, or pin.
The following provides examples for setting the clock skew for a clock, port, and pin.

 The set_clock_uncertainty command for a clock

The following figure shows an example where the set_clock_uncertainty command is set for the clock (CLK2).
The skew is set for the clock pins of all the sequential cells (including FF, latch, and RAM) within the transition
fan-out of the clock.

Check the Uncertainty = 1.0

Setup

 The set_clock_uncertainty command for a port

The following figure shows an example where the set_clock_uncertainty command is set for a port on which a
clock is created. The skew is set for the clock pins of all the sequential cells (including FF, latch, and RAM)
within the transition fan-out of the port.

Check the Uncertainty = 1.0

Setup
 Page 54/257
 The set_clock_uncertainty command for an instance pin

The following figure shows an example where the set_clock_uncertainty command is set for the instance pin
on which a clock is created. The skew is set for the clock pins of all the sequential cells (including FF, latch,
and RAM) within the transition fan-out of the instance pin.

Check the Uncertainty = 1.0

Setup
 Page 55/257
7.3.5. set_clock_latency

The set_clock_latency command is used to set clock latency. Two types of clock latency can be set with this
command.
One is clock source latency, that is, a delay set to a clock definition point.
The other is clock network latency, that is, the time required for propagation from a clock definition point to the
clock pins of sequential cells (including FF, latch, and RAM).

◆ Recommended usage
 Options to be used vary with the clock latency type to be set.
 When setting clock source latency:
 Use the -source option.
 Specify a clock or clock definition point as objects.
 When setting clock network latency:
 Do not use the -source option.
 Items other than a clock and clock definition point can be specified as objects.

◆ Recommended example of command description

 When setting clock source latency

In the example below, a clock source latency value of 1.0 is set between clock CLK and the clock definition
point (port CLK).

create_clock -period 10 -waveform {0 5} -name CLK [get_ports CLK]

set_clock_latency 1.0 [get_clocks CLK] -source

 When setting clock network latency

In the example below, the clock from the clock definition point (clock CLK) to the clock pin of the sequential
cell (such as FF, latch, and RAM) is treated as an ideal clock, and a clock network latency value of 1.0 is set.

◆ Supplement
The set_clock_latency command allows the following settings. Each setting is described below.
 Clock latency for rising and falling edges
 Clock latency with minimum and maximum delays
 Clock source latency -early and -late
 Page 56/257
 Clock latency for rising and falling edges

When setting clock latency values for rising and falling edges, use the -rise and -fall options as shown below.
If neither the -rise nor -fall option is specified, the same clock latency value is set for rising and falling edges.
When both the -rise and -fall options are specified, respective clock latency values are set for rising and
falling edges. If only the -rise option is specified and the -fall option is not specified, the default value 0.0 is
set for falling. Similarly, if only the -fall option is specified, the default value 0.0 is set for rising.

When CLK waveform

when source latency
is not set

When CLK
source waveform when
source latency is set
latency

set_clock_latency -source -rise 1.0 [ get_clocks CLK ]

set_clock_latency -source -fall 0.5 [ get_clocks CLK ]

 Clock latency with minimum and maximum delays

When setting clock latency values with the minimum and maximum delays, use the -min and -max options.
The values to be set for these options vary with -analysis_type (single, bc_wc, or on_chip_variation) of
set_operating_conditions. When -analysis_type is single, analysis is made with single operating conditions.
When -analysis_type is bc_wc, the setup analysis is made for all paths with the maximum delay and the hold
analysis is made for all paths with the minimum delay. When -analysis_type is on_chip_variation, the setup
analysis is made with the maximum delay for the data path or with the minimum delay for the clock path, and
the hold analysis is made with the minimum delay for the data path or with the maximum delay for the clock
path.

 Clock latency with minimum delay

In the example below (where -analysis_type is on_chip_variation and -min is specified), the -min value is set
for the capture clock (F2/CLK) in the setup analysis and for the launch clock (F1/CLK) in the hold analysis.

<Setup analysis>

When F2/CLK
waveform when
source latency is
not set

When F2/CLK
waveform when
source latency is set

Clock
source
latency

<Hold analysis>

When F1/CLK
waveform when
source latency is
not set

When F1/CLK
waveform when
source latency is set

 Clock latency with maximum delay

In the example below (where -analysis_type is on_chip_variation and -max is specified), the -max value is set
for the launch clock in the setup analysis and for the capture clock in the hold analysis.
 Page 57/257
<Setup analysis>

When F1/CLK
waveform when
source latency is
not set

When F1/CLK
waveform when
source latency is set

Clock
source
latency

<Hold analysis>

When F2/CLK
waveform when
source latency is
not set

When F2/CLK
waveform when
source latency is set

 Clock source latency -early and -late

When setting the clock source latency with the clock source specified, early clock source latency can be set
by specifying the -early option or late clock source latency can be set by specifying the -late option. In the
example below, in the setup analysis, the -late value is set for the launch clock and the -early value is set for
the capture clock. In the hold analysis, the -early value is set for the launch clock and the -late value is set for
the capture clock.

When CLK
waveform when
source latency is
not set

Clock
source
latency

set_clock_latency -source -early 1.0 [ get_clocks CLK ]

set_clock_latency -source -late 2.0 [ get_clocks CLK ]

 Specifying objects to which the set_clock_latency command is applied

The set_clock_latency command can be used to set the clock latency for a clock, port, or pin. The following
provides examples for setting the clock source latency for a clock, port, and pin.

 Setting the clock source latency for a clock

The following figure shows an example where the set_clock_latency command (with -source specified) is set
for a clock. With this setting, a clock source latency value of 1.0 is set for the clock definition point (clock CLK).
 Page 58/257
When CLK
waveform when
source latency is
not set

Clock source When CLK

waveform when
latency source latency is set

 Setting the clock source latency for a port

The following figure shows an example where the set_clock_latency command (with -source specified) is set
for a port. With this setting, a clock source latency value of 1. 0 is set for the clock definition point (port CLK).

When CLK
waveform when
source latency is
not set

Clock source When CLK

latency waveform when
source latency is set

 Setting the clock source latency for a pin

The following figure shows an example where the set_clock_latency command (with -source specified) is set
for a pin. With this setting, a clock source latency value of 1.0 is set for the clock definition point (instance pin
I2/Y).

When I2/Y waveform

when source latency is
not set

When I2/Y waveform

when source latency is
set
 Page 59/257
7.3.6. set_clock_sense / set_sense

The set_clock_sense and set_sense commands are used to stop propagation of a clock from specific pins.

◆ Recommended usage
 Use the set_clock_sense or set_sense command to specify a pin on which you wish to stop clock
propagation.
 If two or more clocks have reached the pin and you wish to stop one of the clocks, use the -clocks option
to specify the name of the clock.
 Be sure to specify the -stop_propagation option.
 When the set_sense command is used:
 Specify the -type clock option.

◆ Recommended example of command description

create_clock [get_ports CLK1]

create_clock [get_ports CLK2]
set_clock_sense -clocks [get_clocks CLK1] -stop_propagation [get_pins MUX/Z] ;# set_clock_sense command
set_sense -type clock -clocks [get_clocks CLK1] -stop_propagation [get_pins MUX/Z] ;# set_sense command

In this example, propagation of CLK1 stops at the Z pin of MUX. Therefore, CLK1 does not propagate to the
flip-flop F1 (only CLK2 propagates to F1).

◆ Note
The set_clock_sense command is available in version 2.0 and earlier versions of SDC.
The set_sense command is available in version 2.1 and later versions of SDC. Use an appropriate SDC
version.

◆ Supplement
The set_clock_sense and set_sense commands can also be used to control the polarity of the clock to be
propagated. The following provides an example to control the polarity of clock.

 Setting the clock polarity to positive

To set the clock polarity to positive, use the -positive option.

set_clock_sense -positive -clocks [get_clocks CLK1] [get_pins XOR/Z]

set_sense -type clock -positive -clocks [get_clocks CLK1] [get_pins XOR/Z]
In this example, the polarity of CLK1 at the Z pin of XOR is set to positive.

 Setting the clock polarity to negative

To set the clock polarity to negative, use the -negative option.

set_clock_sense -negative MUX/Z

set_sense -type clock -negative MUX/Z
In this example, the polarity of all clocks that propagate from the Z pin of MUX is set to negative.
 Page 60/257
7.3.7. set_clock_groups

The set_clock_groups command is used to set the asynchronous transfer relationship between clocks.

◆ Recommended usage
 Using the -asynchronous option is recommended.
 Use the -group option to specify clock(s) for which you want to set asynchronous transfer relationship.
 If you want to set the transfer relationship between two or more clocks to asynchronous, specify the -
group option twice or more times.
 If you want to set the transfer relationship between two or more specific clocks and other clocks to
asynchronous, specify two or more clocks for the argument of the -group option.

◆ Recommended example of command description

Setting the asynchronous transfer relationship with the set_clock_groups command affects the crosstalk
analysis.

It can be declared that two clocks are in asynchronous relationship. In this case, the timing path (lanched by
one clock and captured by the other clock) is not checked as in the case of declaration of a false path between
two clocks.

In the crosstalk analysis, infinite timing windows are assumed between two clocks, which results in pessimistic
crosstalk.

 Setting the transfer relationship between two clocks to asynchronous

The following set_clock_groups command set the transfer relationship between CLK_T2 and CLK_T6 to
asynchronous.

create_clock -period 2 -name CLK_T2 [get_ports CLK1]

create_clock -period 4 -name CLK_T4 [get_ports CLK2]
create_clock -period 6 -name CLK_T6 [get_pins OSC/OUT]
set_clock_groups -asynchronous -group {CLK_T2} -group {CLK_T6}

In this example, the clock domain of CLK_T2 and CLK_T4 and the clock domain of CLK_T4 and CLK_T6 are
synchronous.
 Page 61/257
 Setting a single clock and all other clocks to asynchronous

Set asynchronous transfer relationship between CLK_T6 and other clocks.

create_clock -period 2 -name CLK_T2 [get_ports CLK1]

create_clock -period 4 -name CLK_T4 [get_ports CLK2]
create_clock -period 6 -name CLK_T6 [get_pins OSC/OUT]
set_clock_groups -asynchronous -group {CLK_T6}

In this example, the clock domain of CLK_T2 and the clock domain of CLK_T4 are synchronous.

 Specifying mutual exclusion for multiple groups

When two or more groups are specified, each group and other groups become exclusive.

Description example to specify mutual exclusion among CK1 and CK2, CK3 and CK4, and CK5
set_clock_groups -asynchronous ¥
-group {CK1 CK2} ¥
-group {CK3 CK4} ¥
-group {CK5}

◆ Note
 Note that set_clock_groups -group {CK1} -group {CK2} and set_clock_groups -group {CK1 CK2} lead to
different asynchronous transfer relationships.
➢ The set_clock_groups -group {CK1} -group {CK2} command sets asynchronous transfer relationship
between CK1 and CK2.
➢ The set_clock_groups -group {CK1 CK2} command sets asynchronous transfer relationship between
CK1 or CK2 and other clocks.

◆ Supplement

 Exclusive clocks

The set_clock_groups command can be used with the -logically_exclusive or -physically_exclusive option for
clocks that are to be exclusively used due to circuit configuration.
The -logically_exclusive option is used in a configuration to select multiple input clocks with a selector.
The -physically_exclusive option is used when clocks set for the same pin are not input simultaneously.

Using the -physically_exclusive option affects the crosstalk analysis. It is assumed that there is no interaction
of crosstalk between two clocks in the crosstalk analysis.

 Specifying two clocks exclusively

Description example to specify mutual exclusion between CLK1 and CLK2

set_clock_groups -logically_exclusive -group {CLK1} -group {CLK2}

CLK1 and CLK2 are synchronous with the other clocks that are not specified as a clock group. In the example
above, CLK1 and CLK3 are synchronous and CLK2 and CLK3 are also synchronous.
 Page 62/257
 Specifying multiple clocks for a clock group

Since CLK1 or CLK2 is selected by MUX1 in this circuit configuration, they must be exclusive. Furthermore,
since a divided clock is supplied to FF3, specify synchronous relationship between CLK1 and CLK1_DIV2 and
between CLK2 and CLK2_DIV2.

create_clock -name CLK1 [get ports CLK1] -period 2

create_clock -name CLK2 [get ports CLK2] -period 5
create_generated_clock -name CLK1_DIV2 -source [get_clocs CLK1] ¥
-master_clock [get_ports CLK1] -divide_by 2 [get_pins DIV2/Q]
create_generated_clock -name CLK1_DIV2 -source [get_clocs CLK2] ¥
-master_clock [get_ports CLK2] -divide_by 2 [get_pins DIV2/Q]
set_clock_groups -physically_exclusive -group {CLK1 CLK1_DIV2} ¥
-group {CLK2 CLK2_DIV2}

 Specifying a name for a clock group

A desired name can be assigned to the declaration of clock group, making it possible to easily delete specific
declarations later. However, the deletion command is not SDC.

set_clock_groups -logically_exclusive -name EX1 -group {CK1 CK2} -group {CK3 CK4}
 Page 63/257

7.3.8. Check rules

R0005 Constrained clock not used as a clock

Severity RTL Layout I/F STA IP
n/a Warning Warning Error/Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA CLK_0021 (IP:Error)
CLK_0026
SpyGlass Clk_Gen02

◼ Description

Timing calculation will get inaccurate if a clock definition is placed in a location where it is not to be used as a
clock (in the case of an ideal clock). Any unused clock definition may result in the increase in the execution
time of the layout tool. No clock should be defined for any signal that is not to be used as a clock. This rule
detects the condition in which create_clock or create_genearated_clock propagates to a pin other than the
clock pin and for unused clocks (that do not propagate to the clock pin of FFs or not referenced by
create_generated_clock/set_input_delay/set_output_delay).

◼ Sample circuit configuration and constraints

1. Clock propagating to the Data pin of an FF

IV1
FF1 FF2
D Q D Q
IV2
CLK CK CK

create_generate_clock
create_clock

create_clock -name DCLK -period 10 -waveform { 0 5 } [get_ports {CLK}]

create_generated_clock -source [get_ports CLK] [get_pins FF21/Q]

2. The clock definition is specified excluding this clock signals

No timing verification create_clock

FF
DATA D1 Q
CK
GATE1
CLK
AND1
create_clock -name DCLK -period 10 -waveform { 0 5 } [get_ports {FF/DATA}]

GCA Message

CLK_0026：
Clock clock is used as data. One or more sources of the clock fans out to a register data pin or to a
constrained primary output or inout port.

GCA Message

CLK_0021：
Clock clock is not used in this scenario.
*GCA reports that clocks do not propagate to registers with analyze_unclocked_pins command
 Page 64/257
ex.）
analyze_unclocked_pins -include {register_disabled unclocked case_disabled}

4. The clock definition is cut along the way and the clock does not propagate to the clock pin

No clock propagates to the clock pin of the FF and thus, the clock resultantly propagates to the data pin of
AND1 and this is detected.
FF
set_case_analysis 0 DATA D1 Q
CK
GATE1
CLK
AND1
create_clock
create_clock -name CLK1 -period 18 -waveform { 0 9 } [get_ports {CLK}]
set_case_analysis 0 [get_ports {GATE1}]

GCA Message

CLK_0021：
Clock ‘clock’ is not used in this scenario.
*GCA reports that clocks do not propagate to registers with analyze_unclocked_pins command
ex.）
analyze_unclocked_pins -include {register_disabled unclocked case_disabled}

Action

Action against circuit configuration and constraint example 1

In the case of generated clocks, the clock line should be separated from the data line and the generated clock
should be set at output pin of the buffer for clock setting. Note that this case causes rule 7.02.07 which is “A
Clock is set to the point at which the clock signal is generated”

IV1
FF1 FF1
D Q D Q
IV2
CLK CK CK

create_generate_clock
create_clock

create_clock [get_ports CLK] –period 100 –waveform {0 50}

create_generated_clock –source [get_ports CLK] [get_pins IV2/Y]

Confirmation method

●CASE: CLK_0026

<Debug method>
You can check the location of the clock definition by clicking the “Schematic” button in the Violation detail
Window of the GUI.
Check that the relevant clock is stopped according to the design specifications.
 Page 65/257
By pressing the ”Schematic” button, the clock definition location can be confirmed on the schematic.
In this case, you can see that the clock is defined on the output pin of the register.

You can check the timing constraints of the clock with “report_clocks”.
ptc_shell> report_clocks POSTCK

Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
POSTCK 14.50 {0 7.248} p, G {top/top_nonfb/cpgma/I_postcksel/I_cksel/out_reg_reg/Q}

Generated Master Generated Master Waveform

Clock Source Source Clock Modification
--------------------------------------------------------------------------------
POSTCK top/top_nonfb/cpgma/I_pll1/I_PLL/CLKOUT
top/top_nonfb/cpgma/I_postcksel/I_cksel/out_reg_reg/Q
CPGMAPLL1 div(24)

In addition, when there is a Black Box, there is no timing arc, so the propagation of data signals and clocks
stops there. Therefore, check whether LNK-805 is reported in the GCA / PTC execution log. If this LNK-805 is
reported, there is a library or Netlist shortage or specification error. Check again whether the input file is
complete.

Warning: Unable to resolve reference to 'XXXX' in 'top'. (LNK-805)

In the case of PrimeTime, LNK-005 is reported, so please check that as well.

● CASE：CLK_0021

<Debug method>
By clicking the name of the GUI Violation detail Window or the clock name of Master Clock, you can check the
corresponding restrictions. Make sure that the clock is not used in this scenario according to the design
specifications.
 Page 66/257

Limitations

CLK_0026 erroneously detects the generated clock which propagates to the data pin of the FF for the clock
divider as a feedback loop because CLK_0026 also detects the non-clock pin to which the clock definition
propagates.
 Page 67/257
R0006 Multiple paths exist from the clock pin of a sequential cell to different clock sources
Severity RTL Layout I/F STA IP
n/a Info Info Info
Category □consistency ■semantics □unclear □TDL ■check rule user’s manual
GCA CLK_0024
SpyGlass Clk_Gen06

◼ Description

This rule applies to single mode SDC.

Reports registers with propagated clocks with different sources.

◼ Sample circuit configuration and constraints

① Two or more clock definitions in one clock signals

create_clock [get_ports {CLK}] -name CLKA -period 10 -waveform {0 5}
create_clock [get_ports {CLK}] -add -name CLKB -period 30 -waveform {0 15}

② If the set_case_analysis constraint is not specified on the select pin of the mux
then the rule will flag
create_clock [get_ports {CLK2}] -name CLK2 -period 10 -waveform { 0 5 }
create_clock [get_ports {CLK3}] -name CLK3 –period 30 –waveform {0 15}

① ②

FF FF
D1 Q D1 Q
CK MUX1 CK
CLK2 net
net1 Z
1
CLK CLK3 S

set_case_analysis is not set

If the set_case_analysis constraint is not specified on the select pin of the mux then the rule will flag

GCA Message

CLK_0024：
Register Clock pin ‘pin’ has ‘count’ clocks.}.
Since the number of active paths is not fixed at 1, the net that is connected to the clock pin of FF1 is
driven by CLK2 and CLK3. （②）
Analyze_clock_networks command enables a related clock information reference.
ex.）analyze_clock_networks -to FF1/CK

Confirmation method

<Violation>
Register Clock pin 'FF02/CP' has '2' clocks.
<Debug method>
Use the analyze_clock_networks command to check the clock network on pin FF02/CP.
Check if the clock propagation is correct based on the product specifications.

ptc_shell> analyze_clock_networks -to [get_pins FF02/CP] -max_endpoints 1 -style full -end_types {register}
-nosplit
 Page 68/257
****************************************
Clock Sense Abbreviations:
P - positive
Clock Network End Type Abbreviations:
REG - register

Full report for clock: CK2

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source CLK2 (in)
1 P BLK2/MUX01/I0 (library_cell_name)
2 P BLK2/MUX01/Z (library_cell_name)
3 P REG FF02/CP (library_cell_name)

Full report for clock: CK3

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source CLK3 (in)
1 P BLK2/MUX01/I1 (library_cell_name)
2 P BLK2/MUX01/Z (library_cell_name)
3 P REG FF02/CP (library_cell_name)

GCA Limitations

The value of rule property "max_clocks_per_register" is changed from the initial value of 4 to 1.
This will report CLK_0024 when more than one clock is propagating to the clock pin of the register.
 Page 69/257
R0008 A Clock Constraint Is Set to All Register Clock Pins
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA DES_0001
DES_0002
SpyGlass Clk_Gen01a

◼ Description

If there is no clock definition for a register (F/F, RAM, or hardware macro), timing analysis cannot be performed
normally for the paths related to the register.
For this reason, checks are made to make sure that a clock is set for all registers.

Example of rule error detection

In the following circuit configuration, when "create_clock" is not defined for external port CLK from which the
clock signal is to be input to FFA, the following message is output.

◼ Sample circuit configuration and constraints

1. Clock not defined

FFA

CLK

GCA Message

DES_0001 :
Register clock pin 'FFA/CLK' has no clock signal

2. Case value propagated to the Clock pin

FFA

CLK

CEN

Create_clock -period 10 [get_ports CLK]

set_case_analysis 0 CEN

CGA Message

DES_0002 :
Register clock pin ‘pin’ is disabled due to case values or disabled constraint arcs.

-The following message has been changed in M-2017.06-SP3-3.

(There are no changes to the check contents)
All checks on clock pin ‘pin’ are disabled due to case values or disabled constraint arcs.

◼ Action
Check if a clock definition is needed for the undefined clock signal that reported the error.
If the clock definition is necessary as a result of the check, correct the SDC.

Confirmation method

■DES_0001

<Violation>
Register clock pin 'FF02/CP' has no clock signal
 Page 70/257

<Debub method>

Check if there is a potential clock at the “FF02/CP” pin.

gca_shell> get_attribute [get_pins FF02/CP] potential_clocks
{“CK"}

Then use the analyze_clock_netowrks command to see why the clock “CK” is not reaching pin “FF02/CP”.
In this case, you can see that the set_disable_timing is set on the clock network and the signal is blocked.
Check if the set_disable_timing setting is appropriate.

gca_shell> analyze_clock_networks -from [get_clocks CK] -through [get_pins FF02/CP] -traverse_disabled -

style full -nosplit
****************************************
Clock Sense Abbreviations:
P - positive
Potential senses detected with -traverse_disabled:
[P,FF] - potential positive, fall_to_fall
Clock Network End Type Abbreviations:
REG - register
CG - clock_gating

Full report for clock: CK

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source CK (in)
1 P CG CGC/CP (library_cell_name)
2 [P,FF] DT#0 CGC/Q (library_cell_name)
3 [P,FF] REG FF02/CP (library_cell_name)

Clock Blocking Constraints:

DT#0 = set_disable_timing
at pin: CGC/Q

1
 Page 71/257
■DES_0002

<Violation>
Register clock pin ‘FF02/CP’ is disabled due to case values or disabled constraint arcs.
* The report is an old message, but the debugging method has not changed.

<Debug method>
First, use the analyze_unclocked_pins command to check the status of pin FF02 / CP.
In this case, you can see that DES_0002 is reported because a Constant logic value is propagated.

gca_shell> analyze_unclocked_pins -verbose [get_pins FF02/CP]

****************************************
Analyze Register Clock Pins that do not have clocks assigned

Summary
-----------------------------------------------------------------
Register Clock Pin Status Number of Pins
-----------------------------------------------------------------
Clocked 0
Unclocked 0
Case disabled clock pin 1
Register behavior disabled 0
-----------------------------------------------------------------
Total register clock pins 1

Check for potential clock on "FF02/CP" pin.

gca_shell> get_attribute [get_pins FF02/CP] potential_clocks
{"CK2", "CK3"}

Next, use the analyze_path command to check if a constant is propagated to “FF02/CP” pin.
In this case, you can see that the constant set in the route is propagating.
Check if the set_disable_timing setting is appropriate.

gca_shell> analyze_paths -from [get_clocks CK2] -to [get_pins FF02/CP] -traverse_disabled -path_type full
-unconstrained
****************************************
Summary of Paths:
Dominant Overridden Count Clocks
Startpoint Endpoint Constraint Constraints (r,f,R,F) Launch/Capture
--------------------------------------------------------------------------------
CLK2 (in) FF02/CP (library_cell_name)
CASE#0,CASE#1 (2,2,2,2) unclocked/unclocked

Disabled Object Information:

CASE#0 = case_value_source
Sources of Case Values
Value: 1 at Pin: CLK2

CASE#1 = case_value_source
Sources of Case Values
Value: 1 at Pin: CLK2

Value: 1 at Pin: CLK3

Full report of all pins in the paths

Level Pin Attr Constraints

--------------------------------------------------------------------------------
1 CLK2 (in) Start user_case_1
2 BLK2/MUX01/I0 (library_cell_name) case_1
3 BLK2/MUX01/Z (library_cell_name) case_1
4 FF02/CP (library_cell_name) case_1
 Page 72/257
GCA/PTC LIMITATIONS

・DES_0001 detects a pseudo error for the hard macro checkpin.

This is a tool (Library Compiler). When the target object is a hard macro, two timing arcs are separated in
order to verify each timing path during STA verification. As a branch point, the tool automatically generates
checkpin inside the hard macro. If the checkpin timing constraint detected by GCA / PTC is a create_clock
command, judge it as a pseudo error.

・DES_0002 detects all timing checks (setup, hold, recovery, removal) and clock pins of cells where the
sequential arc from CK to Q is disabled. For this reason, if the enable pin of the Clock gating cell is fixed to
inactive, all timing checks will be disabled, and will be detected.
Among them, if the case setting is as intended for the pin through which the active clock passes through the
Enable pin of the DES_0002 clock gating cell, judge it as pseudo. You can get a list of pins in the following
ways:

gca_shell> source /common/appl/Renesas/GCA/RULES/V020200/utility/EDA16-RELG-T10-D-

004_GCA_DES_0002_filter_v2.tcl

＜Use Case＞
gca_shell> source EDA16-RELG-T10-D-004_GCA_DES_0002_filter_v2.tcl
gca_shell> get_pseudo_error_of_DES0002
・If there is a false error, the following message and pin name will be reported.
** <INFO> The following clock pin of the ICG cell propagates the clocks to clock out. Only the
setup/hold constraints of EnablePin/TestEnable with the clock pin are disabled. It can be judged as a false
error of DES_0002.
CGC/CPN
・If there are no false errors, nothing is reported.

If the black-box model has no logic description in the library such as IP core or RAM, and the clock attribute is
not attached to the clock pin, it is not possible to detect the leakage of the clock definition for that clock pin.
In STA, such a terminal is not handled as a clock terminal, so there may be a problem with the library.
 Page 73/257
R0010 It Is Specified That All Clocks Are Treated as Ideal (before CTS Execution)
Severity RTL Layout I/F STA IP
n/a Error n/a Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA CLK_0034
SpyGlass Clk_Gen20

◼ Description

Before CTS execution, the clock tree structure is not fixed. If it is specified that a clock is treated as
propagated, accurate timing analysis cannot be performed and unnecessary timing analysis may be performed.
For this reason, checks are made to make sure that it is specified that all clocks are treated as ideal in pre-
CTS design phases.

◼ Sample circuit configuration and constraints

When the SDC file contains "set_propagated_clock" as shown below and a template file for the RTL or Gates
(pre-CTS) is used, the following error message is output.

create_clock -name CLK -period 4 -waveform { 1 2 } [get_ports {CLK}]

set_propagated_clock [get_clocks {CLK}]

GCA Message

CLK_0034 :
Clock 'CLK' has propagated latency during pre-layout analysis.

SpyGlass Message

Clk_Gen20 Error ./top.sdc 4 10 set_propagated_clock should not be set for clock "CLK" in
synthesis/prelayout script [Also File(Lines): ./top.sdc(xx)]

Action (common)

From the clock definition for which an error is reported, remove the "set_propagated_clock" setting.
 Page 74/257
Confirmation method

Use the report_clock command to see the timing constraints that define the reported clock.
An example is shown below.

<violation>
Clock 'CLK' has propagated latency during pre-layout analysi

<constraint>
create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK]

ptc_shell> report_clock
****************************************

Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
CLK 10.000 {0 5} p {CLK}
CLK_D 40.000 {0 20} p, G {MUX01/Z}

You can also view timing constraints by clicking on the clock name in the GUI's ”ViolationBrowser”.
 Page 75/257
R0011 It Is Specified That All Clocks Are Treated as Propagated (after CTS Execution)
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA CLK_0033
SpyGlass Clk_Gen10

◼ Description

After CTS execution, the clock tree structure is fixed. Specifying that a clock is treated as propagated makes
it possible to perform timing analysis more accurately. For this reason, checks are made to make sure that it
is specified that all clocks are treated as propagated in post-CTS design phases.

◼ Sample circuit configuration and constraints

When a clock definition is made, but "set_propagated_clock" is commented out as shown below, and a
template file for Gates (post-CTS) is used, the following error message is output.

create_clock -name CLK -period 4 -waveform { 1 2 } [get_ports {CLK}]

# set_propagated_clock [get_clocks {CLK}]

GCA Message

CLK_0033：
Clock “clock” has ideal latency during post-layout analysis.

SpyGlass Message

Clk_Gen10 Error ./top.sdc 2 5 set_propagated_clock constraint not set for clock "CLK" in postlayout
analysis

Action (common)

For the clock definition for which an error is reported, set "set_propagated_clock".
 Page 76/257

R0012 A Clock Does Not Converge through More Than One Path
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency ◼semantics unclear ◼TDL ◼check rule user's
manual
GCA CLK_0030
SpyGlass Clk_Gen29

◼ Description

If a clock is propagated to a flip-flop (level latch) via more than one path, unintended timing analysis may be
performed.

◼ Sample circuit configuration and constraint

Prohibited.

GCA Message

CLK_0030 :
There is reconvergent logic in the network for clock 'clk1'.

SpyGlass Message

Clk_Gen29 Warning TEST.sdc 1 10 Same clock CLK11 defined on port/pin "clk1[1]", converges through
different combinational paths [Also File(Lines): TEST.v(12)]

Action

Please do the following one of correspondence.

1. Circuits should be corrected if there is possibility that a clock hazard occurs.

2. Please make sure that the problem of CRPR does not occur.
3. Please select one path of clock paths with set_case_analysis command.
 Page 77/257
R0013 A Clock Is Set to the Point at Which the Clock Signal Is Generated
Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category consistency semantics unclear TDL ◼check rule user's manual
GCA UDEF_GClockSetPointCheck
SpyGlass No corresponding rule

◼ Description

To consider the slew and duty of a clock signal in STA, it is necessary to set the clock to the point at which the
clock signal is generated. Basically, set the clocks to the points listed below. This rule makes a check on
create_clock. No virtual clocks are checked, however.

Target Clock type Clock setting point

Normal clock External port
Macro
Generated clock F/F output pin
Normal clock PLL or OSC output pin
Chip Generated clock F/F output pin
External input clock External port

◼ Sample circuit configuration and constraints

GCA Message

UDEF_ClockSetPointCheck :
Master Clock 'Clock' is not defined on a port or at the output pin of PLL/OSC(PLL_OSC_inst). Clock is
not defined at a proper point.

Action

Please check if the specified part of the clock reported by UDEF_ClockSetPointCheck is valid.
Confirmation method

<Violation>
A Clock 'NGclk' on 'CFF02/CP' is not defined on a port or at the output pin of PLL/OSC(PLL_OSC_inst). Clock
is not defined at a proper point.

<Constraint>
create_clock -name NGclk -period 10 [get_pins CFF02/CP]

<Debug method>

Use report_clock to check the specified point of the reported clock.

ptc_shell> report_clock NGclk

****************************************

Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
NGclk 10.000 {0 5} p {CFF02/CP}

Or, you can check the specified clock point on the GUI's “ViolationBrowser”.
 Page 78/257

GCA Limitations

Setting create_clock at the output pin of PLL or OSC causes detection of UDEF_ClockSetPointCheck.
When removing these terminals from detection target, these instances have to be specified for GCA. Please
refer to GCA’s use guide in for more information.
 Page 79/257
R0014 Prohibition of overlap between create_clock commands on the same clock network.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL ■check rule user’s manual
PTC UDEF_TransAnotherClock
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When plural create_clock are set on the same clock network, setting nearer a sequential cell becomes effective.
It should be careful that the clock latency is calculated from each clock setting points. This rule flags message
when plural create_clock are set on the same clock network
This rule does detect any clocks that are specified for the same location with the -add option. It does not take
into account the set_false_path setting between clocks.

◼ Sample circuit configuration and constraints

① Two or more occurrences of create_clock specified without -

add on the same clock network
create_clock –period 10 –waveform {0 5} –name CLK1 [get_ports CLK] (1)
create_clock –period 10 –waveform {0 5} –name CLK2 [get_pins INV2/Y] (2)

FF1
（1） INV1 D Q
CLK CK

clock path clock path for CLK2

for CLK1 FF2
INV2 D Q
CK
Y
（2）

① The overlap specify the create_clock on -add with the same clock network

create_clock –period 10 –waveform {0 5} –name CLK1 [get_ports CLK] (1)

create_clock –period 10 –waveform {0 5} –name CLK2 [get_pins INV2/Y] (2) –add

FF1
（1） INV1 D Q
CLK CK

clock path clock path for CLK2

for CLK1 FF2
INV2 D Q
CK
Y
（2）
 Page 80/257
GCA Message

UDEF_TransAnotherClock：
The clock clock1 is defined on the object that is in the transitive fanout of another clock clock2'.

Action

When considering a clock latency from (1) with setting clock at (2), create_generated_clock must be not
create_clock

Confirmation method

<Debug method>
Check the relationship between the two reported clocks.

The following is an example.

<violation>
The clock 'clk2' on 'FF01/CP' that is in the transitive fanout of another clock 'CLK_D' on 'MUX01/Z' in the SDC
file '{{/full_path/sdc.tcl 2}}'. Valid clocks are 'n/a'

<constraint>
create_clock -name clk1 -period 10 [get_pins MUX01/Z]
create_clock -name clk2 -period 10 [get_pins FF01/CP]

<Debug method>

Use the analyze_clock_networks command to check the clock reaching "FF01/CP" (clock_source).

ptc_shell> analyze_clock_networks -through FF01/CP -style full -traverse_disabled

****************************************
Clock Sense Abbreviations:
P - positive
Clock Network End Type Abbreviations:
REG - register
CS - clock_source

Full report for clock: clk2

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P REG, source
FF01/CP (library_cell_name)

Full report for clock: CLK_D

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source MUX01/Z (library_cell_name)
1 P CS FF01/CP (library_cell_name)

Or, enter the command displayed in Violation Details on the GUI's “ViolationBrowser” into the Console.
 Page 81/257

By executing this command, you can also check with “Schematic”.

Based on this information, consider whether this error is true or false, delete “clk2” (clock), and replace “clk2”
with a generated clock (defined by create_generateed_clock).
 Page 82/257
R0016 Clock Waveform Definitions Are Set as Clock Constraints
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
PTC UIC-068
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

If there is an omitted clock waveform definition, timing analysis may be performed with an incorrect clock
waveform. For this reason, checks are made to see if period and waveform are assigned as clock constraints.

◼ Sample circuit configuration and constraints

When the -period option is not defined in a clock definition as shown below, the following
message is output.

[Sample SDC description]

create_clock -name CLK -period 4 [get_ports {CLK}]

GCA Message

UIC-068：
Warning: The -waveform option for the clock is not specified. A default waveform is assumed. (UIC-068)

This UIC-068 is not a rule reported when performing SDC validation (analyze_design). This rule is reported
when SDC is read. In the case of GUI, it is displayed in UserMessage Browser (CLK_ * etc. are displayed
in Violations Browser). To output this information to a file, set the option -include {user_messages} of the
report_constraint command.

Action

Modify the SDC description to define -period and -waveform for the clock definition for which an error is
reported.

Confirmation method
In order to confirm that there is no -waveform option during SDC verification, UIC-068 must be displayed
(default is hidden). Set “suppress_message UIC-068” in the GCA / PTC execution script.

The following is an example in interactive mode.

gca_shell> unsuppress_message UIC-068
gca_shell> create_clock -name CLK -period 4 [get_ports {CLK}]
#Set timing constraints after setting variables
Warning: The -waveform option for the clock is not specified. A default waveform is assumed. (UIC-068)

If the -waveform option is not set, a waveform with a rising edge of 0.0 and a falling edge of 1/2 the period
specified with the -period option is set. You can check the status of the clock with the report_clocks command.

ptc_shell> report_clocks
****************************************
Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
CLK 4.00 {0 2} p {CLK}
CLK2 5.00 {0 3} p {CLK2}
 Page 83/257
GCA Limitations

UIC-067 and UIC-068 are used when reading SDCs. But these rules are also detected when rule checking
after reading SDCs. So ‘Renesas_sdc_start’ and ‘Renesas_sdc_end’ command are prepared to suppress
messages by their rules. Using these commands before and behind ‘read_sdc’ make suppress detection of
unnecessary message about UIC-067 and UIC-068. Please refer to the following sample to use them.

<install directory>/Renesas/GCA/RULES/<rule version>/sample/gca_run/script.tcl

 Page 84/257
R0018 Prohibition of specification of the -invert option in create_generated_clock that is
incompatible with the circuit configuration
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
PTC CLK_0036
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

STA does not calculate the timing while assuming inverted clock source even if there is an inverter in the circuit
between clock-source and generated clock when defining a generated clock with create_generated_clock
command. It detects any inconsistency between the clock polarity in the circuit configuration and the clock
polarity of the generated clock (specified in the -invert option).

◼ Sample circuit configuration and constraints

CLK
FF0
D Q D Q
INV0 reference waveform by INV0/Z
PI the circuit
Z
waveform by constraint 1
create_clock –name CLK [get_ports PI] FF0/Q
waveform by constraint 2

fig.1 fig.2

The clock waveform of INV2/Z that is expected from the circuit shown in fig. 1 is the "waveform that is expected from the
circuit configuration” shown in fig. 2. Since an inverter exists on the path that runs after the frequency division, the
waveform associated with the constraint 1 differs from the "waveform expected from the circuit configuration" because the
-invert option is not specified.

constraint 1

create_generated_clock –name GCK –source [get_pins INV0/Z] -divide_by 2 [get_pins FF0/Q]

On the other hand, if setting 'CLK' as source-clock and using '-invert' option like fig.2,
that expects "waveform by constraint 2", it differs from "reference waveform by the circuit".
This constraint causes inconvenience for implementation by logical synthesis and layout tool.

constraint 2
create_generated_clock –name GCK –source [get_ports PI] -divide_by 2 [get_pins FF0/Q] -invert

GCA Message

CLK_0036 :
Generated clock 'clock' has incorrect waveform inversion.

GCA/PTC LIMITATIONS

・CLK_0036 cannot be detected when the -edge option is used to invert the clock waveform (revision request
to Synopsys).
ex) create_clock -name CLK -period 10
create_generated_clock –name GCK –source [get_pins INVO/Z] -edges {3 5 7}

・CLK_0036 does not report for clocks for which CLK_0020 or CLK_0008 is reported.
 Page 85/257
Action (common)

Desk check how the clock that is set up in create_clock propagates into the register that generates a generated
clock. If the clock is inverted along the path following the frequency divider circuit, specify the correct clock
polarity using the -invert option.

Check the following.

・ -invert option setting mistake or specification?
・ -edges Check if there is an option setting mistake.

Therefore, check how the clock set by create_clock propagates to the register that outputs the generated clock,
and specify the -invert option if the clock is inverted in the path after the divider circuit. Set the correct clock
polarity.
Confirmation method
Clock propagation can be checked with the analyze_clock_networks command.

<Violation>
Generated clock 'gclk1' has incorrect waveform inversion.

<Constraint>
create_generated_clock -name gclk1 -divide_by 1 -source [get_ports CLK1] -master_clock [get_clocks CK1]
[get_pins BLK1/FF01/Q] -add -invert

<Debug method>

ptc_shell> analyze_clock_networks -through [get_ports {CLK1}] -to [get_clocks {gclk1}] -max_endpoints 1 -

style full -end_types {clock_source} -nosplit
****************************************
Clock Sense Abbreviations:
P - positive
R - rise_triggered
Clock Network End Type Abbreviations:
REG - register
CS - clock_source

Source latency paths for generated clock: gclk1

from master clock: CK1

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source CLK1 (in)
1 P REG BLK1/FF01/CP (library_cell_name)
2 P BLK1/FF01/CP (library_cell_name)
3 R CS BLK1/FF01/Q (library_cell_name)

Or, use the report_clock command to check the clock definition information.
 Page 86/257
ptc_shell> report_clock
****************************************
Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
CK1 6.00 {0 3} p {CLK1}
CK2 10.00 {0 5} p {CLK2}
CK3 12.00 {0 6} p {CLK3}
gclk1 6.00 {3 6} G {BLK1/FF01/Q}

Generated Master Generated Master Waveform

Clock Source Clock Modification
--------------------------------------------------------------------------------
gclk1 CLK1 BLK1/FF01/Q CK1 div(1), inv

Check the validity of the generated clock definition and design.

Review the generated clock definition and design and add or remove the -invert option to redefine the
generated clock. In this example, to match the design with the “CK1” waveform, you must remove the -invert
option.
 Page 87/257
R0019 Do not specify different value with –divide_by option of create_generated_clock command
from divide ratio which is decided by the circuit
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
PTC CLK_0020
CLK_0008
CLK_0032
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Please do not set different constraints from design structure, because it cause unexpected waveform if set
different value with –divide_by option of create_generated_clock command.
If a value different from the division ratio determined by the circuit configuration is set to the -divid_by option
of create_generated_clock, the waveform expected as the device operation cannot be obtained. This is a
pessimistic and optimistic timing check. Furthermore, depending on the conditions, the
create_generated_clock command may fail and the timing check may not be performed. Avoid constraint
settings that are different from the design structure. If the path to the master clock is a combinational circuit, it
is recommended to use the “-combinational” option instead of using “-divide_by 1”.

◼ Sample circuit configuration and constraints

1. Setting divide_by 1 for a frequency divider circuit

CLK
FF0
reference waveform
D Q D Q
by the circuit
PI wrong waveform FF0/Q
by constraint 1
wrong waveform
create_clock –name CLK [get_ports PI]
by constraint 2

fig.1 fig.2

When setting create_generated_clock for FF0/Q at fig.1, ‘-divide_by 1’ setting cause wrong
waveform by constraint 1.

Constraint 1
create_generated_clock –name GCK –source [get_ports PI] -divide_by 1 [get_pins FF0/Q]

To get expected waveform same reference waveform by the circuit, set suitable divide ratio to ‘-divide_by’
option as ‘Constraint 2’.
Constraint 2

create_generated_clock –name GCK –source [get_ports PI] -divide_by 2 [get_pins FF0/Q]

GCA Message

CLK_0020 :
Generated clock 'clock' has edge relationships with its master clock 'master_clock' that can not be
satisfied. Only paths with 'path_sense' sense exist from the master clock to source pin 'source_pin'.
A 'expected_sense' sense is expected.

Limitations

Even if source-latency-path appoints -divide_by 1 in the case of a combined circuit, GCA cannot detect it.
 Page 88/257

Setting -divide_by n (n >= 2) for a non-frequency-divider circuit (combinational circuit)

B1

Generated clock
FFB

CLK1 CLK

create_clock -name CLK -period 10 [get_ports CLK]

create_generated_clock -name CLK_div -source [get_ports {CLK1}] -divide_by 1 [get_pins {B1/CLK}]

GCA Message

CLK_0020 :
Generated clock 'clock' has edge relationships with its master clock 'master_clock' that can not be
satisfied. Only paths with 'path_sense' sense exist from the master clock to source pin 'source_pin'.
A 'expected_sense' sense is expected.

Setting -divide_by n (n >= 2) when the master pin and the source pin are the same (combinational circuit)

B1

Generated clock
FFB

CLK1 CLK

create_clock -name CLK -period 10 [get_ports CLK]

create_generated_clock -name CLK_div -source [get_pins {B1/CLK}] -divide_by 2 [get_pins
{B1/CLK}]

GCA Message

CLK_0032 :
Non-combinational generated clock 'clock' has a source identical to its master source object.

Action

Desk check the designed frequency division ratio and, when setting the timing constraint, give the same design
frequency division ratio with -divide_by or specify the -combinational option.
If the cycle ratio to the master clock exceeds 1000 times, STA tool signals an error and performs no timing
analysis on the slow clock side. In such a case, specify an appropriate frequency division ratio since the same
design frequency division ratio cannot be set.

Confirmation method

・CLK_0020

Use the report_clock command to check the relationship between the master clock and the generated clock.

create_generated_clock –name GCK –source [get_ports PI] -divide_by 1 [get_pins FF0/Q]

You can check the relationship between the generated clock and the master clock using the report_clock
command. In the above example, the report shows that the waveform of “g1” is the same as the waveform of
the master clock “clk1”.
 Page 89/257
ptc_shell> report_clock {clk1 g1}

****************************************

Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------
clk1 2.00 {0 1} {CLK}
g1 2.00 {0 1} G {mux/Z}

Generated Master Generated Master Waveform

Clock Source Source Clock Modification
--------------------------------------------------------------------------------
g1 CLK mux/Z clk1 div(1)

・CLK_0008
There are multiple paths from the master clock to the generated clock. Verify that the path depth (latency path
is different. For example, the number of cells, for example, the sequential path consisting of FF or the
combinational path of the combinational circuit is close)

Use analyze_clock_networks to check clock propagation.

 Page 90/257
gca_shell> analyze_clock_networks -through [get_ports {CLK1}] -to [get_clocks {GCLK}] -max_endpoints 1 -
style full -end_types {clock_source} -nosplit

****************************************
Clock Sense Abbreviations:
P - positive
R - rise_triggered
Clock Network End Type Abbreviations:
REG - register
CS - clock_source

Source latency paths for generated clock: GCLK

from master clock: CK1 - 2 partial path branches

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 S1 P source CLK1 (in)
1 P REG FF01/CP (library_cell_name)
2 P FF01/CP (library_cell_name)
3 R FF01/Q (library_cell_name)
4 R MUX01/I0 (library_cell_name)
5 E1 R CS MUX01/Z (library_cell_name)

Branch 1: from branch 0 reconverges to branch 0

Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
1 P REG FF02/CP (library_cell_name)
2 P FF02/CP (library_cell_name)
3 R FF02/Q (library_cell_name)
4 R REG FF03/CP (library_cell_name)
5 R FF03/CP (library_cell_name)
6 R FF03/Q (library_cell_name)
7 R MUX01/I1 (library_cell_name)
1
gca_shell>
 Page 91/257
Or, you can launch Schematic and check the clock by clicking execute and show schematic in the
ViolationBrowser in the GUI.

Limitations

To check whether the clock edge which is referenced by a generated clock is reachable from the master
clock, an ordinary 1/2 frequency divider circuit will generate no error when the value specified in -
divide_by is 2*n. (only the rise edge of the master clock can pass through a rise edge triggered FF).
If the frequency divider clock is generated by a counter + clock gating, the clock gating circuit will
generate no error whatever value is specified in the -divide_by option because the edges of all master
clocks can reach the clock generation point.
B1

FFB Generated clock

ICG
CLK1 CLK
CEN

CLK

CEN

GCLK
 Page 92/257
R0020 A Correct Source Clock Is Specified for a Generated Clock
R0020
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
PTC CLK_0016
CLK_0017
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

If there is an error in the source clock description used for generating a generated clock, clock generation may
not be performed as intended by the designer, resulting in incorrect timing analysis being performed. For this
reason, checks are made to see if a correct source clock is specified for a generated clock.

◼ Sample circuit configuration and constraints

1. If you specify the source of the CLK2 create_generated_clock there is no connection with
the FFB

There is a physical path between the specified point of “CLK2” and the specified point of the generated
clock, but the master clock signal is blocked due to some influence.

Generated clock
FFB

CLK1

create_generated_clock -name CLK_div4 -source [get_ports {CLK1}] -divide_by 4 [get_pins

{FFB/Q}]

GCA Message

CLK_0016 :
Generated clock clock has no source latency path from its master clock master_clock.

Action

Check the generated clock definition for which an error is reported to see whether the source clock is correct.
After checking, modify the SDC description to specify the correct source clock.

Confirmation method
■CLK_0016

<Violation>
Generated clock 'GCLK' has no source latency path from its master clock 'CK1'.

<Constraint>
create_clock -name CK1 -period 20 -waveform {0 10} [get_ports CLK1]
reate_generated_clock -name GCLK -divide_by 4 -source [get_ports CLK1] [get_pins MUX01/Z]
set_case_analysis 1 [get_ports SEL]
<Debug method>
For the reported clock, use analyze_clock_networks to determine the clock propagation path.
 Page 93/257
In this case, we can see that there are two paths from the master clock “CK1” to the generated clock “GCLK”.
Of these, the branch 1 path shows that the clock signal stops due to the Constant logic value of the multiplexer
selector pin. Based on this information, the authenticity of the report is determined, and the Constant logic
value is changed.

ptc_shell> analyze_clock_networks -to [get_clocks {GCLK}] -max_endpoints 1 -style full -end_types

{clock_source} -traverse_disabled -nosplit
****************************************
Clock Sense Abbreviations:
P - positive
Potential senses detected with -traverse_disabled:
[P] - potential positive
[R] - potential rise_triggered
Clock Network End Type Abbreviations:
REG - register
CS - clock_source

Source latency paths for generated clock: GCLK

from master clock: CK1 - 2 partial path branches

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 S1 P source CLK1 (in)
1 [P] REG FF01/CP (library_cell_name)
2 [P] FF01/CP (library_cell_name)
3 [R] FF01/Q (library_cell_name)
4 [R] MUX01/I0 (library_cell_name)
5 E1 [R] CS, COND#0 MUX01/Z (library_cell_name)

Branch 1: from branch 0 reconverges to branch 0

Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
1 [P] REG FF02/CP (library_cell_name)
2 [P] FF02/CP (library_cell_name)
3 [R] FF02/Q (library_cell_name)
4 [R] REG FF03/CP (library_cell_name)
5 [R] FF03/CP (library_cell_name)
6 [R] FF03/Q (library_cell_name)
7 [R] MUX01/I1 (library_cell_name)

Clock Blocking Constraints:

COND#0 = conditional_arc
at positive_unate arc from: MUX01/I0
to: MUX01/Z
 Page 94/257

Or, click “execute” in the GUI's “ViolationBrowser” to check it in Schematic.

Limitations

“No topological connection” is the reason for reporting CLK_016. Since there is no clear debugging method
in this case, a debugging method is currently being developed by Synopsys.
STAR 9001194921: (CLK_0016) Enhance Debug and violation section - No topological connection case

This is an interim measure (one sample).

In the case of “No topological connection”, the clock may be blocked in the timing path.
Therefore, find “Internal clock break points” with the analyze_clock_networks command.

sample:
clk (port) ---|>--U8(buff)----------|>---U9(Black_box)---->Flop---(Gen_clock definition)---->

This analyze_clock_network command finds where the master clock clk is stopped.
At this time, by setting the option -end_types internal_end, you can report where the clock stops.
 Page 95/257
ptc_shell> analyze_clock_networks -from [get_ports clk] -end_types internal_end

****************************************
Clock Network End Type Abbreviations:
I - internal_end
End
Example End Pin/Port Type Clocks Count
--------------------------------------------------------------------------------
U8/Z (IV) I set 0 1

Clock Sets:
set 0 (1 clocks):
clk - positive

From this report we can see that the master clock clk stops at “U8/Z” pin.
Then find the cell connected to that “U8/Z” pin.

ptc_shell> get_cells -of_objects [get_nets -of_objects U8/Z]

{"U9", "U8"}

In this case, since the clock is propagated up to cell “U8”, it turns out that the problem is in cell “U9”.
Since cell “U9” is a block box cell, the timing arc has disappeared, so the clock propagation has also stopped.

Check whether the library of cell “U9” is set correctly

Related message
If CLK2 with no FFB connection is specified as the source of create_generated_clock, and there is no physical
path between the specified point of CLK2 and the specified point of the generated clock, CLK_0017 is reported.

Generated clock
FFB

CLK1

FFA

CLK2

create_generated_clock -name CLK_div4 -source [get_ports {CLK2}] -divide_by 4 [get_pins {FFB/Q}]

GCA/PTC MESSAGE
CLK_0017 :
The master source of generated clock clock is not in the fanin of the generated clock source pin.

Limitations
In the rule set (before V02.01.01), CLK_0017 is not enabled_rule. Switch enable / disable by the following
method as required.

〈設定例〉
ptc_shell> enable_rule CLK_0017
ptc_shell> set_rule_severity error CLK_0017
ptc_shell> analyze_design
 Page 96/257
R0023 There Is One Delay Calculation Path for a Generated Clock
Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category consistency semantics unclear TDL ◼check rule user's manual
PTC UDEF_GclockMultiDelayCalcPathCheck
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When a generated clock is set, the latency (delay for the original clock) is automatically calculated. If there are
multiple paths for calculating the latency, an unintended clock latency is calculated. A path through an F/F is
also considered. Design the circuit so that there is one path for a generated clock.

◼ Sample circuit configuration and constraints

In the circuit in the figure below, there are <1> and <2> as latency calculation paths for generated clock GCLK.

<1>

GCLK

create_geneated_clock
–source [get_ports CLK]
CLK <2>
–divideby 2

GCA Message

UDEF_GclockMultiDelayCalcPathCheck：
Generated Clock 'gen_clk' in the SDC file 'SDCfile', has multiple paths to its master clock 'master_clk'.

Action

Check for any CRP problem.

Disable the timing for the unnecessary path so that there is only one delay calculation path.

set_disable_timing

GCLK

create_geneated_clock
–source [get_ports CLK]
CLK –divideby 2

Confirmation method

<Violation>
Generated Clock 'CLK_D' in the SDC file '{/full_path/sdc.tcl 9}', has multiple paths to its master clock 'CLK'.
 Page 97/257
<Constraint>
create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK]
create_generated_clock -name CLK_D -divide_by 4 -source [get_ports CLK] [get_pins MUX01/Z]

<Debug method>

To check the unnecessary path, check the path from CLK (master_clk) to CLK_D (gen_clk).
As indicated by the violation message, there are multiple routes (Branch0 and Branch1) from CLK to CLK_D,
and Branch0 is reconverged.
Check if this clock definition is valid.

ptc_shell> analyze_clock_networks -to [get_clocks CLK_D] -traverse_disabled -style full_expanded

****************************************
Clock Sense Abbreviations:
P - positive
R - rise_triggered
Clock Network End Type Abbreviations:
REG - register
CS - clock_source

Source latency paths for generated clock: CLK_D

from master clock: CLK - 2 partial path branches

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 S1 P source CLK (in)
1 P REG CFF01/CP (library_cell_name)
2 P CFF01/CP (library_cell_name)
3 R CFF01/Q (library_cell_name)
4 R REG CFF02/CP (library_cell_name)
5 R CFF02/CP (library_cell_name)
6 R CFF02/Q (library_cell_name)
7 R MUX01/I1 (library_cell_name)
8 E1 R CS MUX01/Z (library_cell_name)

Branch 1: from branch 0 reconverges to branch 0

Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
1 P REG CFF03/CP (library_cell_name)
2 P CFF03/CP (library_cell_name)
3 R CFF03/Q (library_cell_name)
4 R MUX01/I0 (library_cell_name)

Or you can check it with Schmatic by executing the above command in Console of GUI.
 Page 98/257

Execute the analyze_clock_networks command with Console as shown below.

After execution, you can see the clock propagation and two paths in Schmatic.

GCA/PTC LIMITATIONS

・The analyze_clock_networks command is used to verify UDEF_GclockMultiDelayCalcPathCheck.

”ACN-002 (report when object is not an endpoint with analyze_clock_networks -to object) may be output for
this analyze_clock_networks command. If the analyze_clock_networks command is not used in the GCA / PTC
execution script, this CAN-002 should be a false error. Similarly, if the message is ACN-004 (when a virtual
clock is specified for object) and the analyze_clock_networks command is not used in the GCA/PTC execution
script, this CAN-002 should be a false error.
 Page 99/257
R0025 Detection of the clock pin in which clock latency is not defined (Before CTS)
Severity RTL Layout I/F STA IP
n/a Info n/a Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
PTC CNL_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When set_clock_latency is not set, the layout tool sets the default value (0ns) to the clock
propagation delay value. Therefore, it reports on the clock pin to which set_clock_latency is not set so that the
designer may judge the necessity of the setting of set_clock_latency.

◼ Sample circuit configuration and constraints

The clock latency doesn't reach the clock pin.

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports CLK]

set_clock_latency 1.0 [get_pins I1/Z]

set_clock_lat
ency setting
point(clock The clock latency reach
buufer output the clock pin.
pin)

l1 l3
CK
Z
l2 l4
CLK CK
Z

The clock latency doesn't reach the

clock pin. This rule report it.

GCA Message

CNL_0005 ：
All register clock pins in the fanout of 'object' have no clock latency for clock 'clock'.

Action

Please visually confirm the report to judge necessity of clock latency.

 Page 100/257
R0026 Source or network latency not defined for a virtual clock
Severity RTL Layout I/F STA IP
n/a Info Info Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
PTC UDEF_VclkSrcLatencyCheck
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Since virtual clocks usually correspond to real clocks, latency should be set. If Latency is not set, input or
output timing calculations related to the virtual clock may be inaccurate. This rule detects a virtual clock that
has no set_clock_latency specified or has a source latency/network latency of 0.

◼ Sample circuit configuration and constraints

Specification with source latency value 0 for virtual clock

create_clock -name VClk -period 10 -waveform { 0 5}

set_clock_latency -source 0 {VClk}

GCA Message

UDEF_VclkSrcLatencyCheck：
Virtual Clock 'Clock' has no/partial source latency defined.

No latency defined on the Virtual clock.

create_clock -name VClk2 -period 10 -waveform { 0 5 }

GCA Message

UDEF_VclkSrcLatencyCheck：
Virtual Clock 'Clock' in the SDC ('SDCfile') has no/partial source latency defined.

◼ Action
Specify a value greater than 0 for the latency value specified with the set_clock_latency command.
* Negative values cannot be specified for the Latency value. If specified, UIC-028 is reported in the log. please
check the log file.
Warning: Negative clock latency specified: -1 (UIC-028)
 Page 101/257
Confirmation method
Please check clock latency with report_clock command.

You can check the clock latency value using the report_clock command for the current value.

■When source latency value 0 is specified for virtual clock

<Violation>
Virtual Clock 'VClk' in the SDC ('/full_path/sdc.tcl') has no/partial source latency defined.

<Constraint>
create_clock -name VClk -period 10 -waveform { 0 5 }
set_clock_latency -source 0 {VClk}

<Debug method>

ptc_shell> report_clock -skew VClk

****************************************
Min Condition Source Latency Max Condition Source Latency
--------------------------------------------------------------------------------
Object Early_r Early_f Late_r Late_f Early_r Early_f Late_r Late_f Rel_clk
-----------------------------------------------------------------------------------------------
VClk 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 --

■When Latency is not specified for virtual clock

The same message is displayed when the latency is not specified for the virtual clock, but if you check with
the report_clock command, an empty report is displayed.

<Violation>
Virtual Clock 'VClk' in the SDC ('/full_path/sdc.tcl') has no/partial source latency defined.

<Constraint>
create_clock -name VClk -period 10 -waveform { 0 5 }
# set_clock_latency -source 0 {VClk}

<Debug method>

ptc_shell> report_clock -skew VClk

****************************************

Limitations
If it falls under "2.No latency specified for virtual clock", report_clock -skew will not report the virtual clock.This
is because the clock latency value for the virtual clock is not set by default.Check the design specifications to
see if the latency value is required for the virtual clock for which UDEF_VclkSrcLatencyCheck is reported.

ptc_shell> report_clock -skew {VClk2}

****************************************
※ Virtual clocks without a clock latency value are not reported.
1
 Page 102/257
R0027 Necessary Conditions Are Defined for Latency
R0027
Severity RTL Layout I/F STA IP
n/a Warning Warning Info
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
PTC CNL_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When latency is defined, different specifications can be defined for early and late conditions. If only either of
these conditions is defined, necessary timing analysis may not be performed because latency is not considered
for the undefined condition.
For this reason, checks are made to see if constraints supposed to be paired are defined in latency definition.

◼ Sample circuit configuration and constraints

When only -early is valid and -late is invalid in "set_clock_latency" as shown below, an error related to this rule
is detected.
set_clock_latency -source -early 5.432 [get_clocks {CLK}]
# set_clock_latency -source -late 6.789 [get_clocks {CLK}] ←no constraint

GCA Message

CNL_0005 :
All register clock pins in the fanout of 'pin' have no clock latency for clock 'clock'.

Action

Check the latency definition for which an error is reported to see whether the insufficient condition definition is
required.
After checking, if the definition is required, modify the SDC description.

Confirmation method

set_clock_latency -source -early 5.432 [get_clocks {CLK}]

ptc_shell> report_clock -skew CLK
****************************************

Min Condition Source Latency Max Condition Source Latency

--------------------------------------------------------------------------------
Object Early_r Early_f Late_r Late_f Early_r Early_f Late_r Late_f Rel_clk
-----------------------------------------------------------------------------------------------
CLK 5.432 5.432 - - 5.432 5.432 - - --

Limitations

CNL_0005 also detects that network latency is not set or is set to 0.

 Page 103/257
R0028 A Clock Latency is Set (Before CTS)
R0028
Severity RTL Layout I/F STA IP
n/a Info n/a n/a
Category consistency ◼semantics unclear TDL check rule user's manual
PTC CNL_0005
CSL_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

In Front-end design, an ideal clock is set. At this time, the clock path delay is 0 by default. Actually, a delay is
also generated on the clock path, so any problem with timing caused by the clock path delay cannot be
analyzed. For this reason, set a clock delay for all clocks including generated clocks as an estimated value.

◼ Sample circuit configuration and constraints

No clock latency setting

create_clock -name CLK12 -period 10 [get_ports CLK12]

＃ set_clock_latency -source 3 [get_clocks CLK1２]  Not set.

GCA Message

CNL_0005 ：
All register clock pins in the fanout of 'object' have no clock latency for clock 'clock'.

CSL_0004
Generated clock 'clock' master clock 'master_clock' is not propagated and has zero or incomplete
source latency values.
 Page 104/257
R0029The Source Latency Is Set for a Generated Clock. (Before CTS)
R0029
Severity RTL Layout I/F STA IP
n/a Info n/a n/a
Category consistency ◼semantics unclear TDL check rule user's manual
PTC CSL_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

In Front-end design, an ideal clock is set. At this time, the source latency (delay up to the generated clock
setting pin) is 0 for a generated clock. Actually, a delay is also generated on the clock path, so any problem
with timing caused by the generated clock delay cannot be analyzed. For this reason, set the source latency
for the generated clock as an estimated value.

◼ Sample circuit configuration and constraints

Source latency

create_generated_clock -name GCLK -divide_by 2 -source [get_ports CLK] [get_pins FFB/Q]

#set_clock_latency –source 2 [get_clocks GCLK]  Not set.

GCA Message

CSL_0004：
Generated clock 'clock' master clock 'master_clock' is not propagated and has zero or incomplete
source latency values.
 Page 105/257
R0030 set_clock_transition should not be set on clock in postlayout (After CTS)
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
PTC CTR_0006
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The Clk_Trans11 rule flags set_clock_transition constraints set on clocks in the postlayout phase.
In post-layout, transition values are supposed to be computed through the clock network.
If you specify set_clock_transition, it directly annotates the transition value on the clock terminal of the register,
which could be different. from what will actually propagate.
* Due to the low usage frequency, the Renesas recommended rules are currently not supported.

◼ Sample circuit configuration and constraints

The set_clock_transition constraints set on clocks in the postlayout phase.

create_clock -name CK1 -period 10.000000 -waveform { 0.000000 5.000000 } {clk}

set_clock_transition 3.3 -fall [get_clocks CK1]

set_clock_transition setting point

clk

create_clock
setting point

GCA Message

CTR_0006 ：
Clock clock has clock transition values in post-layout.
 Page 106/257

R0031 Clock transition value set by using set_clock_transition is outside technology bounds
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
PTC TRN_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When clock transition value is set out of tolerance level of library or technology, chip implementation becomes
difficult. Therefore, the set_clock_transition should have suitable value.

◼ Sample circuit configuration and constraints

clock with improper clock transition values specified with the

set_clock_transition commands. (-default_min_transition=0)

create_clock -name CK1 -period 10 -waveform {0 5} clk

set_clock_transition 0 CK1

set_clock_transition setting point

clk

create_clock
setting point

GCA Message

TRN_0001 :
The transition constraint on 'object_type’ ‘object' is larger than the maximum transition design rule.

Please confirm the setting value with report_clock.

Example:
report_clock -skew CK1

◼ Action
Specify a clock transition value that is smaller than the maximum transition value defined in the library definition.
Confirmation method
Check whether the value specified in the timing constraint is correct.

<Violation>
The transition constraint on 'pin' 'CFF01/CP' is larger than the maximum transition design rule.

<Constraint>
set_annotated_transition 5 [get_pins CFF01/CP]

<Debug method>
 Page 107/257

You can check the “value defined in the library” and “specified value of set_annotated_transition” of the pin
reported by ViolationBrower of GUI.

Library-defined pin capacitance

Value specified with set_annotated_transition

 Page 108/257
R0032 Clock should be set transition time (Before CTS)
R0032
Severity RTL Layout I/F STA IP
n/a Warning n/a Warning
Category consistency ◼semantics unclear TDL check rule user's manual
PTC CTR_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

In Front-end design, an ideal clock is set. At this time, the transition time of a clock signal is 0 (ideal
waveform) by default. Actually, a transition time is generated for the clock signal, so any problem with timing
caused by the slew cannot be analyzed. For this reason, set a clock transition time for all clocks including
generated clocks as an estimated value.
Due to the low usage frequency, the Renesas recommended rules are currently not supported.

◼ Sample circuit configuration and constraints

Clock transition time

#set_clock_transition 0.5 [get_clocks PCLK] ;# No setting

GCA/PTC MESSAGE
CTR_0005 :
Clock 'clock' has no clock transition values in pre-layout.
◼ Action

Set set_clock_transition to the reported clock.

set_clock_transition 0.2 -rise [get_clocks CLK]

set_clock_transition 0.1 -fall [get_clocks CLK]

Limitations

Check if the reported clock has set_clock_transtion.

<violation>
Clock 'CLK' has no clock transition values in pre-layout.

<constraint>
create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK]
 Page 109/257

R0034 Uncertainty Is Defined for Clock Constraints

Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UNC_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If "set_clock_uncertainty" corresponding to a clock constraint is not defined, EDA tools do not take jitter
into account. So, necessary timing analysis may not be performed.
For this reason, checks are made to see if "set_clock_uncertainty" is defined for each clock constraint.

◼ Sample circuit configuration and constraints

When an SDC description contains only a clock definition, and does not contain "set_clock_uncertainty"
as shown below, the following message is output. Targets of this rule are both of simple uncertainty and
interclock uncertainty.

create_clock -name CLK -period 4 -waveform { 1 2 } [get_ports {CLK}]

GCA Message

UNC_0003 :
Clock uncertainty is incomplete or incorrect between two interacting clocks 'clock1' and 'clock2'’

Action

Check the clock definition for which an error is reported to see whether a jitter definition is required.
After checking, if a jitter definition is required, modify the SDC description.

◼ Confirmation method
Use the report_clock command to check the uncertainty of the reported clock.

The following is one sample.

<Violation>
Clock uncertainty is incomplete or incorrect between two interacting clocks 'CLK' and 'CLK'

<Constraint>
set_clock_uncertainty -hold 0.2 -from [get_clocks CLK] -to [get_clocks CLK]

If you look at the report of the report_clock command, you can see that the Uncertainty between clocks is
specified as the Uncertainty on the Hold side, and the value on the Setup side is not specified.

Hold Setup
rise-rise 0.20 -
rise-fall 0.20 -
fall-rise 0.20 -
fall-fall 0.20 -

ptc_shell> report_clock -skew [get_clock {CLK}]

****************************************

From To Hold Setup

Object Object Uncertainty Uncertainty
-----------------------------------------------------------------------------------------------
CLK CLK 0.200 -
 Page 110/257
Or you can check the Violation Details of “ViolationBrowser” in GUI.
By clicking execute, you can get the information of “report_clock -skew [get_clocks {CLK}]” above.

Clock Uncertainty の状態

◼ Limitations

・UNC_0003 also detects when set_clock_uncertainty is not set or the set value is 0.
・Check specification change of UNC_0003 is changed in the rule set (RenesasCommonRule_IP / Layout /
STA).

<Settings>
If you are using a ruleset, you do not need to set this variable.
set_rule_property suppress_violations_for_incorrect_uncertainty true UNC_0003

<Specification change>
In addition to the normal check, by default (when the above variable is false), set_clock_uncertainty setup
and also check the size of hold (if setup value> hold value). This rule check is excluded when using rule sets.
 Page 111/257
R0035 Confirm the lack of conditions in the definition of uncertainty
Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC UNC_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When uncertainty is defined, different specifications can be defined for setup and hold conditions. If only
either of these conditions is defined, necessary timing analysis may not be performed because uncertainty is
not considered for the undefined condition.
For this reason, checks are made to see if constraints supposed to be paired are defined in uncertainty
definition. Targets of this rule are both of simple uncertainty and interclock uncertainty
This rule detects the case in which latency is set for any object other than the clock objects.

◼ Sample circuit configuration and constraints

When only -setup is valid and -hold is invalid in "set_clock_uncertainty" as shown

below, an error related to this rule is detected.

set_clock_uncertainty -setup 0.2 -from [get_clocks CLK1] -to [get_clocks CLK2]

# set_clock_uncertainty -hold 0.2 -from [get_clocks CLK1] -to [get_clocks CLK2]

GCA Message

UNC_0003 :
Clock uncertainty is incomplete or incorrect between two interacting clocks clock1 and clock2

Action

Check the uncertainty definition for which an error is reported to see whether the insufficient condition definition
is required.
After checking, if the definition is required, modify the SDC description.

◼ Confirmation method
Use the report_clock command to check the uncertainty of the reported clock.
One sample:

<Violation>
Clock uncertainty is incomplete or incorrect between two interacting clocks 'CLK' and 'CLK'

<Constraint>
set_clock_uncertainty -hold 0.2 -from [get_clocks CLK] -to [get_clocks CLK]

If you look at the report of the report_clock command, you can see that the Uncertainty between clocks is
specified as the Uncertainty on the Hold side, and the value on the Setup side is not specified.

Hold Setup
rise-rise 0.20 -
rise-fall 0.20 -
fall-rise 0.20 -
fall-fall 0.20 -

ptc_shell> report_clock -skew [get_clocks {CLK}]

****************************************

From To Hold Setup

Object Object Uncertainty Uncertainty
-----------------------------------------------------------------------------------------------
 Page 112/257
CLK CLK 0.200 -

Or you can check the Violation Details of ViolationBrowser in GUI.

By clicking execute, you can get the information of “report_clock -skew [get_clocks {CLK}]” above.

Clock Uncertainty status

GCA Limitations

UNC_0003 checks any valid timing paths. In addition, the rule property
suppress_violations_for_incorrect_uncertainty is set to true to suppress the magnitude relation check between
setup and hold.

・UNC_0003 also detects when set_clock_uncertainty is not set or the set value is 0.
・Check specification change of UNC_0003 is changed in the rule set (RenesasCommonRule_IP/Layout/ STA).

<Settings>
If you are using a ruleset, you do not need to set this variable.
set_rule_property suppress_violations_for_incorrect_uncertainty true UNC_0003

<Specification change>
In addition to the normal check, by default (when the above variable is false),
set_clock_uncertainty setup and also check the size of hold (if setup value> hold value). Use rulesets
If you're excluding this size check.
 Page 113/257
R0056 set_input_transition must be defined on clock ports in postlayout stage (After CTS)
Severity RTL Layout I/F STA IP
n/a Info Error Info
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC DRV_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The Clk_Trans07 rule flags primary clock ports (specified using the create_clock constraint) without
set_input_transition constraint set in the post-layout phase.
In post-layout, the clock transition and delay values are propagated through the network. Therefore, transition
values should be defined at the input port, so that the values may be propagated across the clock network.

◼ Sample circuit configuration and constraints

set_input_transition command is not specified on clock port

clk

create_clock
setting point

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

GCA Message

DRV_0001 ：
Input/inout port 'port' has no input transition or driving cell or drive resistance specified.

Limitations

DRV_0001 also detects undefined conditions for input ports other than clock ports and input/output ports.
 Page 114/257
R0099 Prohibition of specification for clock definition to the select pin of MUX
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UDEF_definedClockMuxSelPin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Usually, signals which goes via control pin of MUX does not become clocks.

FFA

create_clock CLK1 MUX

◼ Sample circuit configuration and constraints

If clock is set at a control signal of MUX on the following circuit, the following message appears.

create_clock –name CLK1 –period 10 –waveform {0 5}

[get_ports SEL]
create_clock –name CLK2 –period 12 –waveform {0 6} FFA
[get_ports D2]
D1 MUX
D2

SEL
GCA Message

UDEF_definedClockMuxSelPin
The clock 'clock' is passed on the MUX select pin 'select_pin'. This clock is set in the SDC file'SDCfile'.
Please analyze w/ analyze_clock_network -from 'clock_name' -style full.

Action

Please visually confirm whether clock definition is wrong or not to repair clock source if it’s a setting mistake.
 Page 115/257
◼ Confirmation method

<Violation>
The clock 'clk1' is passed on the MUX select pin 'MUX01/S'. This clock is set in the SDC file'{{/full_path/sdc.tcl
3}}'. Please analyze w/ analyze_clock_network -from 'clk1' -style full.

<Constraint>
create_clock -name clk1 -period 10 -waveform {0 5} [get_ports SEL]

<Debug method>
As indicated by the violation message, the clock has reached the multiplexer selector pin "MUX01/S".

If you want to check details, you can use the analyze_clock_network command to check the status of the clock
network where clock clk1 reaches pin "MUX01/S".

ptc_shell> analyze_clock_network -from [get_clocks clk1] -through [get_pins MUX01/S] -style full
****************************************
Clock Sense Abbreviations:
P - positive
P,N - positive, negative
Clock Network End Type Abbreviations:
CS - clock_source

Full report for clock: clk1

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source SEL (in)
1 P MUX01/S (library_cell_name)
2 P,N CS MUX01/Z (library_cell_name)

Or, you can check with “Schematic” by entering the above command in the “Console” of the GUI.
 Page 116/257
R0112 A Clock Does Not Converge through More Than One Path.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC CLK_0020
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

STA does not calculate the timing while assuming inverted clock source even if there is an inverter in the circuit
between clock-source and generated clock when defining generated clock with create_generated_clock
command.
Notice: ‘-invert’ option of create_generated_clock command is used to invert the polarity of the generated clock.

◼ Sample circuit configuration and constraints

CLK
FF0
D Q D Q INV0/Z
INV0 reference waveform by
PI the circuit
Z
waveform by constraint 1 FF0/Q
create_clock –name CLK [get_ports PI]
waveform by constraint 2

fig.1 fig.2

The divided clock at FF0/Q at fig.1 expects “reference waveform by the circuit" at fig.2. We must set clock-source to
"INV0/Z" which inverts CLK, not "CLK", when defining divided clock synchronized in the falling edge at the FF0/Q (Refer
to constraint 1). This setting makes "waveform by constraint 1" same as “reference waveform by the circuit".

constraint 1

create_generated_clock –name GCK –source [get_pins INV0/Z] -divide_by 2 [get_pins FF0/Q]

On the other hand, if setting 'CLK' as source-clock and using '-invert' option like fig.2,
that expects "waveform by constraint 2", it differs from "reference waveform by the circuit".
This constraint causes inconvenience for implementation by logical synthesis and layout tool.

constraint 2
create_generated_clock –name GCK –source [get_ports PI] -divide_by 2 [get_pins FF0/Q] -invert

GCA Message

CLK_0020 :
Generated clock 'clock' has edge relationships with its master clock 'master_clock' that can not be
satisfied. Only paths with 'path_sense' sense exist from the master clock to source pin 'source_pin'.
A 'expected_sense' sense is expected.

Action

Please visually confirm how clock set by create_clock propagate at FFs that output generated clock. Then use
the output of the last stage inverter which inverts clock as clock source for generated clock if inverted clock
propagate. Use the -edges option as follows:

create_generated_clock –name GCK –source [get_clocks CLK] -edges { 2 4 6} [get_pins FF0/Q]

 Page 117/257

R0119 Wildcard Which Matches Object Besides Clock Is Prohibited for set_clock_latency
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UIC-002
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

PrimeTime applies clock latency to any valid clock-sources specified by ‘*’. ICC（DC: Design Compiler ) does
not apply clock latency to any clock-source or non-clock source specified by ‘*’. This causes discrepancy
between PrimeTime and ICC（DC) timing results.
This rule detects the case in which latency is set for any object other than the clock objects.

◼ Sample circuit configuration and constraints

create_clock -period 10 -waveform {1 6} -name CK1 [get_ports CLK1]

create_clock -period 10 -waveform {2 7} -name CK2 [get_pins C2/Y]
create_clock -period 10 -waveform {3 8} -name CK3 [get_pins C3/Y]
set_clock_latency -source 2.0 C*/Y

GCA/PTC MESSAGE
UIC-002:
Unable to set %s on '%s'; %s.

ex)
Unable to set clock source latency on 'C1/Y'; the object is not a clock source.

◼ Action
Define the clock name and pin / pin name directly for the object specified by the set_clock_latency command,
without using the wild card ‘*’.

The set_clock_latency command defines the time required for propagation from the clock setting location to
the clock pin from the clock setting location to the first sequential cell as the clock source latency as the clock
source latency and the clock network latency depending on the specified location. Check the design
specifications.
The following is an example of clock source latency.
create_clock -period 10 -waveform {1 6} -name CK1 [get_ports CLK1]
create_clock -period 10 -waveform {2 7} -name CK2 [get_pins C2/Y]
create_clock -period 10 -waveform {3 8} -name CK3 [get_pins C3/Y]
set_clock_latency -source 2.0 [get_clocks CK1]
set_clock_latency -source 2.0 [get_clocks CK2]
set_clock_latency -source 2.0 [get_clocks CK3]
 Page 118/257
◼ Confirmation method

You can check the timing constraints reported by “UserMessageBrowser” in the GUI.

Or, the corresponding object can be confirmed in the log with the following message.
source ./sdc.tcl
Error: Unable to set clock source latency on 'CINV01/ZN'; the object is not a clock source. (UIC-002)
Error: Unable to set clock source latency on 'CINV02/ZN'; the object is not a clock source. (UIC-002)
Error: Unable to set clock source latency on 'CINV03/ZN'; the object is not a clock source. (UIC-002)
 Page 119/257
R0120 Prohibition of specification of a clock port for a set_clock_uncertainty multi-clock
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UDEF_clock_uncertainty_mux
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

PrimeTime and ICC（DC) may use different clock uncertainty set on clock ports for a convergence clock from
multiple clocks. This causes discrepancy between PrimeTime and ICC（DC) timing results.

create_clock -period 10 -waveform {0 5} -name CK0 [get_ports CLK0]

create_clock -period 20 -waveform {0 10} -name CK1 [get_ports CLK1]
set_clock_uncertainty 2 [get_ports CLK0]
set_clock_uncertainty 3 [get_ports CLK1]

GCA Message

UDEF_clock_uncertainty_mux:
set_clock_uncertainty is wrongly set point at 'clockpin_source'. Because the multiple
clocks('converged_clocks') are converged at the instance ('instance'). Please each clock is set
"set_clock_uncertainty [get_clocks 'clock']".

Action

Set ‘set_clock_uncertainty’ to the clock object.

create_clock -period 10 -waveform {0 5} -name CK0 [get_ports CLK0]
create_clock -period 20 -waveform {0 10} -name CK1 [get_ports CLK1]
set_clock_uncertainty 2 [get_clocks CK0]
set_clock_uncertainty 3 [get_clocks CK1]

◼ Confirmation method
<Violation>
Violation 1: set_clock_uncertainty is wrongly set point at 'CLK2'. Because the multiple clocks('CK2 CK1') are
converged at the instance ('MUX01'). Please each clock is set "set_clock_uncertainty [get_clocks 'CK2']".

Violation 2: set_clock_uncertainty is wrongly set point at 'CLK1'. Because the multiple clocks('CK2 CK1') are
converged at the instance ('MUX01'). Please each clock is set "set_clock_uncertainty [get_clocks 'CK1']".

<Constraint>
create_clock -name CK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name CK2 -period 20 -waveform {0 10} [get_ports CLK2]
set_clock_uncertainty 1 [get_ports CLK1]
set_clock_uncertainty 2 [get_ports CLK2]

<Debug method>
 Page 120/257
You can check the part reported by “ViolationBrowser” of GUI and the description of the corrective action.

GCA Limitations

GCA simply detects that set_clock_uncertainty is set for a port or pin.

 Page 121/257

R0124 A generated clock that has two or more clock sources with branches must not be present
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC UDEF_UndefinedPartClockGene
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When there are more than one clock source with branches, OCV timing analysis calculates the generated
clock constraints pessimistically. A common point is searched every clock object, and source point outside the
course is also analyzed. Therefore, OCV timing analysis becomes pessimistic at the following case. Because
GCK1 set at I4/Z outside clock course is also considered and common point I2/Y is used when analyzing the
path from F2 to F3.

◼ Sample circuit configuration and constraints

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports clk]

create_generated_clock -divide_by 1 -name GCK0 ¥
-source [get_pins {I1/Z}] [get_pins {I1/Z}] -master_clock GCK0 -add
create_generated_clock -divide_by 1 -name GCK1 ¥
-source [get_pins {I1/Z}] [get_pins {I2/Z I4/Z}] -master_clock GCK0 -add
create_generated_clock -divide_by 1 -name GCK2 ¥
-source [get_ports {clk}] [get_pins I6/Z] -master_clock GCK0 –add

F2
GCK0
GCK1
F3
GCK2
I5 I6
F1
I1 I2 I3 I4
clk

GCA Message

UDEF_UndefinedPartClockGene
Mismatch between generated clock definitions at pin from_pin -> to_pin and potential master clocks.
Clock name : clock

Action

1. Rename GCK1, which the clock set as more than one points(I2/ZY、I4/Z), to handle as different clocks.
create_generated_clock -divide_by 1 -name GCK1_1 ¥
-source [get_pins {I1/Z}] [get_pins {I2/Z}] -master_clock GCK0 –add
create_generated_clock -divide_by 1 -name GCK1_2 ¥
-source [get_pins {I1/Z}] [get_pins {I4/Z}] -master_clock GCK0 –add

2. Set the master clock of GCK2 to I1/Z.

create_generated_clock -divide_by 1 -name GCK2 ¥
-source [get_pins {I1/Z}] [get_pins I6/Z] -master_clock GCK0 –add
 Page 122/257
R0125 A generated clock of which the master clock is a multi-clock must not be present
R0125
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC CLK_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

If there are two or more locations that will serve as master clocks with a generated clock constraint, a generated
clock is set two or more master clocks, resulting in an unclear generated clock definition unless the --
master_clock option is specified. This condition is therefore inhibited.
This rule checks that no master clock is explicitly specified with the -master_clock option when there are two
or more locations that will serve as master clocks with a generated clock constraint.

◼ Sample circuit configuration and constraints

FF1

CLK

-master_clock option is not specified

create_clock -name CLK_33 -period 33 [get_ports CLK]
create_clock -name CLK_48 -period 48 [get_ports CLK] -add
create_generated_clock -name CLK_DIV2 -divide_by 2 [get_pins FF1/Q]

GCA Message

CLK_0004
Mismatch between generated clock definitions at pin_or_port and potential master clocks.

Action

Use the -master_clock option to create_generated_clock command to define the master clock.
◼ Confirmation method

<violation>
Mismatch between generated clock definitions at ' FF01/Q ' and potential master clocks.

<constraint>
create_clock -name CLK_33 -period 33 [get_ports CLK1]
create_clock -name CLK_48 -period 48 [get_ports CLK1] -add
create_generated_clock -name CLK_DIV2 -divide_by 2 -source [get_ports CLK1] [get_pins FF01/Q]

Check the relationship between the master clock and the generated clock on the GUI ViolationBeroser.
In this case, the master clock of the generated clock “CLK_DIV2” is automatically set to “CLK_33”, which has
a faster clock.
To prevent automatic interpretation by the tool in this way, define a master clock for the generated clock
“CLK_DIV2”.
 Page 123/257

You can also check Schematic by clicking Schmeatic in “ViolationBrowser”.

 Page 124/257
R0126 Generated clocks must be defined for all master clocks
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC CLK_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

If the section that is to be the master clock of the generated clock constraints there is more than one, you can
detect when you have not set the clock derived constraints to the master clock of all. Sealing the clock
constraint at the specified -master_clock options.

◼ Sample circuit configuration and constraints

FF1

CLK

create_clock –name CLK_33 –period 33 [get_ports CLK]

create_clock –name CLK_48 –period 48 [get_ports CLK] -add
create_generated_clock –name CLK_33_DIV2 –master_clock CLK_33 -divide_by 2 [get_pins FF1/Q]
# create_generated_clock –name CLK_48_DIV2 –master_clock CLK_48 –divide_by 2 [get_pins FF1/Q]
Because -master_clock is not set, not generated clock definition for CLK_48.

GCA Message

CLK_0004
Mismatch between generated clock definitions at pin_or_port and potential master clocks.

Confirmation method

<violation>
Mismatch between generated clock definitions at 'FF01/Q' and potential master clocks.

<constraint>
create_clock -name CLK_33 -period 33 [get_ports CLK1]
create_clock -name CLK_48 -period 48 [get_ports CLK1] -add
create_generated_clock -name CLK_33_DIV2 -master_clock CLK_33 -divide_by 2 ¥
-source [get_ports CLK1] [get_pins FF01/Q] -add

Check the relationship between the master clock and the generated clock on the GUI “ViolationBeroser”.
In this case, the master clock of the generated clock “CLK_DIV2” is automatically set to “CLK_33”, which has
a faster clock.
To prevent automatic interpretation by the tool, define all master clocks for the generated clock “CLK_DIV2”.

Define timing constraints for clock “CLK_48”.

create_generated_clock -name CLK_48_DIV2 -master_clock CLK_48 -divide_by 2 ¥
-source [get_ports CLK1] [get_pins FF01/Q] -add
 Page 125/257

You can also check Schematic by clicking Schmeatic in “ViolationBrowser”.

GCA Limitations

You may not properly detect if the flag rules.

R0124 “エラー! 参照元が見つかりません。” A generated clock that has two or more clock sources with
branches must not be present
 Page 126/257
R0127 Care must be taken with respect to duplicated -name options for a clock definition
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UIC-034
UIC-065
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Specified after the create_clock/create_generated_clock command is enabled, without any warning message
output ICC, PrimeTime to command -name options in duplicate. However, the ban for the intentions of the
constraints is difficult to understand.

◼ Sample circuit configuration and constraints

create_clock -name CLK -period 10 [get_ports {P1 P2}]

create_clock -name CLK -period 10 [get_ports P3]

Explanation
create_clock -name CLK -period 10 [get_ports P3]

GCA Message

UIC-034
Redefining clock '%s'. %s

ex)
Redefining generated clock create_clock_name. Previously defined at: SDCfile, line lineNo

UIC-065
Redefining generated clock '%s'. %s

ex)
Redefining generated clock generated_clock_name. Previously defined at: ‘SDCfile, line lineNo

Action

Remove the duplicate clock name for the clock definition for which this message was reported.

Confirmation method

UIC-034 and UIC-065 above are reported in the log.

Or you can check with UserMessageBrowser of GUI.
 Page 127/257
R0135 Note the size relation of skew when using set_clock_uncertainty
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UNC_0004
UNC_0005
UNC_0006
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When the skew between clocks and the skew of a clock are set as the same pin, port or clock, set a large
value to the way of the skew between clocks by set_clock_uncertainty.
The in phase clock, or the clock between different frequency is not subject to check by the rule.

◼ Sample circuit configuration and constraints

FFA FFB

Q DATA Q
DIN DATA

CLock “clk1” CLK CLK

CLK1

fig.1 sample circuit

①The skew between clocks should be larger than the simple clock skew.
create_clock -name "clk1" -period 10 [get_ports CLK1]
set_clock_uncertainty 0.5 -from [get_clock clk1] -to [get_clock clk1] ・・・ constraint A
set_clock_uncertainty 0.6 [get_clock clk1] ・・・ constraint B

Regarding the "constraint A" and "constraint B", if the skew value of "constraint B" is larger than the skew
value of "constraint A" the GCA reports following message.

Min Rise Min Fall Max Rise Max Fall Hold Setup Related
Object Delay Delay Delay Delay Uncertainty Uncertainty Clock
-----------------------------------------------------------------------------------------------
clk1 - - - - 0.60 0.60 --
constraint B
From To Hold Setup
Object Object Uncertainty Uncertainty constraint A
-----------------------------------------------------------------------------------------------
clk1 clk1 0.50 0.50

fig.2 Report of “report_clock –skew”

GCA Message

UNC_0004
Inter-clock uncertainty is smaller than simple uncertainty for clock X.
 Page 128/257
Action

Set the skew value of "constraint A" to the value exceeded in the skew value of "constraint B".
“Value of constraint A” >= “Value of constraint B”

Limitations

In the following case, a path which is set by set_false_path is also checked by the rule.
A port is defined as a clock and the port is specified by "-from" of set_false_path.
(GCA does not regard the path as a false path.)

②The skew between clocks should be larger than the clock skew of pin/port.
create_clock -name "clk1" -period 10 [get_ports CLK1]
set_clock_uncertainty 0.5 -from [get_clock clk1] -to [get_clock clk1] ・・・ constraint A
set_clock_uncertainty 0.6 [get_ports CLK1] ・・・ constraint B

Regarding the "constraint A" and "constraint B", if the skew value of "constraint B" is larger than the skew value
of "constraint A" the GCA reports following message.

Min Rise Min Fall Max Rise Max Fall Hold Setup Related
Object Delay Delay Delay Delay Uncertainty Uncertainty Clock
-----------------------------------------------------------------------------------------------
CLK1 - - - - 0.60 0.60 --

From To Hold Setup constraint B

Object Object Uncertainty Uncertainty constraint A
-----------------------------------------------------------------------------------------------
clk1 clk1 0.50 0.50

fig.3 Report of “report_clock -skew”

GCA Message

UNC_0005
Inter-clock uncertainty is smaller than object based uncertainty at pin/port for clock X.

Action

Set the skew value of "constraint A" to the value exceeded in the skew value of "constraint B".

Limitations

In the following case, a path which is set by set_false_path is also checked by the rule.
A port is defined as a clock and the port is specified by "-from" of set_false_path.
(GCA does not regard the path as a false path.)

③The skew of a clock network should be the same as the clock of a pin/port or larger.
create_clock -name "clk1" -period 10 [get_ports CLK1]
set_clock_uncertainty 0.5 [get_port CLK1] ・・・ constraint A
set_clock_uncertainty 0.6 [get_clocks clk1] ・・・ constraint B

Regarding the "constraint A" and "constraint B", if the skew value of "constraint B" is larger than the skew value
of "constraint A" the GCA reports following message.

Min Rise Min Fall Max Rise Max Fall Hold Setup Related
Object Delay Delay Delay Delay Uncertainty Uncertainty Clock
-----------------------------------------------------------------------------------------------
clk1 - - - - 0.60 0.60 --
CLK1 - - - - 0.50 0.50 --
constraint B
constraint A

fig.4 Report to “report_clock -skew”

 Page 129/257
GCA Message

UNC_0006
Object-based uncertainty at pin/port is smaller than simple uncertainty for clock X.

◼ Action
Set the skew value so that the value of Constraint A is greater than or equal to Constraint B.
- “Value of constraint A” >= “Value of constraint B”

Limitations

In the following case, a path which is set by set_false_path is also checked by the rule.
A port is defined as a clock and the port is specified by "-from" of set_false_path.
(GCA does not regard the path as a false path.)
 Page 130/257
R0136 Specified point should not be set to jump over the frontward of the generated clock
definition
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UDEF_JumpGclkForSourcePin
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Previously PrimeTime 2014.12-SP3-1, if multiple generated clocks are defined on the basis of the same master
clock, and the source point of the latter stage of the generated clock is set to jump the generation portion of
the front of the generated clock, clock information is updated incrementally, CRPR (pessimism removal of the
common clock path) was possible to be an incorrect.
Therefore, please do not specify the source point of the generated clock skips the generation position of the
other generated clock. This problem has been fixed in the PrimeTime 2015.12-SP1.

◼ Sample circuit configuration and constraints

create_clock -name CLK -period 10 [get_ports clk]

create_generated_clock -name GCK0 -source [get_ports clk] [get_pins I3/Y] -div 1
create_generated_clock -name GCK1 -source [get_ports clk] [get_pins F1/Q] -div 2

GCK0
GCK1
GCK1
F2
GCK0
F1
GCK0 clock source I3 I4
latency
clk
CLK GCK1 clock source
latency

GCA/PTC MESSAGE
UDEF_JumpGclkForSourcePin
Multiple generated clocks Gclk2 and Gclk3 based on same master clock Mclk are connected serially and
it's based on the same source point. The latter stage of the generated clock should be based on the previous
stage of the generated clock.

Action

Please change the specified point of the generated clock "GCLK1".

As follows, change the specified point from the port "clk" to the pin “I3/Y”.
before correction：create_generated_clock -name GCK1 -source [get_ports clk] [get_pins F1/Q] -div 2
after correction ：create_generated_clock -name GCK1 -source [get_pins I3/Y] [get_pins F1/Q] -div 2

Limitations

1) This rule does not consider other timing constraints. So, it verifies false path between clocks specified in
set_false_path command.

2) This rule is verify physical connection there is no path at the source point of the master clock and the
specified generation portion of the generated clock.
 Page 131/257
3) This rule does not take into account the contradiction of -source option and -master options.
Therefore, to verify even if there is a difference “-source <point>” and “-master <clock-name>”.

◼ Confirmation method
amaYou can check whether the message is a pseudo error corresponding to restrictions (1) and (2) using the
following procedure.

Use the analyze_paths command to check for physical paths.

If there is no physical path, treat this error as a pseudo error.
gca_shell> analyze_paths ¥
-from [get_clocks <MClk (master clock name)>] ¥
-through [get_pins <Gen2 or Gen3 clock specification points>] ¥
-through [get_pins <Gen2 or Gen3 clock specification points>] ¥
-traverse_disabled ¥
-max_endpoints 1

In the following example, there is no physical path, so it can be determined as a false error.
****************************************
No Valid Paths. ⇐ No path. In this case, it can be judged as a pseudo error.
 Page 132/257

R0137 Defining constraints in pair (set_clock_latency)

Severity RTL Layout I/F STA IP
n/a Warning Warning Error/Info
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC CNL_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Although different specifications can be defined for pairs of min and max conditions, early and late conditions,
and setup and hold conditions, if only one item of a pair is defined, the tool may not be able to perform
necessary timing analysis because it does not take the the undefined condition into consideration. This rule is
therefore used to check whether the constraints supposed to be paired are defined.

Target options:
⚫ -early / -late
⚫ -rise / -fall
⚫ -min / -max
⚫ Valid combinations of the above

◼ Sample circuit configuration and constraints

1. Only -early of set_clock_latency is valid and -late is invalid

set_clock_latency -source -early 5.432 [get_clocks {CLK}]
# set_clock_latency -source -late 6.789 [get_clocks {CLK}] ←Setting is missing.

GCA Message

CNL_0005 :
All register clock pins in the fanout of 'object' have no clock latency for clock 'clock'.

Action

Check whether it is necessary to define the missing conditions for the latency for which the error is reported.
If a definition proves necessary as the result of the check, modify the SDC.

GCA Limitations

CNL_0005 detects the cases in which no network latency is set or it is set to 0.

2. Only -setup of set_clock_uncertainty is valid and -hold is invalid
 Page 133/257

R0138 Defining constraints in pair (set_clock_uncertainty)

Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UNC_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

Although different specifications can be defined for pairs of min and max conditions, early and late conditions,
and setup and hold conditions, if only one item of a pair is defined, the tool may not be able to perform
necessary timing analysis because it does not take the the undefined condition into consideration. This rule is
therefore used to check whether the constraints supposed to be paired are defined.

Target options:
⚫ -hold / -setup
⚫ -rise / -fall
⚫ Valid combinations of the above

◼ Sample circuit configuration and constraints

Only -setup of set_clock_uncertainty is valid and -hold is invalid

set_clock_uncertainty -setup 0.2 -from [get_clocks CLK1] -to [get_clocks CLK2]

# set_clock_uncertainty -hold 0.2 -from [get_clocks CLK1] -to [get_clocks CLK2]

GCA Message

UNC_0003 :
Clock uncertainty is incomplete or incorrect between two interacting clocks 'clock1' and 'clock2'

Action

Check whether it is necessary to define the missing conditions for the uncertainty for which the error is reported.
If a definition proves necessary as the result of the check, modify the SDC.

GCA Limitations

UNC_0003 checks not only for missing uncertainty between clocks but also the magnitude relation between
setup and hold; it detects the case in which the setup side value > hold side value.

・UNC_0003 also detects when set_clock_uncertainty is not set or the set value is 0.
・Check specification change of UNC_0003 is changed in the rule set (RenesasCommonRule_IP/Layout/STA).

<Settings> If you are using a ruleset, you do not need to set this variable.
set_rule_property suppress_violations_for_incorrect_uncertainty true UNC_0003

<Specification change> In addition to the normal check, the default (when the above variable is false) also
checks the set_clock_uncertainty setup and hold relationship (if the value on the setup side is greater than the
value on the hold side). This rule check is excluded when using rule sets.
 Page 134/257

R0139 Generated Clocks from the same master clock must be declared exclusive
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to detect excessive constraints on the set_clock_groups command.
As a rule of SDC, clocks generated from the same master clock are treated as exclusive (meaning that all
clocks other than their own clocks or clocks specified in the same group are excluded).
Therefore, it is possible to delete the constraints for which this rule is output.

◼ Sample circuit configuration and constraints

Cases in which clocks generated from the same master clock are set in an exclusive
relationship

Clock generation point of clock GCLK1

Exclusive relationship as SDC rules

Clock generation point of clock MCLK

Clock generation point of clock GCLK2

## test.sdc. in this case violation.

create_clock -name MCLK -period 10 -waveform {0 5} [get_ports CLK]
create_generated_clock -name GCLK1 -source [get_ports CLK] -divide_by 2 [get_pins DFF1/Q]
create_generated_clock -name GCLK2 -source [get_ports CLK] -divide_by 2 [get_pins DFF2/Q]
set_clock_groups -name CG1 -asynchronous -group {GCLK1} -group {GCLK2}

GCA/PTC MESSAGE
CGR_0001:
Clocks generated from the same master clock master_clock are declared as asynchronous.

◼ Action
In the above example, “set_clock_groups -name CG1 -asynchronous -group {GCLK1} -group {GCLK2}” is
deleted, or multiple generated clocks are not generated from the same master clock MCLK.
 Page 135/257
R0140 The definition of clock exclusive relationship between parent and child clocks should be
eliminated due to over-setting.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0002
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to detect illegal restrictions on the set_clock_groups command.
As an SDC rule, you cannot set an exclusive relationship between clocks in a parent-child relationship.
Therefore, it is necessary to review the constraints for which this rule is output.
◼ Sample circuit configuration and constraints

Cases in which an exclusive relationship is set between parent-child clocks

Clock generation point of clock GCLK1

Clock generation point of clock MCLK Exclusive relationship as SDC rules

## test.sdc. in this case violation.

create_clock -name MCLK -period 10 -waveform {0 5} [get_ports CLK]
create_generated_clock -name GCLK1 -source [get_ports CLK] -divide_by 2 [get_pins DFF1/Q]
set_clock_groups -name CG1 -asynchronous -group {MCLK} -group {GCLK1}

In this example, the generated clock GCLK1 is generated from the master clock MCLK. In such a case,
MCLK and GCLK1 have a parent-child relationship and are detected by this rule.
GCA/PTC MESSAGE
CGR_0002:
Clock clock1 is generated directly or indirectly from the clock clock2. They should not be declared as
asynchronous.

◼ Action
In the above example, “set_clock_groups -name CG1 -asynchronous -group {GCLK1} -group {GCLK2}” is
deleted.
 Page 136/257
R0141 Set up an exclusive relationship between non-interfering clocks
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to suggest a recommended setting for the set_clock_groups command as an SDC
description.
For clocks that do not interfere with each other between clocks, this should be stated as an exclusive
relationship. In addition, as a rule of SDC description, it is necessary to set an exclusive relationship for each
generated clock generated from each master clock with a master clock exclusive relationship because it does
not inherit the exclusive relationship.
Therefore, consider setting an exclusive relationship between the clocks detected by this rule.
◼ Sample circuit configuration and constraints

Cases where there is a shortage of exclusive relationship settings

Clock generation point of clock GCLK1

If the master clocks are in an exclusive relationship, the child clocks

Clock generation point of clock MCLK should also be in an exclusive relationship.

Should be an exclusive relationship

Clock generation point of clock GCLK2

Clock generation point of clock MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK2]
create_generated_clock -name GCLK1 -source [get_ports CLK1] -divide_by 2 [get_pins DFF1/Q]
create_generated_clock -name GCLK2 -source [get_ports CLK2] -divide_by 2 [get_pins DFF2/Q]
set_clock_groups -name CG1 -asynchronous -group {MCLK1} -group {MCLK2}
In this example, clocks MCLK1 and MCLK2 do not interfere with each other. In this case, the clock MCLK1
and MCLK2 should be treated as an exclusive relationship. As described above, this exclusive relationship
setting is not carried over between the generated clocks and must be set separately. Therefore, it is
necessary to set an exclusive relationship between clocks GCLK1 and GCLK2 as well.

GCA/PTC MESSAGE
CGR_0004 :
Clock clock1 and clock clock2 are defined asynchronous with each other. There are clocks generated
directly or indirectly from these clocks which are not defined as asynchronous.

◼ Action
In the above example, set_clock_groups -name CG1 -asynchronous -group {clk1 clk3} -group {clk2 clk4}
 Page 137/257

R0142 Confirm that there is no shortage in the setting of exclusive relationship between clocks
R0142
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The clock reported by this rule has one or more clocks that have an exclusive relationship with that clock.
Therefore, an exclusive relationship must be set for one or more exclusive relationship clocks.
Therefore, consider adding an exclusive relationship to the clock from which this rule is output.

◼ Sample circuit configuration and constraints

Cases where no exclusive relationship is set between clocks that do not interfere with each
other

Clock generation point of clock Clock generation point of clock Clock generation point of clock
MCLK1 MCLK2 MCLK3

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK2]
create_clock -name MCLK3 -period 30 -waveform {0 15} [get_ports CLK3]
set_clock_groups -name CG1 -asynchronous -group {MCLK1} -group {MCLK2}

In this example, MCLK1 and MCLK2 are in an exclusive relationship, but there is no definition for MCLK3.
Since it is necessary to set an exclusive relationship with MCLK1 or MCLK2 for MCLK3, it is detected by this
rule.

GCA/PTC MESSAGE
CGR_0004 :
clock clock1 is missing an asynchronous definition with at least one clock in each of the following
asynchronous clock pairs.

◼ Action
In the above example, add an exclusive relationship definition for clock MCLK3.
set_clock_groups -asynchronous -group {MCLK1 MCLK2} -group {MCLK3}
 Page 138/257
R0143 Confirm that there is no error in using the set_clock_groups option.
R0143
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to detect incorrect usage of the set_clock_groups command options. Use of the -
physically_exclusive option is inappropriate because the clocks of constraints verified by this rule are not
physically exclusive.
Therefore, it is necessary to review the constraint options output by this rule.
◼ Sample circuit configuration and constraints

Cases where -physically_exclusive is used between clocks that are not physically exclusive

Clock generation point of clock MCLK1

Clock generation point of clock MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK2]
create_generated_clock -name GCLK2 -combinational [get_pins MUX/Y] -source [get_ports CLK1]
set_clock_groups -name CG1 -physically_exclusive -group {MCLK1} -group {GCLK2}

In this example, the generated clock GCLK2 is generated from the clock MCLK1. In this case, because
there is a physical relationship, it is wrong to declare MCLK1 and GCLK2 as “physically exclusive” (-
physically_exclusive).

GCA/PTC MESSAGE
CGR_0005 :
Clock clock1 is generated directly or indirectly from the clock clock2. They should not be declared as
physically exclusive.

◼ Action
In the above example, delete the following clock group
set_clock_groups -name CG1 -physically_exclusive -group {MCLK1} -group {GCLK2}
Or, check whether the master clock/derived clock definition relationship is correct.
 Page 139/257
R0144 Use the -physically_exclusive option between clocks that do not physically interfere
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0006
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to detect a shortage of set_clock_groups commands.
Must be defined as being physically exclusive (-physically_exclusive) to between physically exclusive clocks
There is. Therefore, it is necessary to add or review the constraints between the clocks that output this rule.
◼ Sample circuit configuration and constraints

Cases in which parent clocks are in an exclusive relationship but child clocks are not in an
exclusive relationship setting

Clock generation point of clock GCLK1

If the master clocks are in an exclusive relationship, the child clocks

Clock generation point of clock MCLK1 should also be in an exclusive relationship.

Should be an exclusive relationship

Clock generation point of clock GCLK2

Clock generation point of clock MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK2]
create_generated_clock -name GCLK1 -source [get_ports CLK1] -divide_by 2 [get_pins DFF1/Q]
create_generated_clock -name GCLK2 -source [get_ports CLK2] -divide_by 2 [get_pins DFF2/Q]
set_clock_groups -name CG1 -physically_exclusive -group {MCLK1} -group {MCLK2}

In this example, set_clock_groups is defined between master clocks MCLK1 and MCLK2, but
set_clock_groups is not defined between its derived clocks GCLK1 and GCLK2, so this rule detects them.

GCA/PTC MESSAGE
CGR_0006 :
Clock clock1 and clock clock2 are defined physically exclusive with each other. There are clocks
generated from these clocks which are not defined as physically exclusive.

◼ Action
In the above example, use
“set_clock_groups -name CG1 –physically_exclusive -group {MCLK1 GCLK1} -group {MCLK2 GCLK2}“
and -physically_exclusive option
 Page 140/257
R0145 Confirm that the set_clock_groups command is set between clocks of the same
definition location.
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0007
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The purpose of this rule is to detect a shortage of set_clock_groups commands. As a rule of SDC, when
multiple clocks are defined on the same port/pin, or is physically exclusive (-physically_exlusive) or exclusive
relationship (-asynchronous) to the reference clock of set_input_delay/set_output_delay command Must be
defined.
Therefore, this rule requires additional consideration of the set_clock_groups command for the clock.
◼ Sample circuit configuration and constraints

Cases where multiple clocks are defined for the same port

Clock generation point of clock MCLK1 and

MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK1] -add

In this example, multiple clocks are defined for the same port. In such a case, the clocks MCLK1 and MCLK2
do not operate simultaneously on the actual chip. Therefore, it must be physically exclusive of each other, so
it is detected by this rule.
GCA/PTC MESSAGE
CGR_0007 :
Multiple clocks or a clock with either set_input_delay or set_output_delay are defined at pin/port pin_port.
In both cases, (the defined multiple clocks or a defined clock with the reference clock), these clocks should
be defined as exclusive/asynchronous.

◼ Action
In the above example, add the exclusive relationship setting as physically exclusive.
set_clock_groups -name CG1 -physically_exclusive -group {MCLK1} -group {MCLK2}
 Page 141/257
R0146 Use the set_clock_groups command to set the false value between clocks
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0008
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The purpose of this rule is to detect candidates that replace the false definition method between clocks from
the set_false_path command to the set_clock_groups command. Consider reviewing the restrictions that
output this rule.

◼ Sample circuit configuration and constraints

Cases in which false between clocks is set with the set_false_path command

Clock generation point of clock GCLK1

Clock generation point of clock MCLK1

Should be an exclusive relationship

Clock generation point of clock GCLK2

Clock generation point of clock MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1]
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK2]
set_false_path -from [get_clocks MCLK1] -to [get_clocks MCLK2]
set_false_path -from [get_clocks MCLK2 -to [get_clocks MCLK1]
In this example, the false setting between clocks is set using the set_false_path command between master
clocks. This setting is correct. As described above, the clock MCLK1 and MCLK2 clocks can be replaced with
the recommended setting set_clock_groups command.

GCA/PTC MESSAGE
CGR_0008:
Multiple clocks defined at pin/port pin_port have false path set between them. For accurate signal integrity
results use the set_clock_groups command.

◼ Action
In the above example, replace set_false_path with the set_clock_groups command.
set_clock_groups -name CG1 -physically_exclusive -group {MCLK1} -group {MCLK2}
 Page 142/257

R0147 STA tool accuracy is difficult to guarantee

Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CGR_0009
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
There is a valid timing between the detected clocks, but the common base period (the least common multiple
of the period between the two clocks) exceeds the clock period. Even with such a valid timing path, the STA
tool detects the problem during SDC verification because it is out of the support (guarantee) range when the
common base period exceeds the tool threshold.

The threshold values are as follows.

set_rule_property max_period_multiplier 101 ;# default 101.
set_rule_property min_period_multiplier 1000 ;# default 1000.
set_rule_property skip_clocks_with_MCP true [get_rules CGR_0009]
;# Not issue error when setting MCP inter-clocks

◼ Sample circuit configuration and constraints

When an exclusive relationship is set between parent-child clocks

Clock generation point of clock MCLK1

Clock generation point of clock MCLK2

## test.sdc. in this case violation.

create_clock -name VCLK1 -period 3.1
create_clock -name VCLK1_mod -period 11.07
create_clock -name CLK1 -period 3.1 [get_ports CLK1] -add
create_clock -name CLK2 -period 6.2 [get_ports CLK2] -add
create_clock -name CLK1_mod -period 11.07 [get_ports CLK1] -add
create_clock -name CLK2_mod -period 22.14 [get_ports CLK2] -add
set_clock_groups -group {CLK1 CLK2} -group {CLK1_mod CLK2_mod} -physically_exclusive
set_input_delay 1.23 -clock VCLK1 -add [get_ports DATA]
set_input_delay 4.23 -clock VCLK1_test -add [get_ports DATA]

In this example, one SDC mode consists of function 1 “clocks VCLK1, CLK1, CLK2” and function 2 “clocks
VCLK1_test, CLK1_test, CLK2_test”. However, since there is no definition of set_clock_groups, it is detected
by this rule.
GCA/PTC MESSAGE
CGR_0009:
Clocks clock1 and clock2 have valid timing paths between them, but their common base period is more
than the limit times the clock period.

“Valid timing paths” in the message does not matter whether the clock is a virtual clock or a real clock. In
addition, regarding data path, it is physically present and set_false_path is not specified.
 Page 143/257
◼ Action

・For the above example, add the following settings:

set_clock_groups -group {CLK1 CLK2 VCLK1} ¥
-group {CLK1_mod CLK2_mod VCLK1_mod} ¥
-physically_exclusive

・If Multicycle path is set between two clocks and you want to exclude this rule from checking, set the following
variable to true. Between clocks CGR_0009 violation is no longer output between clocks for which Multicycle
path is set.

set_rule_property skip_clocks_with_MCP true CGR_0009 ;# default: false

・ The equivalent message in PT of CGR_0009 of PTC is PTE-053. The above restriction relaxation by PTC
is effective only by PTC. Therefore, CGR_0009 is not reported by PTC when the above restrictions are relaxed,
but PTE-053 may be reported by PT.

Warning: For computing a common base period for a number of clocks PrimeTime limits the waveform
expansion of the smallest period to be no more than 1000 times and the waveform expansion of the largest
period to be no more than 101 times. PrimeTime has computed a common base period bounded by these
limits. (PTE-053)
 Page 144/257
R0148 Attention to the multiple specification order of the -through option of the timing
exception command.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Attention
With the -through option of the timing exception command, you can specify all paths through one or more
specific pins, ports, or instances. There are a method of specifying passing points in order and a method of
specifying passing through one of the specified points, and there is also a specifying method that combines
these. When using -through, be careful of these specification methods.

◼ Sample circuit configuration and constraints

How to specify the points to pass in order

It specifies a path with F1/CLK as the start point, B1 and C1 (in this order), and F2/DATA as the end point.
set_false_path -from [get_pins {F1/CLK}] -to [get_pins {F2/DATA}] -through B1 -through C1

Specification method that passes through one of the specified points

The path is specified with F1/CLK as the start point, B1 or C1 and F2/DATA as the end point.
set_false_path -from [get_pins {F1/CLK}] -to [get_pins {F2/DATA}] -through { B1 C1 }

How to specify in combination

The path that uses F1/CLK as the start point, passes B1 or B2, then passes C1 or C2, and uses F2/DATA as
the end point is specified.

set_false_path -from [get_pins {F1/CLK}] -through {B1 B2} -through {C1 C2} -to [get_pins {F2/DATA}]
 Page 145/257
R0150 Do not mix ideal clock and propagate clock (after CTS execution)
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC CLK_0019
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
All clocks should be treated as "ideal clocks" before running CTS, and all clocks should be treated as
"propagated clocks" after running CTS. In this rule CLK_0019, check that the ideal clock and propagated clock
are mixed.

◼ Sample circuit configuration and constraints

When only some clocks are specified in the set_propagated_clock command

create_clock -name CK1 -period 4 -waveform { 1 2 } [get_ports {CLK1}]
create_clock -name CK2 -period 6 -waveform { 0 3 } [get_ports {CLK2}]
set_propagated_clock [get_clocks {CLK1}]

GCA/PTC MESSAGE

CLK_0019 ：
Design has both propagated and ideal non-virtual clocks.

◼ Action
Please set all clocks "propergeted cloks" or "ideal cloks"

(A) After CTS (If CTS is executed, set all clocks as propagate)
create_clock -name CK1 -period 4 -waveform { 1 2 } [get_ports {CLK1}]
create_clock -name CK2 -period 6 -waveform { 0 3 } [get_ports {CLK2}]
set_propagated_clock [all_clocks]

(B) Before CTS: (If CTS is not running, set all clocks to ideal)
create_clock -name CK1 -period 4 -waveform { 1 2 } [get_ports {CLK1}]
create_clock -name CK2 -period 6 -waveform { 0 3 } [get_ports {CLK2}]
#set_propagated_clock [get_clocks {CLK1}]

Confirmation method

<Violation>
Design has both propagated and ideal non-virtual clocks.

<Constraint>
* Omitted
create_clock -name rclk -period 4 [get_ports CLK1]
create_clock -name clk -period 6 [get_ports CLK2]
create_clock -name gclk7 -period 8 [get_ports CLK2]
set_propagated_clock [get_clocks {rclk clk}]

A list of “ideal clock” and “propagated clock” is displayed in “Violation Details” of “ViolationBrower”.
Please empty either clock list.
 Page 146/257

GCA/PTC LIMITATIONS

・CLK_0019 doesn’t check the clock and virtual clock defined for the output terminal. The virtual clock has no
source and doesn’t affect the registers in the design. Therefore, the virtual clock cannot be propagated, and if
set_propagated_clock is applied to the virtual clock, UIC-025 is reported in the log when reading SDC.

Warning: Virtual clock '<clock-name>' cannot be made propagated. (UIC-025)

・V02.01.05 does not check CLK_0019 (scheduled to be introduced in the next version). If necessary, the
designer can switch between enabling and disabling the settings below.

〈Setting example〉
ptc_shell> enable_rule CLK_0019
ptc_shell> set_rule_severity error CLK_0019
ptc_shell> analyze_design
 Page 147/257

S0002 Confirm that the pin specified as ClockSense does not transition
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert SDC_SENSE_ANALYSIS
(Dynamic Simulation）

◼ Description
Confirm that there is no Toggle (signal change) on the logic simulation / emulation of the pin with the
ClockSense constraint. If there is Toggle on functional simulation/emulation, check if it is as designed. Note
that the SVA Flow utility is used for this verification. Please refer to the procedure manual (scheduled to be
issued in the second half of 2019) for usage.

When multiple clocks reach the specified pin of ClockSense

Clock generation point of clock MCLK1
and MCLK2

## test.sdc. in this case violation.

create_clock -name MCLK1 -period 10 -waveform {0 5} [get_ports CLK1] -add
create_clock -name MCLK2 -period 20 -waveform {0 10} [get_ports CLK1] -add
set_clock_sense -stop_propagation [get_pins MUX/D0] -clock [get_clocks MCLK1]

The above set_clock_sense is intended to stop clock propagation of clock MCLK1 on STA at pin MUX/D0.
Confirm that there is no signal change at the specified pin on the logic simulation/emulation.

SIM/HWE result

SIM(VCS)

Toggle Toggle 1->0 Toggle 0->1

SENSE_0 Yes Yes Yes

HWE(Palladium)

[SENSE TOGGLE COUNT] Toggle count (max = 15)

[SENSE TOGGLE COUNT] Signal : Rise count : Fall count
[SENSE TOGGLE COUNT] ----------------------------------------------
[SENSE TOGGLE COUNT] [SENSE_0] MUX.D0: 15 : 15
[SENSE TOGGLE COUNT] ----------------------------------------------

◼ Action
The Toggle coverage at the specified pin of the ClockSense constraint is expected to have no signal change
on logic simulation/emulation. In the above example, there is a signal change (with Toggle), so it can be seen
that the STA differs from the verification environment on the functional simulation/emulation. Therefore, check
whether the selection of the reset signal is appropriate in the functional simulation/emulation environment or
whether the file to be input to the SIM/HWE environment is appropriate, and correct it accordingly. Similarly,
check if there are any shortages in the clock specified in the ClockSense constraint, and correct accordingly.
 Page 148/257
Limitations

・There may be cases where the design intent cannot be determined based on the tool results alone. Please
check the SENSE setting information table to see if it is as designed.
 Page 149/257
S0003 Confirm that the settings specified in the derived clock (items that can be checked with SVA)
match the actual operation.
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert <Clock Name>___<Additional information on the
(Dynamic Simulation） clock>___<checker_type>

◼ Description
The SVA of this rule verifies whether the waveform of the point defining the generaeted clock actually matches
the waveform defined by the timing constraint (create_generated_clock) on the functional simulation/emulation.
If the logic simulation/emulation does not match (FAIL), the RESET signal at the time of verification is
appropriate, the correspondence between the logic simulation/emulation environment and the SVA checker is
correct, or the specified point and division/multiplication of the generaeted clock are correct Review is required.

◼ Sample circuit configuration and constraints

When the relationship between the master clock and the derived clock is different from the SDC

Delay factor

## test.sdc.
create_clock -name CLK_100M -period 10 -waveform {0 5 } [get_ports CLK1]
create_generated_clock -name CLK_100M_DIV_2 -divide_by 2 -source [get_ports CLK1] [get_pins DFF1/Q]

The above create_generated_clock generates a clock divided by 2 of the master clock CLK_100M. However,
if there is a factor that hinders signal propagation from the master clock to the designated point of the
genereated clock on the circuit, an unintended genereated clock may be generated. Therefore, for this
genereated clock, use the following SVA to check whether the genereated clock point is the intended one.

・Properties :
With this property, it is possible to confirm that the point where the derived clock is specified is divided by 2
with respect to the master clock after one cycle of the startup of the evaluation clock (CLK), excluding the non-
evaluation period (RST) .

property p_divided_by_n(MASTER_CLK, GENERATED_CLK, RESET, n);

@(posedge MASTER_CLK) disable iff (RESET) ##1 $rose(GENERATED_CLK)
|=> !$rose(GENERATED_CLK)[*n-1] ##1 $rose(GENERATED_CLK);
endproperty
 Page 150/257
・SVA (assertion) converted from SDC
This SVA is got by applying actual clock pins and specified pins to the above properties.
// divide_byN>=2, no-invert
`define CHECK_DIVIDED_BY(ID, MASTER_CLK, GENERATED_CLK, RESET, N) \
c_``ID``_divided_by_``N: cover property(p_divided_by_n(MASTER_CLK, GENERATED_CLK, RESET, N)); \
a_``ID``_divided_by_``N``_or_more: assert property(p_divided_by_n_or_more(MASTER_CLK, GENERATED_CLK, RESET, N)); \
a_``ID``_not_multiplied_pe: assert property(p_stable_on_posedge(GENERATED_CLK, MASTER_CLK, RESET)); \
a_``ID``_not_multiplied_ne: assert property(p_stable_on_negedge(GENERATED_CLK, MASTER_CLK, RESET)); \
a_``ID``_not_same_pnp: assert property(p_not_same_freq_pnp(GENERATED_CLK, MASTER_CLK, RESET)); \
a_``ID``_not_same_npn: assert property(p_not_same_freq_npn(GENERATED_CLK, MASTER_CLK, RESET));
//#GEN_1 と`CHK_DISABLE_FP、
`TOP_INST For clock: CLK_100M_DIV_2 Line: 7は
`CYCLE define
File: マクロを使い、SIM/HWE 実行前に定義してください。
/<SDC-PATH>/test.sdc
`CHECK_DIVIDED_BY(
・`TOP_INST ： Netlist トップ階層名
CLK_100M_DIV_2,
・`CHK_DISABLE_FP
`TOP_INST.CLK1, ：FP チェック除外条件であるリセット信号を設定してください。
`TOP_INST.DFF1.Q,
・`CYCLE：ユーザ指定の任意の期間(指定ピンが遷移しない期間)を設定してください。
`CHK_DISABLE_GC,
2
);

`TOP_INST and `CHK_DISABLE_CG should be defined before SIM/HWE execution using define
macro.
・`TOP_INST ： Netlist top hierarchy name
・`CHK_DISABLE_CG ：Set a reset signal that is a condition for excluding generated clocks.

SIM/HWE result
SIM(VCS)

"tb.test.GCM__0.a_ CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_multiplied_pe", 44 attempts, 40 successes, 0 failures, 1

incompletes
"tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_multiplied_ne", 44 attempts, 37 successes, 0 failures, 1
incompletes
"tb.test.GCM__0.c_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_divided_by_2", 106 attempts, 37 matches, 0 mismatches, 2
incompletes
"tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_divided_by_2_or_more", 106 attempts, 40 successes, 0 failures,
1 incompletes
"tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_same_pnp", 106 attempts, 81 successes, 0 failures, 1
incompletes
"tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_same_npn", 106 attempts, 0 successes, 0 failures, 1
incompletes

HWE(Palladium)

Checked? Finish Failed Assertion Name

44 40 0 tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_multiplied_pe
44 37 0 tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_multiplied_ne
106 37 0 tb.test.GCM__0.c_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_divided_by_2
106 40 0 tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_divided_by_2_or_more
106 81 0 tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_same_pnp
106 0 0 tb.test.GCM__0.a_CLK_100M_DIV_2___div2___CHECK_DIVIDED_BY_not_same_npn
 Page 151/257
◼ Action
The SVA of the generated clock is expected to be the specified division/multiplication ratio at the designated
point of the generated clock specified by the SDC with respect to the master clock. There is a period that is
not the expected operation because there is a Fail judgment more than once. Therefore, check whether the
RESET signal at the time of verification is appropriate, whether the logical simulation/emulation environment
and the SVA checker are correct, and check that the specified point and division / multiplication of the
generated clock are correct.

Limitations

・Constraints that include -edges_shift option are outside the scope of this rule's SVA.
-edges_shift option is outside the scope of this rule's SVA. Please confirm the validity of SDC by rule check
and ConCert GUI.
 Page 152/257

7.4. Clock Gating

7.4.1. set_clock_gating_check

The set_clock_gating_check command is used to set setup time and hold time values for checking timing of
clock gating cells. Checking of the setup time is used to make sure that the control data signal is stable
before the clock is activated in a combination circuit to which the clock signal propagates. On the other hand,
checking of the hold time is used to make sure that the control data signal is stable after the clock is active.

◆ Recommended usage
The following description method is recommended for setting the set_clock_gating_check command.
 Use simple gates (such as AND, NAND, OR, and NOR) on the clock line as definition points.
 When specifying elements other than simple gates as definition points, indicate the timing check polarity
by using the -high or -low option.

◆ Recommended example of command description

Example for setting setup time and hold time for checking clock gating

set_clock_gating_check -setup 1.0 -hold 1.0 [get_cells I1]

Example for setting polarity for checking clock gating

set_clock_gating_check -setup 1.0 -hold 1.0 -low [get_cells I1]

 Page 153/257
◆ Notice
 Do not specify any clock or port as an object. If a clock is specified as an object, all clock gating cells
activated by the clock are targeted, which may lead to unintended verification.
 It is mandatory to specify an object. If no object is specified, all clock gating cells in the design are targeted,
which may lead to unintended verification.
 Use the -rise or -fall option to indicate whether the setup time and hold time values should be applied to
the rising or falling waveform. If neither the -rise nor -fall option is specified, the setup time and hold time
values are applied to both rising and falling waveforms.
 If polarity (-rise/-fall) is set for cells (such as selector cells and composite cells other than AND, NAND,
OR, and NOR) whose polarity cannot be determined by the tool and the polarity is different from that
recognized by the tool, the user setting takes precedence.

◆ Supplement
The following describes differences depending on whether the set_clock_gating_check setting is present.

Timing checking when set_clock_gating_check is not used

The following shows the result of checking clock gating timing without the set_clock_gating_check setting.

・ Since cell I1 is an AND cell and the tool can automatically determine the polarity of the clock gating checking,
the checking is enabled even if set_clock_gating_check is not specified. For an AND cell, checking is to
make sure that the control signal remains unchanged while the clock is at a high level, and the setup time
and hold time are the default value of 0.0.
・ Since cell I2 is a simple logic cell (OR), checking of the clock gating timing is automatically performed. For
an OR cell, checking is to make sure that the control signal remains unchanged while the clock is at a low
level.
・ Since cell I3 is an XOR cell and the tool cannot automatically determine the polarity of the clock gating
timing checking, the tool does not perform checking automatically.
 Page 154/257
Setting clock gating setup and hold constraint values
A default constraint value of 0.0 is set for clock gating setup and hold time. To change this value to a specific
value, use the -setup and -hold options of the set_clock_gating_check command as shown below.

Setting the polarity of clock gating timing checking

For cells (such as composite logic cells, multiplexer, and logic cells other than simple logic cells AND, NAND,
OR, and NOR) for which the polarity of clock gating timing checking cannot be determined by the tool, the
polarity must be specified using the -high and -low options of the set_clock_gating_check command.
When checking timing as in the case of clock gating with AND and NAND cells, use the -high option as shown
below.

When checking timing as in the case of clock gating with OR and NOR cells, use the -low option as shown
below.

The polarity of clock gating cells automatically determined by the PrimeTime can be changed by using the -
high and -low options. However, if the automatically determined polarity differs from the polarity specified by
the -high and -low options, the PrimeTime outputs the following message and the polarity specified by the -
high and -low options is used for the analysis.
 Page 155/257
Setting clock gating setup and hold time for each transition of control signal
To set the constraint value of clock gating timing checking for each transition (rising and falling) of a control
signal, use the -rise and -fall options.
・ When neither -rise nor -fall option is specified, the same set of setup time and hold time values is applied
to both transitions.
・ When both -rise and -fall options are specified, the respective sets of setup time and hold time values are
applied to both transitions.
・ When only the -rise option is specified, the default value 0.0 is set for falling.
・ When only the -fall option is specified, the default value 0.0 is set for rising.

Specifying objects to which the set_clock_gating_check command is to be applied

object_list can be used to specify the range of objects to which the set_clock_gating_check command is
applicable. Clocks, pins, and instance cells can be specified with object_list. If object_list is omitted, the
command is applied to the current design (entire design).

Example where object_list is omitted

The following figure shows a setting with object_list omitted. Since this setting is provided for the current design,
this setting applies to all clock gating cells with fixed timing check polarity. This setting is not effective for clock
gating cells whose timing setting polarity cannot be automatically recognized.

Example where a clock is specified

The following figure shows an example where set_clock_gating_check is set for a clock. This setting applies
to all clock gating cells driven by that clock.
 Page 156/257
Example where a pin of instance cell on the clock line is specified
In the following figure, set_clock_gating_check is specified for the pin of an instance cell on the clock line. In
this case, the clock gating cells existing within the transitional fan-out of the pin are applicable.

Example where clock gating cell is specified

In the following figure, set_clock_gating_check is set for a clock gating cell. In this case, all gate pins of the
specified instance cell are applicable. Furthermore, the clock gating cells existing within the transitional fan-
out of the specified instance cell are applicable.

Example where the gate pin of clock gating cell is specified

In the following figure, set_clock_gating_check is set for the gate pin of a clock gating cell. In this case, the
specified pin and the clock gating cells existing within the transitional fan-out of the specified pin are applicable.
 Page 157/257
7.4.2. Check rules

R0061 Specification for cells except simple function cell like AND, NAND, OR or NOR, etc
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC CLK_0035
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The complex cells such as XOR, XNOR and MUX, which tool cannot automatically distinguished their polarity
either high or low for clock gating timing check, are needed to specify polarity with ‘-high’ or ‘-low’ option. This
rule reports the instance of complex cells even if with or without polarity, when the set_clock_gating_check is
specified for cell except simple function cell such as AND, NOR, etc.

◼ Sample circuit configuration and constraints

1. ‘-high’ or ‘-low’ option is not specified

create_clock –name CLK –period 10 [get_ports CLK]

set_clock_gating_check -setup 1.0 -hold 2.0 [get_pins X1/A]

X1
D Q
CLK B
DATA A CK

specify exclusive OR

GCA Message

CLK_0035 :
2014.12-SP3-1 previous :
No clock-gating check inferred for the instance: cell clock pin: clk_pin enable pin: enable_pin lib cell:
lib_cell

2015.06 and later : Reports the clock name.

No clock-gating check inferred for the instance: cell clock pin: clk_pin enable pin: enable_pin lib cell:
lib_cell clk name: clock

In PTC.2017.12-SP3-3-VAL-20190404, “clock name + blank” in “clk name: clock” was deleted, and only “clock
name” was added.

2. ‘set_clock_gating_check’ option is not specified.

create_clock –name CLK –period 10 [get_ports CLK]

X1
D Q
CLK B
DATA A CK

not set the command : set_clock_gating_check

GCA Message

CLK_0035 :
2014.12-SP3-1 previous :
 Page 158/257
No clock-gating check inferred for the instance: cell clock pin: clk_pin enable pin: enable_pin lib cell:
lib_cell

2015.06 and later : Reports the clock name.

No clock-gating check inferred for the instance: cell clock pin: clk_pin enable pin: enable_pin lib cell:
lib_cell clk name: clock

Confirmation method

<Violation>
No clock-gating check inferred for the instance: 'MUX01' clock pin: 'MUX01/I0' enable pin: 'MUX01/S' lib cell:
'library_name/library_cell_name' clk name: 'CK1 '

<Constraint>
create_clock -name CK1 -period 10 -waveform {0 5} [get_ports CLK1]

<Debug method>

For the reported clock, use analyze_clock_networks to check the clock propagation path.
As described in “Description”, the multiplexer cannot set the polarity of the clock gating timing check
automatically, so set_clock_gating_check should be set.

ptc_shell> analyze_clock_networks -from [get_clocks CK1] -style full -end_types {register port clock_source}
-max_endpoints 1
****************************************
Clock Sense Abbreviations:
P - positive
Clock Network End Type Abbreviations:
REG - register

Full report for clock: CK1

Branch 0:
Branch
Level Info Sense Notes Port/Pin
--------------------------------------------------------------------------------
0 P source CLK1 (in)
1 P MUX01/I0 (library_cell_name)
2 P MUX01/Z (library_cell_name)
3 P REG FF04/CP (library_cell_name)

You can also check the GUI's “ViolationBrowser”.

Click Schematic to display Schematic, and click the clock name in Violation Details to check the corresponding
clock definition.
 Page 159/257

<Addition >

You can also display clock information by executing the above analze_clock_networks on the “Console” of the
GUI.

When you run the command, Schematic is displayed.

 Page 160/257
R0062 Prohibition of specification for the different value to the same cell
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UIC-045
(report_clock_gating_check command can check this rule.)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When two set_clock_gating_check commands are specified to the same cell such as the following figures,
both commands have an influence on AND1/A. In this way, when the different values are specified to the same
clock gating cell, the operation is different in Prime Time and ICC. Prime Time adopts value set for pin, but
it is not clear that ICC adopts either values. Therefore, this rule reports the instance name of clock
gating cell when the different values are specified to the same clock gating cell.

◼ Sample circuit configuration and constraints

① The different value is specified to the same cell

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports CLK]

set_clock_gating_check -setup 1.0 -hold 2.0 [get_pins AND1/A] ・・・（1）
set_clock_gating_check -setup 2.0 -hold 4.0 [get_clocks CLK] ・・・（2）

setting with influence to the same cell

DATA D Q
（1）
CK
GATE1 A
CLK
AND1
（2）

GCA Message

Check UIC-045.
And, report_clock_gating_check command can confirm the setting point and the set value.
 Page 161/257

② The different value is specified to the same point.

When setting both ‘-high’ and ‘-low’ option of ‘set_clock_gating_check’ command to the
same cell, PrimeTime gives priority to the last command, but ICC accepts only the first
command. So there is different analysis result between PrimeTime and ICC.

create_clock -period 10 -waveform {0 5} -name CK1 [get_ports CLK]

set_clock_gating_check -setup 0.1 -high [get_pins AND1/A] ・・・（1）
set_clock_gating_check -setup 0.1 -low [get_pins AND1/A] ・・・（2）

setting with influence to the same cell

DATA D Q
（1） （2）
CK
GATE1 A
CLK
AND1

GCA Message

UIC-045:
set_clock_gating command at %s is overwritten by the command at %s for %s.

ex)
set_clock_gating command at abc.sdc, line 12 overwrites a previously issued command at abc.sdc, line
10 for pin AND1/A.
 Page 162/257
R0063 Prohibition of specification for cell for exclusive use of clock gating
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UDEF_IntegratedCellSetClockGating
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

When combinational cell is used as clock gating cell, constraint value for setup and hold is set with
set_clock_gating_check. In the other, clock gating integrated cell, which is exclusive use of clock gating and
has latch within cell for hazard free, has constrant value for setup and hold. When the clock gating integrated
cell is used, the operation is different in Prime Time and ICC.
Prime Time analysis timing with the constraint value by set_clock_gating_check, but ICC uses the constraint
value within cell library. Therefore, this rule reports the instance name of cell for attention when
set_clock_gating_check command is used for clock gating integrated cell.

◼ Sample circuit configuration and constraints

①set_clock_gating_check is specified to clock gating integrated cell (exception

simple function cell such as AND, NAND, OR and NOR) for timing constraint.

set_clock_gating_check -setup 1.0 -hold 2.0 [get_cells GCLK1]

clock gating integrated cell

FF
GCLK1 D1 Q
CEN GCK CK

CLK

clock gating integrated cell

GCA Message

No adaptation rule in GCA now.

However, report_clock_gating_check command can confirm the setting point and the set value.
 Page 163/257

7.5. Input/Output Constraints

7.5.1. set_input_delay/set_output_delay

Before conducting STA for the signal interface between the LSI and off-chip registers, define input delay and
output delay for input pins, output pins, and input/output pins. To be exact, define a value including the skew
of the clock driving the off-chip registers and that driving the registers in the LSI.
Use the set_input_delay and set_output_delay commands to define input delay and output delay.

◆ Recommended usage
 For the set_input_delay or set_output_delay command, use the -clock option to define which clock is
synchronized. Be sure to specify the -clock option.
 When making verification using multiple on-chip clocks or off-chip clocks, specify the -add_delay option.
Input delays are affected by blunting of the input waveform and output delays are affected by the output
load capacity. Make settings according to these characteristics as needed.

Input delay (set_input_delay) example

In the figure above, the reference clock of block A (verification target) is the clock of the register at the start
point of block B (not a verification target).
If no clock to be analyzed by IO exists in the block, a virtual clock is used.
Since input delay is affected by blunting of waveforms, make the following drive strength setting as needed
assuming the information of connections outside the block, and calculate the waveform blunting value. If these
constraints are not set, the estimated value of the wiring delay from the input port becomes 0.
 Page 164/257

Output delay (set_output_delay) example

set the load capacity

In the figure above, the reference clock of block B (verification target) is the clock of the register at the end
point of block A (not a verification target). If no clock to be analyzed by IO exists in the block, a virtual clock is
used.

Furthermore, set the output load capacity as needed, assuming the information of connections in block A (not
a verification target).

◆ Recommended example of command description

Input delay (set_input_delay)

Setting input delay at the rising edge of a clock
Set an input delay value of 1.0 for the input port DIN. Note that the delay starts at the rising edge of CLK (not
time 0). Input delay is set at the rising edge of a clock by default.
create_clock -period 5.0 -name CLK -waveform { 1.0 3.0 } [get_ports CLK]
set_input_delay 1.0 -clock [get_clocks CLK] [get_ports DIN]

It is recommended that input delay be set based on clock timing.

 Setting input delay based on multiple clocks

The following figure shows an example to set input delay based on multiple clocks.

First, set an input delay value of 1.2 at the rising edge of CLK1 for the input port DIN. Next, to additionally set
an input delay value of 2.2 at the rising edge of CLK2 for the same input port DIN, specify -add_delay for the
set_input_delay command. Note that, if -add_delay is omitted, the input delay that was set previously based
on CLK1 is overwritten by the input delay that was set later based on CLK2.

set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports DIN]

set_input_delay 2.2 -clock [get_clocks CLK2] -add_delay [get_ports DIN]
 Page 165/257

 Setting input delay at rising and falling edges of a clock

The following figure shows an example for setting input delay values at rising and falling edges of a single
clock.
Set input delay values of 2.0 (rising) and 2.5 (falling) based on the rising edge of CLK for the input port DIN.
set_input_delay -rise 2.0 -clock [get_clocks CLK] [get_ports DIN]
set_input_delay -fall 2.5 -clock [get_clocks CLK] [get_ports DIN]

Output delay (set_output_delay)

 Setting output delay at the rising edge of a clock

The following figure shows an example for setting output delay based on a single clock. Set an output delay
value of 1.0 at the rising edge of CLK for the output port QOUT. Output delay is set at the rising edge of a clock
by default. The virtual FF (F0) outside the circuit analyzes timing at the rising edge of F0/CLK.
set_output_delay 1.0 -clock [get_clocks CLK] [get_ports QOUT]

 Setting output delay based on multiple clocks

The following figure shows an example for setting output delay based on multiple clocks.
First, set an output delay value of 1.2 at the rising edge of CLK1 for the output port QOUT. Next, to additionally
set an output delay value of 2.2 at the rising edge of CLK2 for the same output port QOUT, specify -add_delay
for the set_output_delay command. Note that, if -add_delay is omitted, the output delay that was set previously
based on CLK1 is overwritten by the output delay that was set later based on CLK2.
 Page 166/257

set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports QOUT]

set_output_delay 2.2 -clock [get_clocks CLK2] -add_delay [get_ports QOUT]

(CLK standards) (CLK2 standards)

 Setting output delay at rising and falling edges of a clock

The following figure shows an example for setting output delay values for rising and falling edges of a single
clock.
Set output delay values of 1.0 (rising) and 1.5 (falling) based on the rising edge of CLK for the output port
QOUT.
set_output_delay -rise 1.0 -clock [get_clocks CLK] [get_ports QOUT]
set_output_delay -fall 1.5 -clock [get_clocks CLK] [get_ports QOUT]

◆ Notice

 Prohibiting specification of set_input_delay and set_output_delay for clock ports

Operation when set_input_delay is specified for clock ports varies with tools.
A problem occurs when the reference clock of the set_input_delay command is the same as the clock set for
a clock port. The input delay is ignored by the tool. Be careful particularly when specifying all_inputs as shown
below.

create_clock -name CLK -period 100 [get_ports CLK]

set_input_delay 1 -clock [get_clocks CLK] [all_inputs]
 Page 167/257

Proposed measures
If a virtual clock is declared as shown below, no problem will occur.
create_clock -name clk [get_ports CLK]
create_clock -name vclk
set_input_delay 1 -clock [get_clocks vclk]

create_clock -name clk -period 20 -waveform {0 10} [get_ports CLK]

set_input_delay -max 3 [get_ports CLK]
set_input_delay -min 2 [get_ports CLK]

◆ Supplement

Setting input delay for an instance pin

In the circuit below, set an input delay value of 1.5 for the instance pin Y of B1 at the rising edge of CLK. With
this setting, the timing path (F1/CLK to F2/DATA) is disconnected and a new timing path (B1/Y to F2/DATA) is
connected. Therefore, timing analysis is not applied to timing paths F1/CLK to F2/DATA and F1/CLK to B1/Y.

set_input_delay 1.5 -clock CLK [get_pins {B1/Y} ]

Setting output delay for an instance pin

In the circuit below, set an output delay value of 1.5 for the instance pin Y of B1 at the rising edge of CLK.
With this setting, the timing path (F1/CLK to F2/DATA) is disconnected and a new timing path (F1/CLK to B1/Y)
is connected. Therefore, timing analysis is not applied to timing paths F1/CLK to F2/DATA and B1/Y to F2/DATA.

set_output_delay 1.5 -clock CLK [get_pins {B1/Y}]

 168/257頁

7.5.2. Check rules

R0038 Input/Output constraints are incorrect relative to a range of clock period

R0038
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC UDEF_ZeroValueSetInOutDly
UDEF_MinusValueSetInOutDly
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If the delay constraint is set to 0 or less in set_input_delay/set_output_delay, it is more likely that the mounted
chip will be defective, so it is necessary to give a constraint that assumes the actual input delay. This rule
detects input/input/output terminals that specify a value of 0 or less for the set_input_delay/set_output_delay
constraint value.

◼ Sample circuit configuration and constraints

3. set_input_delay specification for data port

set_input_delay 0 setting point

din D Q dout
clk CK

create_clock -name CK1 -period 10 -waveform {0 5} clk

set_input_delay 0 –clock [get_clocks CK1] [get_ports din]

PTC Message

UDEF_ZeroValueSetInOutDly ：
zero value is set on 'input_delay_or_output_delay' - 'attrname' command (pin:'pin') in the SDC file
'SDCfile'.
UDEF_MinusValueSetInOutDly
minus value ('delay') is set on 'input_delay_or_output_delay' - 'attrname' command (pin:'pin') in the
SDC file 'SDCfile'.

4. set_output_delay specification for data port

set_input_delay 0 setting point

din D Q dout
clk CK

create_clock -name CK1 -period 10 -waveform {0 5} clk

set_output_delay 0 –clock [get_clocks CK1] [get_ports dout]

PTC Message

UDEF_ZeroValueSetInOutDly ：
zero value is set on 'input_delay_or_output_delay' - 'attrname' command (pin:'pin') in the SDC file
'SDCfile'.
 169/257頁
R0040 Necessary Conditions Are Defined for an External Port Constraint Definition
R0040
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXD_0004
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The rule flags incomplete set_input_delay constraints set on input/inout ports.

The rule flags incomplete set_output_delay constraints set on output/inout ports.
The rule requires:
・ A set_input_delay/set_output_delay constraint must specify either none or both of -min and
-max values.
・ A set_input_delay/set_output_delay constraint must specify either none or both of -rise and -fall
values.

In the set_input_delay/set_output_delay option, specify both -min (minimum delay value) and -max (maximum
delay value) at the same time, or do not specify both. If neither is specified, the minimum and maximum input
delay will be the same. The same applies to the combination of -rise (rise delay) and -fall (fall delay). This rule
detects set_input_delay/set_output_delay settings where only one of these combinations is specified.

◼ Sample circuit configuration and constraints

① A set_input_delay constraint only has -min value.

set_input_delay -min 2 [get_ports din]

-min value only

din

GCA Message

EXD_0004 ：
The input_or_output delay on object_type object_name has incomplete values.
 170/257頁
R0042 Input/output port not constrained by set_input_delay/set_output_delay
Severity RTL Layout I/F STA IP
n/a Warning Warning Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXD_0001
EXD_0002
EXD_0003
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The EXD_0002 rule flag input/inout ports without a set_input_delay constraint.

The EXD_0003 rule flag output/inout ports without a set_output_delay constraint

In order to perform timing verification (STA) correctly, the input delay value for the clock is required. Without
such clock information, timing verification will not be performed correctly. Therefore, set_input_delay is
required.

If the input delay is not set based on the clock with the set_input_delay command (when -clock is not specified),
the path to the sequential cell is verified based on time 0 using the specified input. Please specify the clock
with -clock because it is an unintended restriction depending on the waveform. These rules detect ports for
which the set_input_delay/set_output_delay command is not specified or ports whose
set_input_delay/set_output_delay command does not match the clock.

◼ Sample circuit configuration and constraints

There is no set_input_delay setting.
If the set_input_delay command is not set, the input delay is set to 0 and the timing is verified.

No set_input_delay setting
BLOCK

FF0 FF1
DIN D Q D Q
CK CK
CLK

GCA/PTC MESSAGE

EXD_0001 ：
Input/inout port port has no input delay specified.

◼ Action
Set the input delay for the associated clock to the data input/output port.
Confirmation method
The following is an example.

<violation>
EXD_0001:
Input/inout port 'DIN' has no input delay specified.

<constraint>
# There is no timing constraint for set_input_delay.

Check the reported port using the report_port command.

ptc_shell> report_port -input_delay [get_ports DIN]
****************************************
 171/257頁
Input Delay
Min Max Related Related
Input Port
Rise Fall Rise Fall Clock Pin
---------------------------------------------------------------
DIN -- -- -- -- -- --

Limitations (GCA/PTC)
Added EXD_0001 in Rule Set V02.01.06. EXD_0001 is not set to enable_rule in rulesets released before
V02.01.05. Switch enable/disable by the following method as required.

[example]
ptc_shell> enable_rule EXD_0001
ptc_shell> set_rule_severity error EXD_0001
ptc_shell> analyze_design

When set_input_delay is set but there is no related clock definition

The set_input_delay setting is insufficient

BLOCK

FF0 FF1
DIN D Q D Q
CK CK
CLK

create_clock [get_ports {CLK}] –name CLK –period 10 –waveform {0 5}

set_input_delay 1 [get_ports DIN]

GCA Message

EXD_0002 ：
Input/inout port port has no clock-related input delay specified.

For such timing constraints, GCA / PTC reports the following UIC-070 in “UserMessageBrowser” and log files.

%s without related clock (via -clock) can potentially trigger behavior mismatch from different timers. (UIC-070)

ex)
Warning: set_input_delay without related clock (via -clock) can potentially trigger behavior mismatch from
different timers. (UIC-070)

Action

Please set input delay at the data port for related clock.

Confirmation method

Check the reported port using the report_port command.

The following is an example.

<violation>
EXD_0002:
put/inout port 'DIN' has no clock-related input delay specified.
<constraint>
set_input_delay 1 [get_ports DIN]

In this case, an input delay is defined for port DIN, but you can see that the delay criterion (Clock) is not linked.
 172/257頁
ptc_shell> report_port -input_delay [get_ports DIN]
****************************************

Input Delay
Min Max Related Related
Input Port
Rise Fall Rise Fall Clock Pin
---------------------------------------------------------------
DIN 1.00 1.00 1.00 1.00 -- --

Attention (GCA/PTC)
If the reference clock is not specified in set_input_delay with the -clock option, the input delay is set to the input
terminal based on time 0.In the following cases, an input value of 1.5 is set to the input terminal DIN.

Time 0 is the reference, not the clock

 173/257頁
No set_output_delay setting

The set_output_delay command sets the output delay of the output terminal with respect to the edge of the
reference clock (specified clock of -clock). However, if set_output_delay is not set, or if the reference clock is
propagated to that pin, output delay 0 is set.

No set_output_delay setting
BLOCK

FF0 FF1
DIN D Q D Q OUT
CK CK
CLK

GCA/PTC MESSAGE

EXD_0003 ：
Output/inout port port has no clock-related output delay specified.

◼ Action
Set the input/output delay for the Related clock on the data input/output port.
Confirmation method

The following is an example.

<violation>
EXD_0003:
Output/inout port 'OUT' has no clock-related output delay specified.

<constraint>
# No timing constraint for set_output_delay.

Check the reported port using the report_port command.

From this report, you can see that output_delay is not set for output port OUT.

ptc_shell> report_port -output_delay [get_ports OUT]

****************************************

Output Delay
Min Max Related Related
Output Port
Rise Fall Rise Fall Clock Pin
---------------------------------------------------------------
OUT -- -- -- -- -- --

When set_output_delay is set but there is no definition of the related clock

If the reference clock is not specified for the specified pin and other clocks are not propagated, the timing
check results in “unconstraint path”.

Insufficient set_output_delay setting

BLOCK

FF0 FF1
DIN D Q D Q OUT
CK CK
CLK

create_clock [get_ports {CLK}] –name CLK –period 10 –waveform {0 5}

set_output_delay 1 [get_ports OUT]
 174/257頁

GCA/PTC MESSAGE

EXD_0003 ：
Output/inout port port has no clock-related output delay specified.

Action

Please set output delay at the data port for related clock.

Confirmation method

The following is an example.

<violation>
EXD_0003:
Output/inout port 'OUT' has no clock-related output delay specified.

<constraint>
set_output_delay 1 [get_ports OUT]

Check the reported port using the report_port command.

Looking at this report, you can see that output_delay is set for the output port “OUT”, but the related clock is
not defined.

ptc_shell> report_port -output_delay [get_ports OUT]

****************************************

Output Delay
Min Max Related Related
Output Port
Rise Fall Rise Fall Clock Pin
---------------------------------------------------------------
OUT 1.00 1.00 1.00 1.00 -- --
 175/257頁

R0052 Check conflicts in the external terminal constraint values

Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXD_0009
EXD_0010
EXD_0013
EXD_0015
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

If no timing constraint is set to an external port, timing analysis may not be performed correctly for that external port.
For this reason, checks are made for the following items to see if there is no consistency in constraints set to all
external ports:
- Whether there is no min value greater than the relevant max value
- Whether no delay value is set which exceeds the relevant clock period

◼ Sample circuit configuration and constraints

When the -min value is greater than the -max value in "set_input_delay", the following message is
output.
set_input_delay 3 -clock [get_clocks {CLK}] [get_ports {SEL}] -max
set_input_delay 5 -clock [get_clocks {CLK}] [get_ports {SEL}] -min

GCA Message

EXD_0015:
The input delay at object_type object has inconsistent values.

When the delay value specified in "set_output_delay" exceeds the relevant clock period, the following
message is also output.

create_clock -name CLK -period 4 -waveform { 1 2 } [get_ports {CLK}]

set_output_delay 8 -clock [get_clocks {CLK}] -max [get_ports {OUT}]

GCA Message

EXD_0010 :
The output delay at object_type object_name has values larger than max_percent % of the relative
clock's period.

Action

Check each detected external port to see whether there is a problem in the reported information.
If there is a problem, modify the SDC description.

GCA Limitations

The upper limit of EXD_0010 was changed to 99% from 50% of default values.
When larger than the clock period to which the delay value specified by set_input_delay relates
create_clock -name CLK -period 4 -waveform { 1 2 } [get_ports {CLK}]
set_input_delay 8 -clock [get_clocks {CLK}] -max [get_ports {IN}]

GCA Message

EXD_0009 :
The input delay at object_type object_name has values larger than max_percent % of the relative
clock's period.
 176/257頁

Action (common)

The contents of a report about the detected external terminal are checked.
Please correct SDC, when there is a problem.

Limitations

The upper limit of EXD_0009 was changed to 99% from 50% of default values.

When -min and -max of set_output_delay are reversed

set_output_delay 3 -clock [get_clocks {CLK}] [get_ports {SEL}] -max
set_output_delay 5 -clock [get_clocks {CLK}] [get_ports {SEL}] -min

GCA Message

EXD_00013 :
The output delay at object_type object_name has inconsistent values.
 177/257頁
R0054 A Required Input or Output Delay Is Set for All Connected Clock Domains.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency ◼semantics unclear TDL check rule user's manual
GCA/PTC UDEF_InputDelayCheck_0001
UDEF_OutputDelayCheck_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

An input or output delay is set for a clock domain. When an external pin is connected to multiple clock
domains, it is necessary to set the delay for all of the clock domains. If the delay is not set for any of these
clock domains, unintended timing analysis may be performed or the timing may not be verified.

◼ Sample circuit configuration and constraints

When set_input_delay is not set for CLKB

DIN0 DOUT0

CLKA
Set an input delay for Set an output delay
each of CLKA and CLKB. for each of CLKA and
CLKB.

CLKB

# setting for CLKA

set_input_delay 1 -clock [get_clocks CLKA] [get_ports DIN0]
set_output_delay 1 -clock [get_clocks CLKA] [get_ports DOUT0]

# no constraint for CLKB

# set_input_delay 1 -clock [get_clocks CLKB] –add_delay [get_ports DIN0]
# set_output_delay 1 -clock [get_clocks CLKB] –add_delay [get_ports DOUT0]

GCA Message

UDEF_InputDelayCheck_0001：

・Rule-Set V01.07.00 or later

The input/inout port/pin ("Port") is not set set_input_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set.

・Rule-Set V01.06.01 previous

No input delay is specified for port 'Port' for the required clock(s) 'Clocks'

UDEF_OutputDelayCheck_0001：

・Rule-Set V01.07.00 or later

The output/inout port/pin ("Port") is not set set_output_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set."

・Rule-Set V01.06.01 previous

No output delay is specified for port 'Port' for the required clock(s) 'Clocks'
 178/257頁
5. When CLK2 is associated as a clock related to DATA1 in the following circuit configuration

DATA1 FFA

CLK1

FFB

CLK2

set_input_delay 1 [get_ports DATA1] -clock [get_clocks CLK2]

GCA/PTC Message

UDEF_InputDelayCheck_0001：
・Rule-Set V01.07.00 or later
The input/inout port/pin ("Port") is not set set_input_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set.

・Rule-Set V01.06.01 previous

No input delay is specified for port 'Port' for the required clock(s) 'Clocks'

UDEF_OutputDelayCheck_0001：

・Rule-Set V01.07.00 or later

The output/inout port/pin ("Port") is not set set_output_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set."

・Rule-Set V01.06.01 previous

No output delay is specified for port 'Port' for the required clock(s) 'Clocks'

When CLK2 is associated with DOUT in set_output_delay, but the -add_delay option is not specified

set_output_delay -1 -min [get_ports DOUT] -clock [get_clocks CLKA]

set_output_delay -1 -min [get_ports DOUT] -clock [get_clocks CLKA]

GCA/PTC Message

・Rule-Set V01.07.00 or later

The input/inout port/pin ("Port") is not set set_input_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set.

・Rule-Set V01.06.01 previous

No input delay is specified for port 'Port' for the required clock(s) 'Clocks'

UDEF_OutputDelayCheck_0001：

・Rule-Set V01.07.00 or later

The output/inout port/pin ("Port") is not set set_output_delay for the clocks ("MissClock"). However, the
others ("GenClock") are set."

・Rule-Set V01.06.01 previous

No output delay is specified for port 'Port' for the required clock(s) 'Clocks'
 179/257頁

set_clock_group

When it's different from a clock corrugation of FF in a corrugation of Virtual clock.

create_clock –name CLKA –waveform {0 5} –period 10 CLKA

create_clock –name VCLKA –waveform {0 5} –period 20
create_clock –add –name CLKB –waveform {0 6} –period 13 CLKB
create_clock –add –name VCLKB –waveform {0 6} –period 13
set_input_delay 1 –clock VCLKA DIN0
set_input_delay 1 –clock VCLKB DIN0 –add_delay

GCA Messge

UDEF_InputDelayCheck_0001：
No input delay is specified for port 'Port' for the required clock(s) 'Clocks'
UDEF_OutputDelayCheck_0001：
No output delay is specified for port 'Port' for the required clock(s) 'Clocks'

GCA Limitations

• This rule will report a false error. For example, if you set the set_input_delay command, not only real clock,
also compares with Viratul clock. At that time, this rule, it is determined that different from the clock driving the
end point, and then report the false error. Therefore, if you set the Virtatul clock as intended, please treat it as
"false error".

Action

Please set the input delay for all clock domains on every data input port.
 180/257頁
R0057 No input transition constraints defined for inputs/inouts
Severity RTL Layout I/F STA IP
n/a Info Error Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC DRV_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

The Inp_Trans01a rule flags input/inout ports where none of the input transition constraints -
set_input_transition, set_drive, or set_driving_cell constraint are specified.

◼ Sample circuit configuration and constraints

set_input_transition command is not specified

data

GCA/PTC Message

DRV_0001 ：
Input/inout port pin has no input transition, driving cell or drive resistance specified.

◼ Action
Please set input transition constraint at input or inout port with set_input_transition, set_drive or
set_driving_cell.
Confirmation method

Violation : Input/inout port 'E' has no input transition or driving cell or drive resistance specified.

Use the report_report command to check the status of port “E”.

As the message shows, none of set_input_transition, set_drive, and set_driving_cell is set for port “E”.

ptc_shell> report_port [get_ports E] -drive

****************************************

Resistance (min/max)
Input Port Rise Fall
--------------------------------------------------------------------------------
E -- --

<Refer>
・In the PrimeTime, you can check with "no_driving_cell (report when there is no driving cell in the port)" of
the check_timing command. However, it is reported only if the net connected to the port has parasitics
information.
 181/257頁
R0058 Load on output or inout ports not set or zero
Severity RTL Layout I/F STA IP
n/a Info Warning Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC CAP_0001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
You need to define load constraints for output ports/inout (bidirectional) ports.
The CAP_0001 rule flags missing or incorrect load constraints for output or inout ports.
The CAP_0001 rule flags following cases:
1. An output or inout port without corresponding set_load constraint
2. An output or inout port with zero set_load constraint value

◼ Sample circuit configuration and constraints

◼ An output port with zero set_load constraint value

zero set_load constraint value

outport
D Q
clk
CK
create_clock
setting point

create_clock clk -name CK1 -period 10 -waveform {0 5}

set_load 0 [ get_ports outport ]

GCA/PTC MESSAGE

CAP_0001 ：
Output/inout port port has zero or incomplete capacitance values.

6. No set_load constraint on outport

no set_load constraint

outport
D Q
clk CK
create_clock
setting point

create_clock clk -name CK1 -period 10 -waveform {0 5} [ get_ports outport ]

GCA/PTC MESSAGE

CAP_0001 ：
Output/inout port port has zero or incomplete capacitance values.
◼ Action
Please output load with set_load at out port or inout port.
Confirmation method
 182/257頁
Violation 1: Output/inout port 'OUT' has zero or incomplete capacitance values.

Use the report_port command to check the status of the port 'OUT'.

ptc_shell> report_port [get_ports OUT]

****************************************
Report : port
Design : TOP
Scenario: default
Version: M-2016.12-SP1
Date : Tue Mar 7 16:58:40 2017
****************************************
Pin Cap Wire Cap
Min Max Min Max
Port Dir rise/fall rise/fall rise/fall rise/fall Attributes
--------------------------------------------------------------------------------
OUT out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

Or you can check the Violation Details in the GUI.

 183/257頁

R0128 Defining constraints in pair

Severity RTL Layout I/F STA IP
n/a Warning Warning Error/Info
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC EXD_0004 (IP: n/a)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
Although different specifications can be defined for pairs of min and max conditions, early and late conditions,
and setup and hold conditions, if only one item of a pair is defined, the tool may not be able to perform
necessary timing analysis because it does not take the the undefined condition into consideration. This rule is
therefore used to check whether the constraints supposed to be paired are defined.

Target commands :
⚫ set_input_delay
⚫ set_output_delay
Target potions :
⚫ -hold / -setup
⚫ -early / -late
⚫ -rise / -fall
⚫ -min / -max
⚫ Valid combinations of the above

◼ Sample circuit configuration and constraints

Minimum delay is specified in set_input_delay but maximum delay is not.

set_input_delay -min 2 [get_ports din]

-min value only

din

GCA/PTC MESSAGE

EXD_0004 ：
The 'input_or_output' delay on 'object_type' 'object' has incomplete values.
 184/257頁

R0129 Inconsistency between min/max option values

Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC EXD_0013
EXD_0015
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The tool may not be able to perform timing analysis properly on any constraints on the min and max values if
they have an inconsistency. This rule checks whether the magnitude relation between the min and max values
is reversed. This rule applies to the following SDC commands:
Two SDC commands of this rule, set_input_delay and set_output_delay, are objects.

➢ set_input_delay --- Detection is possible at EXD_0015 (support).

➢ set_output_delay --- Detection is possible at EXD_0013 (support).

The following commands don’t support in RENESAS’s recommendation rules. Because those commands
have not been use much. If you check this rule for those commands, please use A) "report_port -drive" and
B) "report_clocks -skew" if needed.

➢ set_drive --- CTR_0001(Not support) ※A)

➢ set_clock_transition --- DRV_0004(Not support) ※B)

➢ set_input_transition --- DRV_0005(Not support) ※A)

◼ Sample circuit configuration and constraints

-min and -max values in set_input_delay are reversed.

set_input_delay 3 -clock [get_clocks {CLK}] [get_ports {SEL}] -max

set_input_delay 5 -clock [get_clocks {CLK}] [get_ports {SEL}] -min

GCA/PTC MESSAGE
EXD_0015:
The input delay at 'object_type' 'object' has inconsistent values.

◼ Action
The bottom concerned checks the magnitude correlation of the restrictions value (max and min) of an
external terminal. SDC is corrected so that a restrictions value may turn into a "min value < max value."

When -min and -max of set_output_delay are reversed

set_output_delay 3 -clock [get_clocks {CLK}] [get_ports {SEL}] -max

set_output_delay 5 -clock [get_clocks {CLK}] [get_ports {SEL}] -min

GCA/PTC MESSAGE
EXD_0013:
The output delay at 'object_type' 'object' has inconsistent values.
 185/257頁
◼ Action
The bottom concerned checks the magnitude correlation of the restrictions value (max and min) of an
external terminal. SDC is corrected so that a restrictions value may turn into a "min value < max value."
 186/257頁

7.6. Exceptions
7.6.1. set_false_path

The set_false_path command is used to exclude some paths between clocks from the target of timing analysis.
Use the set_clock_groups command to set synchronous or asynchronous relationship between clocks.

◆ Recommended usage
The following description method is recommended for setting the set_false_path command.
 Indicate the launch clock and the capture clock with the -from option and -to option respectively. (This
item can be checked by R0067.)
 Specify the -from and -to options together. Should not specify the -through option alone. (This item can
be checked by R0068 and R0071). If constraints are correct, we can ignore these warnings and use -
through option for false setting.
 Do not specify the net name using the -through option. (This item can be checked by R0121.)

◆ Recommended example of command description

Clock line:
Set the clock line using the set_clock_groups command.

Data line
set_false_path -from [get_clocks {<launch clock name>}] -through [get_pins {<data pin name>}] ¥
-to [get_clocks {<capture clock name>}]

Example 1: Logically inactive paths

Logically inactive paths are also calculated as delays. Unnecessary optimization and timing violation can be
reduced by changing a logically inactive path to a false path.
In the figure below, the logically inactive path from FF2 to FF4 should be set to a false path.

set_false_path -from [get_clocks CLK1] -through [get_pins FF2/Q] -through [get_pins FF4/D] -to [get_clocks
CLK2]

CLK2
CLK1
 187/257頁

Example 2: Passing points

The -through option can be used to specify all paths passing through one or more specific pins, ports, or
instances. The following describe methods for specifying passing points.

Example 2-1: Specifying passing points sequentially

set_false_path -from [get_clocks {CLK}] -through [get_pins {B1/Y}] -through [get_pins {C1/Y}] -to
[get_pins {F2/DATA}]

The path from F1/CLK through B1 and C1 to F2/DATA is specified"

Example 2-2: Specifying a path through any of specified points

set_false_path -from [get_clocks {CLK}] -through [get_pins {B1/Y C1/Y}] -to [get_pins {F2/DATA}]

The path from F1/CLK through B1 or C1 to F2/DATA is specified.

Example 2-3: Specifying a path through a combination of passing points

set_false_path -from [get_clocks {CLK}] -through [get_pins {B1/Y B2/Y}] ¥

-through [get_pins {C1/Y C2/Y}] -to [get_pins {F2/DATA}]

The path from F1/CLK through B1 or B2 and C1 or C2 to F2/DATA is specified.

* The -through option can also be used instead of the -from and -to options but this method consumes many
calculation resources (particularly in large-scale circuits). Use the -from and -to option to specify paths as much
as possible"for more clearly.
 188/257頁
◆ Notice
 The set_false_path command differs from the set_disable_timing command that the set_false_path
disables the timing analysis of specific pins, instances, or ports. The use of the set_disable_timing
command does not delete timing constraints from paths but disconnects timing paths at object points. If
all paths that pass through a pin are false paths, using the set_disable_timing command is more effective.
However, it would be better to specify paths with the set_false_path command when multimode SDC is
considered. Use these commands appropriately. When an arc is broken by the set_disable_timing
command, edges are not physically propagated forward and do not act as crosstalk aggressors
downstream. This could lead to optimistic crosstalk analysis. If there is a true edge that could be
propagated for crosstalk analysis and you only want to suppress the timing analysis of the path, use the
set_false_path command. If the edge cannot truly propagate past a point, use the set_disable_timing
command.
 set_false_path or set_disable_timing affects the result of crosstalk noise. When the arc is cut by the
set_disable_timing command, the edge is not physically propagated forward and does not function as a
downstream crosstalk aggressor. This can lead to optimistic crosstalk analysis. Use the set_false_path
command if you have true edges that can be propagated for crosstalk analysis and you only want to
suppress path timing analysis. Use the set_disable_timing command when an edge cannot truly
propagate beyond a point.
 Though a false path can be specified by various methods, it is effective to select a method for specifying
all paths (affected by timing exception) most easily. If a wildcard is used for -through or paths are specified
one by one, the number of paths will increase as well as memory usage volume and execution time. Avoid
using a wildcard or specifying paths one by one as much as possible. If a wildcard (*) is set, it also applies
to all points that do not have a physical path. As a result, paths that do not require verification are actually
verified, which may increase the verification time.

◆ Supplement
The following descriptions are possible with the set_false_path command though they are not recommended.

Example 1: Setting a path between asynchronous clock domains

In a path between asynchronous clock domains, the allowable signal transition time between flip-flops may be
short (due to non-integer clock cycle ratio), and the tool misrecognizes a non-critical path as a critical path. For
this reason, a false path must be set.
To set all paths between clock domains to false paths specify the launch clock name in -from and the capture
clock name in -to. In the figure below, all paths from F1 to F3 and all paths from F3 to F4 become false paths.
Paths from F1 to F2 (clock domain CLK) and paths from F3 to F5 (clock domain CLK2) are not applied false
paths.
To improve the efficiency of analysis by the tool, specify each clock with a clock name (using get_clocks instead
of get_pins), not with a pin name.
set_false_path -from [get_clocks CLK] -to [get_clocks CLK2] : Setting for the path from F1 to F3
set_false_path -from [get_clocks CLK2] -to [get_clocks CLK] : Setting for the path from F3 to F4

false path

* The set_clock_groups command is recommended for setting a path between clock domains.
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Example 2: Setting a multi-clock path
In the case of the following figure, CLK1 and CLK2 can reach the FF in STA, but these clocks cannot reach
the FF at the same time due to MUX in the actual circuit. CLK1 and CLK2 are logically exclusive clocks.
When switching clocks dynamically, however, the selector signal of MUX must be switched while the clock is
at a low level. Measures to switch the selector signal are required in specifications or circuits.
set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]
set_false_path -from [get_clocks CLK2] -to [get_clocks CLK1]

To conduct verification by single execution of STA for multiple clock modes, define clocks for the same object.
Clocks in each mode will be set false path with clocks in others mode.

Example 3: Setting setup or hold analysis

The -setup or -hold option can be used to specify a false path for setup or hold analysis. This setting method
is shown below. If neither the -setup nor -hold option is specified (default setting), both setup analysis and hold
analysis become false paths.
set_false_path -to [get_pins F2/DATA] -hold

Hold constraint Setup constraint

Hold is not analyzed Setup is analyzed

(false path)

set_false_path -to [get_pins F2/DATA] -setup

Hold constraint Setup constraint

Hold is analyzed Setup is not analyzed

(false path)

Example 4: Setting rising and falling edges

Using the -rise and -fall options is prohibited. By specifying -rise or -fall option, only the path that rises or falls
at the end point is excluded from the timing check. The setting method is shown below.

Hold constraint Setup constraint

Rising edge is not analyzed (false path)

Falling edge is analyzed

Hold constraint Setup constraint

Falling edge is not analyzed (false path)

Rising edge is analyzed
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7.6.2. set_multicycle_path

Multicycle path constraints are intended to relieve verification edges to avoid any path with a data-flow control
circuit from being verified with pessimistic clock edges. Refer Figure 7-1 for more information

◆ Recommended usage
The following description method is recommended for setting the set_multicycle_path command.
 Set multicycle path constraints for paths with a data flow control circuit.
 Indicate the launch clock and the capture clock with the -from option and -to option respectively.
 Indicate the clock to be the reference of multicycle paths with the -end or -start option.
 Use the -through option to specify the data pin as a midpoint.
 Use the “set_multicycle_path with the -setup option” and “set_multicycle_path with the -hold options”
combinatorially to describe a multicycle path.

◆ Recommended example of command description

Multicycle path between clocks (with higher frequency on the capture clock)
set_multicycle_path –setup <number of cycles for setup> -end ¥
-from [get_clocks {<launch clock name>}] -to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -end ¥

-from [get_clocks {<launch clock name>}] -to [get_clocks {<capture clock name>}]

Multicycle path between clocks (with higher frequency on the launch clock)
set_multicycle_path –setup <number of cycles for setup> -start ¥
-from [get_clocks {<launch clock name>}] -to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -start ¥

-from [get_clocks {<launch clock name>}] -to [get_clocks {<capture clock name>}]

Multicycle path of data line (with higher frequency on the capture clock)
set_multicycle_path –setup <number of cycles for setup> -end ¥
-from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] ¥
-to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -end ¥

-from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] ¥
-to [get_clocks {<capture clock name>}]

Multicycle path of data line (with higher frequency on the launch clock)
set_multicycle_path –setup <number of cycles for setup> -start ¥
-from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] ¥
-to [get_clocks {<capture clock name>}]

set_multicycle_path –hold <number of cycles for hold> -start ¥

-from [get_clocks {<launch clock name>}] ¥
-through [get_pins {<data pin name>}] ¥
-to [get_clocks {<capture clock name>}]
 191/257頁

Figure 7-1 Example of Multicycle Path Circuit

◆ Notice
 It is prohibited to use only the -hold option without using the set_multicycle_path command for -setup.
 Do not specify the -setup and -hold options simultaneously with a single command.
 Consider the number of cycles based on the clock of higher frequency.
 Be sure to specify the -setup or -hold option.

◆ Supplement
Multicycle path constraints are used in some cases even when a data flow control circuit is not provided. The
following pages illustrate cases where engineers familiar with product specifications use multicycle path
constraints exceptionally to avoid restrictions on STA tool specifications or prevent timing constraints from
being excessively relieved by false paths. If you use multicycle path constraints just because “such constraints
were used in the previous product” or “timing violation does not converge” without understanding product
specifications, timing specifications may not be met, leading to a product failure. Follow the above
recommendations whenever possible.
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Example 1 Setting a multicycle path as an alternative to a false path

When an asynchronous transfer circuit is designed to prevent metastability, a false path is usually set between
different clock domains. Since false paths are not the target of optimization by the implementation tool, so the
tool will not optimize timing if false path constraints are set for asynchronous transfer circuit paths.
The following provides an example for setting a multicycle path instead of false path constraints if timing
optimization for the asynchronous transfer circuit is required due to design specifications.

・ Example when the capture clock frequency is high

Circuit characteristics are shown below.
* Clocks are asynchronous and their number of cycles is limited (within about 100 cycles).
* The capture clock frequency is higher than that of the launch clock.
* A synchronizer to prevent metastability is provided in the circuit.

Figure 7-2 Example of Asynchronous Transfer Path

The hold verification is not required because a synchronizer to prevent metastability is provided in the circuit.
Since the number of clock cycles is limited, the most critical clock edge is unclear.
There are two methods of setting a multicycle path: correcting the clock definition and using the clock definition
as it is.

[Correcting the clock definition]

If clocks are asynchronous and the number of cycles is limited (within about 100 cycles), the STA tool reports
a warning.
Therefore, it is recommended that the waveforms of the start clock and the end clock be modified so that these
clocks have common edges.
set_multicycle_path -end -setup 3 -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]
set_false_path -hold -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]

[Using the clock definition as it is]

When the number of cycles = n, the setup delay will be as follows:
* The minimum delay = (n-1)* cycles
* The maximum delay = n* cycles
If this setting is allowable, determine the number of cycles required for the minimum delay (n-1)* cycles.
If a delay of at least 2 clock cycles is required, set n = 3.
In this example, multicycle path constraints are the same as those in “correcting the clock definition”.
However, the timing with the same number of cycles is stricter than that in the case of correcting the clock
definition.
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・ Example when the capture clock frequency is low
Circuit characteristics are shown below.
* Clocks are asynchronous and their number of cycles is limited (within about 100 cycles).
* The capture clock frequency is lower than that of the launch clock.
* A synchronizer to prevent metastability is provided in the circuit.

Figure 7-3 Case where the capture clock frequency is lower than that of the launch clock

The hold verification is not required because a synchronizer to prevent metastability is provided in the circuit.
Since the number of clock cycles is limited, the most critical clock edge is unclear.
There are two methods of setting a multicycle path: correcting the clock definition and using the clock definition
as it is.

[Correcting the clock definition]

If clocks are asynchronous and the number of cycles is limited (within about 100 cycles), the STA tool reports
a warning.
Therefore, it is recommended that the waveforms of the start clock and the end clock be modified so that these
clocks have common edges.
set_multicycle_path -start -setup 3 -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]
set_false_path -hold -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]

[Using the clock definition as it is]

When the number of cycles = n, the setup delay will be as follows:
* The minimum delay = (n-1)* cycles
* The maximum delay = n* cycles
If this setting is allowable, determine the number of cycles required for the minimum delay (n-1)* cycles.
If a delay of at least 2 clock cycles is required, set n = 3.
In this example, multicycle path constraints are the same as those in “correcting the clock definition”.
However, the timing with the same number of cycles is stricter than that in the case of correcting the clock
definition.
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Example 2 Setting a multicycle path in cases where no data flow control circuit or synchronizer is
required
Even when it is clear that single-cycle transfer does not occur due to product specifications, multicycle path
constraints may be applied to paths with no data flow control circuit or asynchronous measures circuit.
The multi-cycle paths of Timing-intent are used for frequency relaxation and can be STA for optimistic.
Therefore, it is recommended to set the multicycle path with a constraint corresponding to the circuit
configuration with data flow control.

・ Example when the capture clock frequency is high

Circuit characteristics are shown below.
* Clocks are in synchronization.
* The capture clock frequency is higher than that of the launch clock
* Neither a data flow control circuit nor a synchronizer (to prevent metastability) is provided.

Figure 7-4 Multicycle Path Constraints by Design Intention

If the launch clock frequency differs from the capture clock frequency, consider the multicycle path setting
based on the most critical clock edge.
When the data flow control circuit is not provided, the hold time must be set one clock cycle before the setup
time to prevent FF2 from being in the metastable state.

set_multicycle_path -end -setup 3 -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]

set_multicycle_path -end -hold 2 -from [get_pins FF1/CLK] -to [get_pins FF2/DATA]

・ Example when the capture clock frequency is low

When neither data flow control circuit nor synchronizer is provided and the capture clock frequency is low, no
multicycle path should be given.
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7.6.3. set_max_delay, set_min_delay

The set_max_delay command is used to specify the maximum delay of a path as a constraint value, and the
set_min_delay command is used to specify the minimum delay of a path as a constraint value. The constraint
value set by the set_max_delay command is checked during the setup analysis. The constraint value set by
the set_min_delay command is checked during the hold analysis.

◆ Recommended usage
The following description method is recommended for setting the set_max_delay and set_min_delay
commands.
 Specify the start point (input port, bidirectional port, or register’s clock pin) of a path by “-from” option and
specify the end point (output port, bidirectional port, or register’s data pin) of a path by “-to” option.
 When the route of the path which has constraints is indicated, specify the route by using the -through
option.
 When the signal transition states at the start point, end point, and a point in the halfway route of a path
can be indicated, specify the signal transition states using the -rise_from, -fall_from, -rise_to, -fall_to, -
rise_through, -fall_through options respectively instead of the -from, -to, and -through options.

◆ Recommended example of command description

set_max_delay -from [get_ports {D0}] -to [get_pins {F0/DATA}] 1.0

set_min_delay -from [get_ports {D0}] -to [get_pins {F0/DATA}] 0.5

set_max_delay -from [get_pins {F0/CLK F1/CLK}] -to [get_ports {OUT}] 1.0

set_min_delay -from [get_pins {F0/CLK F1/CLK}] -to [get_ports {OUT}] 0.5
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◆ Notice
 Specification of “-from” can be omitted. In this case, however, constraints are set for paths from all start
points (recognized by the STA tool) to the end point specified by the -to option. When omitting “-from”, it
must be checked whether start points recognized by the STA tool meet the design intention. (This item
can be checked by R0130.)
 Specification of “-to” can be omitted. In this case, however, constraints are set for paths to all end points
(recognized by the STA tool) from the start point specified by the -from option. When omitting “-to”, it must
be checked whether end points recognized by the STA tool meet the design intention. (This item can be
checked by R0130.)
 Pins other than start points and end points of paths can be specified for -from and -to options. In this case,
a newly specified pin is set as a start point or an end point. (This item can be checked by R0082 and
R0084.)
 When a pin in the route of an existing path is specified for “-from”, constraint setting is applied to the
section from the specified pin to the end point of the existing path, generating a new path. The existing
path and the section from the start point of the existing path to the pin specified by the -from option are
not constrained.
Unconstrain

 When a pin in the route of an existing path is specified for “-to”, constraint setting is applied to the section
from the start point of the existing path to the specified pin, generating a new path. The existing path and
the section from the pin specified by the -to option to the end point of the existing path are not constrained.
Unconstrain

 When multiple set_max_delay commands or set_min_delay commands are set for pins other than the
start and end points in an existing path, constraint definition target points vary with tools. When such
setting is required, use your design/verification tool to check whether desired type of analysis is possible
at specific points.
report_timing -to I0/Z
report_timing -from I0/A
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◆ Supplement
The following describes various setting examples and constraints to be applied.
Example: Setting output delay and delay constraints for the same end point
set_output_delay -clock CLK 0.1 [get_ports OUT]
set_max_delay -to [get_ports OUT] 1.0
set_min_delay -to [get_ports OUT] 0.5
The path from F0/CLK to OUT and the path from F1/CLK to OUT are constrained as follows.
Maximum delay: set_max_delay constraint value - output delay value (1.0 - 0.1 = 0.9)
Minimum delay: set_min_delay constraint value - output delay value (0.5 - 0.1 = 0.4)

Example: Setting input delay and delay constraints for the same start point
set_input_delay -clock CLK 0.1 [get_ports D0]
set_max_delay -from [get_ports D0] 1.0
set_min_delay -from [get_ports D0] 0.5
The path from D0 to F0/DATA is constrained as follows.
Maximum delay: set_max_delay constraint value + clock latency - input delay - F0 cell setup constraint
value
Minimum delay: set_min_delay constraint value + clock latency - input delay + F0 cell hold constraint
value
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7.6.4. Check rules

R0064 Prohibition of overlap between timing exceptions commands

Severity RTL Layout I/F STA IP
n/a Info Info Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXC_0014
EXC_0015
UDEF_EXC_0014and15_FilterMcpOverlap (Layout/STA: Warning)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When overlappiing between set_false_path and set_multicycle_path, multicycle path dose not
effective for priority of timing exception. Therefore it should be careful that the multicycle paths which should
be effective does not overlap false paths. This rule flags when each timing exception commands overlap.

◼ Sample circuit configuration and constraints

False paths overlap multicycle paths

set_false_path -from [get_ports {CLK}]

set_multicycle_path –setup 2 -from [get_pins {FF1/CK}] -to [get_pins {FF2/D}]

FF1 FF2
D Q D Q
CK CK
FF3 FF4
D Q D Q
CK CK
FF5 FF6
D Q D Q
CK CK
false path
CLK
multicycle path

GCA/PTC MESSAGE

EXC_0014 ：
A multicycle_path exception at file, line number; file, line number is fully overridden by other exceptions.

* exception command: set_false_path, set_multicycle_path, set_max_delay, set_min_delay

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EXC_0015 ：
A 'multicycle_path exception at file, line number; file, line number is partially overridden by other
exceptions.

Please use ‘analyze_paths” command to confirm the overlap of the timing exceptions.

ex）The following command can check the timing exception information of constraints to pass every
endpoint.
analyze_paths -from [all_clocks] -nosplit > Output filename

UDEF_EXC_0014and15_FilterMcpOverlap :
A multicycle path command at ‘file_line_one’ in the rule ‘rule_name’ is overridden by other multicycle path
commands ‘file_line_two’

Of the violations reported by EXC_0014 and EXC_0015, the overwriting of only set_multicycle_path is filtered
and reported by this rule.

◼ GCA/PTC LIMITATIONS
* set_clock_groups command is checked out of EXC_0014 and EXC_0015.
Overlap between set_false_path command and set_clock_groups command checks the syntax analysis in
the CST-006 and CSTR-007. In addition, duplication of each other set_clock_groups command (read-ahead
priority) is checked by the parsing error UIC-030 and UIC-031 at the time of SDC read.
These errors GUI of UserMessage Browser or, can be found in the "report_constraint_analysis -output
<output file name> -include {user_messages}".

・The set_clock_groups command is not supported by EXC_0014 and EXC_0015.

Duplicates caused by the set_clock_groups command of the set_false_path command are checked with
CSTR-006 and CSTR-007, which are parsing errors when reading SDC. In addition, duplication of
set_clock_groups commands (read ahead is enabled) is also checked by the parsing error UIC-030 and UIC-
031 when reading SDC. These errors can be confirmed with the UserMessage Browser in the GUI or
“report_constraint_analysis -output <output file name> -include {user_messages}”.

CSTR-006 (warning) set_clock_groups overwrote existing false paths.

CSTR-007 (Information) From and to clocks contain exclusive or asynchronous clocks.

* Timing exception command (set_false_path, set_multicycle_path, set_max_delay, set_min_delay) priority

If you set the command of the different timing exception for the same path, a higher priority command is
enabled, low-priority command is disabled. The priority of the command is as follows.
Priority High: set_false_path
↕: set_max_delay and set_min_delay the same leve
Low: set_multicycle_path
・Timing exception command priority (set_clock_groups、set_false_path、set_multicycle_path、set_max_delay、
set_min_delay)

・If different timing exception commands are set for the same path, the command with the higher priority is
enabled and the command with the lower priority is disabled. The command priority is as follows.
Priority High：set_clock_groups
↑：set_false_path
↓：set_max_delay and set_min_delay are at the same level
Low：set_multicycle_path

Duplication of set_clock_groups and set_clock_groups follows the following priority order:

However, GCA / PTC cannot be verified based on this priority (STAR-9000896233).
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Similarly, the same issue occurs with the clock matrix (report_clock_crossing) display
command.set_clock_groups and set_clock_groups overlap follows the following order of precedence.
Priority High：physically exclusive
↕ ：asynchronous
Low：logically exclusive

・To check for set_clock_groups, set the following in the GCA / PTC execution script, and then execute
analyze_design.
enable_rule {CGR_*}

・Duplicate report for UDEF_EXC_0014and15_FilterMcpOverlap and EXC_0014/0015

Even after filtering with UDEF_EXC_0014and15_FilterMcpOverlap, violations for the same
set_multicycle_path are still displayed in EXC_0014/EXC_0015.

・ If the existing environment for GCA summarizer esults is used, the judgment result of
UDEF_EXC_0014and15_FilterMcpOverlap cannot be taken over and will be handled as New.

◼ Action
Please confirm wheter it is problem or not that low priority constraint become invalid when some timing
exception constraints overlap on the same timing paths.
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R0067 Prohibition of specification for the asynchronous set or reset of register
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UDEF_SyncRstSetExceptionTo
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When the endpoint of set_false_path/set_multicycle_path is specified for the asynchronous set or reset pin of
a register, the operation is different between Prime Time and ICC. PrimeTime set it through the set or reset
pin. However, ICC set it to set or reset pin as endpoint. Therefore, this rule reports the instance name of set or
reset pin as an error when endpoint of set_false_path is specified for the asynchronous set or reset of register.

◼ Sample circuit configuration and constraints

The asynchronous reset pin of register is specified for the object of optional -to

set_false_path -to [get_pins f2/RB]

asynchronous reset pin is specified

timing path set_false_path is effective timing path set_false_path is effective

f1 f2 f3 f1 f2 f3
D Q Q D Q D Q Q D Q
CK RB CK CK RB CK

asynchronous reset pin is specified asynchronous reset pin is specified

Interpretation of PrimeTime Interpretation of ICC

GCA/PTC MESSAGE
UDEF_SyncRstSetExceptionTo :

・Rule-Set V02.01.01 or later

Asynchronous preset or clear pin of registers is specified on "option" by the command in the SDC file
"SDCfile".

・Rule-Set V02.00.00 previous

Asynchronous preset or clear pin of registers is specified on " option " by the command "command" in
the SDC file " SDCfile ".

◼ Action
If reset pin of register is set as end point, please move end point to the output pin of the cell which drives its
reset.
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R0068 Option -from/-to not specified for set_false_path/set_multicycle_path command
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UDEF_NoSetFromToFalsePath
UDEF_NoSetFromToMultiPath
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The False_Path11/MCP08 rule flags set_false_path/set_multicycle_path commands where the -from, -to or
both the options are not specified.
False/Multi-cycle paths should ideally be specified using both the -from and -to options. This reduces the
possibility of specifying a single cycle path as false path.
Single cycle path specified as false/multi-cycle path leads to sub-optimization, as the STA tool gets
relaxed for such paths.

◼ Sample circuit configuration and constraints

①-from option setting point ②-to option setting point

D Q
clk2 CK
I2 out1
I1
in1 D Q Z
Z
clk1 CK
③ -through option setting point

(1) set_false_path command where the -to option is not specified.

set_false_path –from [get_ports {in1}] -through [get_pins {I2/Z}]

(2) set_false_path command where the -from option is not specified.

set_false_path -through [get_pins {I2/Z}] -to [get_ports {out1}]

(3) set_false_path command where the -from, -to both the options are not specified.

set_false_path -through [get_pins {I1/Z}]

GCA/PTC MESSAGE

UDEF_NoSetFromToFalsePath ：

・Rule-Set V02.00.01 or later

Option "option" is not specified by the command in the SDC file "SDCfile".

・Rule-Set V02.00.00 previous

Option "option" is not specified by the command command in the SDC file "SDCfile".

UDEF_NoSetFromToMultiPath ：.

・Rule-Set V02.00.01 or later

Option "option " is not specified by the command in the SDC file "SDCfile ".
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・Rule-Set V02.00.00 previous
Option "option " is not specified by the command command in the SDC file "SDCfile ".

◼ Action
Pleaese set set_false_path or set_multicycle_path with start point and end point to clear set point.
 204/257頁
R0069 False/multi-cycle path reference points are not connected
Severity RTL Layout I/F STA IP
n/a Warning Warning Error/Warning
Category ■consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC EXC_0006 (IP: Error)
UDEF_InvalidPartialException
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
These rules checks for existence of paths specified using the -from, -to, or -through arguments of timing
exception constraint in the SDC file(s). These rule also applies to any points for which there is no physical path
if points are set with a wildcard (*). Also, if you set the timing constraints and “-through object1 -through
object2”, GCA/PTC is summarized as one of “thorugh” group. Therefore, GCA /PTC is might output the
excessive report.

◼ Sample circuit configuration and constraints

CLK1
FFA

FFB
CLK2

In the following circuit configuration, when "set_false_path" is specified for a nonexistent path, the
following message is output.

set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]

GCA/PTC MESSAGE

EXC_0006 ：
A false_path exception at file, line number does not specify any valid paths.

UDEF_InvalidPartialException:

Exception defined at ''file_line'' is not specify partially valid paths.

◼ GCA/PTC LIMITATIONS
The specification point of detected set_false_path or set_multicycle_path is checked. A timing exception setup
is invalid. When you specify the same port as a clock generation point in order to set up effectively, please set
up a clock name (the following, the pattern A).
This problem is the specification of a tool, and when the port which carried out the clock definition is specified
as "-from" option, it becomes invalid (The following, the pattern B).

・Pattern A --- Case where a timing exception setup becomes effective

create_clock –name “clk1” –period 10 [get_ports CLK1]
set_false_path –from [get_clocks clk1]
・Pattern B --- Case where a timing exception setup becomes invalid
create_clock –name “clk1” –period 10 [get_ports CLK1]
set_false_path -from [ get_ports CLK1]
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When "set_multicycle_path" is specified for a non-existent path, the following message is also output.

set_multicycle_path 2 -setup -from [get_clocks CLK1] -to [get_ports CLK2]

GCA/PTC MESSAGE

EXC_0006 ：
A false_path exception at file, line number does not specify any valid paths.

UDEF_InvalidPartialException:
Exception defined at ''file_line'' is not specify partially valid paths.

When set_false_path is specified for a partially nonexistent path

create_clock -name CLK1 -period 5.0 -waveform { 0.0 2.5 } [get_ports {T1}]
set_false_path -from [get_pins {I5/Q_reg/CP}] -to [get_pins {I3/Q_reg/D I11/Q_reg/D}]

GCA/PTC MESSAGE
UDEF_InvalidPartialException:
Exception defined at ''file_line'' is not specify partially valid paths.
 206/257頁

◼ Action
Check whether the "set_false_path" and "set_multicycle_path" settings are correct.
After checking, modify the SDC description to set "set_false_path" and "set_multicycle_path" correctly.

◼ Confirmation method

<Violation>
A ‘false_path exception at /full_path/sdc.tcl, line 5’ does not specify any valid paths.

<Constraint>
create_clock -period 5 [get_ports clk1]
create_clock -period 5 [get_ports clk2]
create_clock -period 5 [get_ports clk3]
set_case_analysis 1 [get_pins reg1/Q]
set_false_path -thr [get_pins reg1/Q]

<Debug method>

Detailed information can be obtained by clicking “execute” in “ViolationBrowser” of GUI.

Click "execute" to execute the analyze_path command.

In this case, the user-specified Constant logic value “user_case_1” is set in reg1/Q, and the timing path of the
path for which false path is set is invalid.

ptc_shell> analyze_paths -through [get_pins {reg1/Q}] -max_endpoints 1000 -path_type full -

traverse_disabled -unconstrained
****************************************
Summary of Paths:
Dominant Overridden Count Clocks
Startpoint Endpoint Constraint Constraints (r,f,R,F) Launch/Capture
--------------------------------------------------------------------------------

Full report of all pins in the paths

Level Pin Attr Constraints

--------------------------------------------------------------------------------
1 reg1/CP (LIB-CELL) Start
2 reg1/Q (LIB-CELL) user_case_1
 207/257頁
As an alternative to EXC_0006, you can use report_exceptions to verify that timing exception constraints are
invalid.
ptc_shell> report_exceptions -thr [get_pins reg1/Q] -ignored

###############################################################################
## Redundant exceptions (totally overridden by other exceptions):
## none.

###############################################################################
## Exceptions that do not cover any constrained paths:

# /full-path/sdc.tcl, line 5
set_false_path -through [get_pins {reg1/Q}]

Note that set_case_analysis and set_false_path cannot be set to the same path at the same time.
This is the default behavior for PrimeTime.

For example, if there are two valid paths in the netlist:

reg1/clk1 -> reg2/clk2
reg1/clk1 -> reg3/clk3

Add a false path for this netlist and initial constraints.

set_false_path -thr [get_pins reg1/Q]
As a result, the above two paths are hidden from the timing report.

Next, set the set_case_analysis.

set_case_analysis 1 [get_pins reg1/Q]

By setting Case, the timing arc of reg2 and reg3 is invalidated.

Therefore, the above two paths become invalid paths and the timing path disappears.

When doing so, the false path you set earlier is automatically disabled.

report_disable_timing -nosplit [get_cells {reg2 reg3}]

****************************************

Attributes
c - case-analysis
C - Conditional arc

Cell or Port From To Sense Flag Reason

--------------------------------------------------------------------------------
reg2 CP D setup_clk_rise c D=1
reg2 CP D hold_clk_rise c D=1
reg3 CP D setup_clk_rise c D=1
reg3 CP D hold_clk_rise c D=1

※ The above report is an excerpt from report_disable_timing.

The method of confirming this state by GCA/PTC can be detected by EXC_0006 (report when timing exception
path is invalid). By clicking “execute” using the GUI, a detailed report and schematic will be displayed and you
can see why it was disabled. In this case, you can see that it is the “user_case_value” of the Case that was
set earlier.

The false path itself is already disabled because the timing arc is breaked by the Case setting, so it is reported
as an effect of the set_case_analysis, not overwriting the constraint.

ptc_shell> analyze_paths -through [get_pins {reg1/Q}] -max_endpoints 1000 -path_type full -

traverse_disabled -unconstrained
****************************************
Summary of Paths:
Dominant Overridden Count Clocks
Startpoint Endpoint Constraint Constraints (r,f,R,F) Launch/Capture
 208/257頁
--------------------------------------------------------------------------------

Full report of all pins in the paths

Level Pin Attr Constraints

--------------------------------------------------------------------------------
1 reg1/CP (FD1) Start
2 reg1/Q (FD1) user_case_1
1

◼ GCA/PTC LIMITATIONS

・EXC_0006 cannot be detected if there is a path that does not exist partially.
It takes much time to process UDEF_InvalidPartialException for tracing all constrainted paths. So
UDEF_InvalidPartialException rule is disabled by default. Please use enable_rule command to check its rule
as the need arises.
set_max_delay or set_min_delay command cuts a timing path compulsorily and generates ‘start point’ or ‘end
point’ when setting ‘-from’ or ‘-to’ option at the middle point of path besides ‘start point’ and ‘end point’. Even if
points which ‘-from’ or ‘-to’ were set isn't already ‘start point’ or ‘end point’ of paths by ‘-from’ or ‘-to’ option of
set_max_delay command, EXC_0006 rule will be detected. Because the rule checks without recognizing a
generated pass as a result of the set_max_delay command.

On the other hand, ‘UIC-011’ reports that the ‘start point’ or ‘end point’ are changed compulsorily.
（UIC-011 (warning) %s is forcing pin ’%s’ to be a timing %s.）
。
- It will be improved so that EXC_0006 does not flag when the path is cut.

・If the path specified in the timing exception command is set with the wildcard “*”, EXC_0006 is reported
when there is no path among the multiple paths. Therefore, to confirm the validity of the report, it is necessary
to check the path of each set timing exception constraint with “*”. Please refrain from specifying “*”. In addition,
as a debugging aid, we are requesting a message refurbishment to report the applicable timing exception
constraint from the message reporting the current SDC file and line number.
STAR: 9000823331
report_constraint_analysis should give the command directly in text/csv output is registered.

・When using rule set V01.09.00 or earlier, CMD-012 is reported in UserMessageBrowser, but please ignore
the following two cases. It has been modified so that it does not report in V02.00.00.

Error: extra positional option 'exception' (CMD-012)

Error: extra positional option '_sel44134' (CMD-012)
- The number “44134” of “*_sel44134” changes with each execution.

As for the influence before V01.09.00, SDC reported to EXC_0006 should not be reported again by
UDEF_InvalidPartialException. However, before V01.09.00, there is a possibility that it will be reported twice
(it is an excessive report and there is no omission of verification).

・If UDEF_InvalidPartialException is used, SEL-005 may be reported.

If SEL-005 is a confirmation on the GUI and points to the analyze_design command line, treat SEL-005 as a
pseudo error.
 209/257頁
R0071 -through Is Not Used for an Object for Which -from/-to Can Be Used in a Timing
Exception Constraint.
Severity RTL Layout I/F STA IP
n/a Error Error n/a
Category consistency ◼semantics unclear TDL check rule user's manual
GCA/PTC UDEF_ReportThPointException
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
Any object can be specified for a path point (-through) in a timing exception constraint. If
-through is used for an object for which -from and -to can be used, however, the target object becomes unclear
and timing analysis may not be performed correctly.
This rule detects no command in which a clock is specified in the -from/-to option.

◼ Sample circuit configuration and constraints

Objects that can be set in timing exception constraints

set_false_path, set_multicycle_path
-from -through -to
Clock  ⎯ 
External input pin Used Not Used Not Used
(No problem with syntax
when used)
External output pin Not Used Not Used Used
(No problem with syntax
when used)
F/F clock pin Used Not Used Not Used
(No problem with syntax
when used)
F/F data pin Not Used Not Used Used
(No problem with syntax
when used)
F/F output pin Not Used Used Not Used

Latch gate pin Used Not Used Not Used

(No problem with syntax
when used)
Latch data pin Used Not Used Used
(No problem with syntax
when used)
Latch output pin Not Used Used Not Used
Combinational circuit pin Not Used Used Not Used
Hierarchical pin Not Used Used Not Used

Combinations that are not detected

set_false_path, set_multicycle_path
-from -through -to
clock External input pin
External output pin clock
clock Clock pin of F/F
Data pin of F/F clock
 210/257頁
GCA/PTC MESSAGE

UDEF_ReportThPointException：

・Rule-Set V02.01.01 or later

The number ("number ") of pins/ports are set by '-through' option instead of '-from' or '-to' option in the
command, which is the command in the SDC file " SDCfile ".
・Rule-Set V02.00.00 previous
The number (number") of pins/ports are set by '-through' option instead of '-from' or '-to' option in the command,
which is command in the SDC file "SDCfile".

◼ Action
When the timing exception with ‘-through option’ is set to the site where is able to be set with ‘-from’ or ‘-to’,
please change ‘-through’ to ‘-from’ or ‘-to’ option.

◼ GCA/PTC LIMITATIONS
The upper limit value beyond which an error is raised is set to 10000. The limit value can be changed by setting
the maxerr rule property.

ptc_shell> set_rule_property maxerr 10000 UDEF_ReportThPointException

 211/257頁
R0072 Prohibition of specification for the asynchronous set or reset of register
Severity RTL Layout I/F STA IP
n/a Warning Warning n/a
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UDEF_SyncRstSetExceptionThrough
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When the -through option of set_false_path is specified for the asynchronous set or reset pin of register, the
operation is different in PrimeTime and ICC/EDI. PrimeTime sets a timing path through the set or reset pin as
a false path, while ICC/EDI does not set it as a false path. Therefore, this rule reports the specified point when
the -through option is specified for the asynchronous set or reset of register.

◼ Sample circuit configuration and constraints

The asynchronous reset pin of register is specified for the object of optional -through

set_false_path -to [get_pins f2/RB]

asynchronous reset pin is specified

timing path set_false_path is effective timing path set_false_path is effective

f1 f2 f3 f1 f2 f3
D Q Q D Q D Q Q D Q
CK RB CK CK RB CK

asynchronous reset pin is specified asynchronous reset pin is specified

Interpretation of PrimeTime Interpretation of layout tool

GCA/PTC MESSAGE
UDEF_SyncRstSetExceptionThrough :

・Rule-Set V02.01.00 or later

Asynchronous preset or clear pin of registers is specified on "option" by the command in the SDC file
"SDCfile".

・Rule-Set V02.00.00 previous

Asynchronous preset or clear pin of registers is specified on "option" by the command command in the
SDC file "SDCfile".

◼ Action
When set_false_path is set through reset pin of register, please re-set set_false_path in 2 paths, which are at
the register before the register with through point and at the next regsiter after the register with through point.

◼ GCA/PTC LIMITATIONS

・Reports when the specified point of -through option is other than the asynchronous set / reset pin of the
register.
 212/257頁
➢ Limitation: Rule-set V02.00.00 or earlier
It is also reported when the asynchronous set/reset pin is not specified with the -through option of the
set_false_path command. For this reason, the designer must confirm that the specified point of the -through
option is not an asynchronous set/reset pin. If the specified point is not an asynchronous set/reset pin, it must
be treated as a falseerror.

➢ Not Limitation: Rule-set V02.01.00 or later

As specified in this rule, this rule is reported only when the asynchronous set / reset pin of the register is
specified with the -through option.

* Rule-set V02.00.00 previous was reported without -through option of set_false_path command specifies the
"asynchronous set / reset pin". Therefore, it is false error unless you specify "asynchronous set / reset pin" in
-through option. This issue is resolved in the Rule-set V02.01.00.
 213/257頁
R0074 set_false_path constraint is specified and there exists a crossing among the clocks
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
The DomainInfo flags an informational message in the following cases:
・ If set_false_path constraint is only specified and there exists a crossing among the clocks.
・ If set_clock_uncertainty constraint is only specified and there exists a crossing among the clocks.
The DomainInfo rule generates a .sgdc file that contains all the domain information inferred from the SDC
constraints. This domain information can be used for further analysis.

◼ Sample circuit configuration and constraints

① set_false_path command where the -from option is not specified
set_false_path -through [get_pins {I2/Z}] -to [get_clocks {clk1}]

-to
D Q
clk2 CK
I2 out1
D Q
D Q Z
clk1 CK clk1 CK

② set_false_path command where the -to option is not specified.

set_false_path -setup -from [get_clocks {clk1}] -through [get_pins {I1/Z}]

D Q
clk2 CK
I1
in1 D Q D Q
Z
clk1 CK clk3 CK
-from

GCA/PTC MESSAGE

UDEF_NoSetFromToFalsePath ：

・Rule-Set V02.01.00 or later

Option "option" is not specified by the command in the SDC file "SDCfile ".

・Rule-Set V02.00.00 previous

Option "option" is not specified by the command "command " in the SDC file "SDCfile ".

UDEF_NoSetFromToMultiPath ：
・Rule-Set V02.01.00 or later
Option "option" is not specified by the command in the SDC file "SDCfile "

・Rule-Set V02.00.00 previous

Option "option" is not specified by the command "command " in the SDC file "SDCfile ".
 214/257頁
R0075 Paths between Clock Domains Are Specified as a False Path
Severity RTL Layout I/F STA IP
n/a Warning Warning n/a
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC No applicable rule
(report_clock_crossing command can check this rule.)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
A false-path constraint is usually set to paths between clock domains because they are normally excluded from
timing analysis. If no false-path constraint is given, the paths are also subjected to timing analysis, and
unnecessary timing analysis may be performed. For this reason, checks are made to see if a false-path
constraint is given to paths between clock domains

◼ Sample circuit configuration and constraints

In the following circuit configuration, when set_false_path is not defined between CLK1 and CLK2, the following
message is output.

FFA FFB

CLK1

CLK2

◼ GCA/PTC MESSAGE
No adaptation rule in GCA now.
However, report_clock_crossing command can confirm false paths between clock domains.

◼ Action
Check the path between clock domains to see whether the "set_false_path" specification is required.
After checking, modify the SDC description to specify "set_false_path" when required.
 215/257頁
R0077 Prohibition of specification for different values to the same path in
set_multicycle_path
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics ■unclear □TDL □check rule user’s manual
GCA UDEF_DiffvaluetoPathSetMultiPath1
UDEF_DiffvaluetoPathSetMultiPath2
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When the different value with ‘-through’ option of set_false_path is specified to the same path, the operation is
different between PrimeTime and ICC. In case of setup, both Prime time and ICC validate a smaller set value
of set_multicycle_path, on the other hand, in case of hold, Prime Time validates a bigger set value of it, but
ICC calculates hold value from a combination of a bigger set value of setup and a smaller set value of hold.
Therefore, this rule reports set points as an error when the different value with ‘-through’ option of
set_false_path is specified to the same path

◼ Sample circuit configuration and constraints

Different values set to points that affect the same path

(1)set_multicycle_path -from FF1/CK -setup 3

(2)set_multicycle_path -from FF1/CK -hold 1
(3)set_multicycle_path -through and1/Y -setup 2
(4)set_multicycle_path -through and1/Y -hold 2

FF
1D Q
and1
CK Y
and2 FF
Different value on the same path D2 Q
CK

＜setup＞
Both PT and ICC make more small value 2 effective from (1) and (3).

＜hold ＞
PT makes more larger value 2 effective from (2) and (4). But ICC calculate hold value from
combination of the large value in (1) and (3), and the small value in (2) and (4).

Inconsistent -start/-end options at points that affect the same path

(1)set_multicycle_path -from FF1/CK -setup 3 -start

(2)set_multicycle_path -from FF1/CK -hold 1 -end
(3)set_multicycle_path -through and1/Y -setup 3 -end
(4)set_multicycle_path -through and1/Y -hold 1 -start
 216/257頁

FF
1D Q
and1
CK Y
and2 FF
In the areas that affect the same path
does not match the start/-end option D2 Q
CK

GCA/PTC MESSAGE
UDEF_DiffvaluetoPathSetMultiPath1 :
"Difference path multiplier values are setting to between to muticycle path "file_line" and "file_line_ow"

UDEF_DiffvaluetoPathSetMultiPath2 :
Difference -start/-end option are setting to between to muticycle path "file_line" and "file_line_ow"

◼ Action
Please visually confirm to summarize to one if some multicycle paths are on the same timing path.

◼ GCA/PTC LIMITATIONS

1) When the constraint is overwritten (UIC-056 is the flag), the original constraint and the overwritten constraint
are held within GCA in a mixed manner, causing a false error.
set_multicycle_path 5 -from CLK -through mod1/in1 ;# -- M0
set_multicycle_path 5 -through mod1/in1 ;# -- M1
set_multicycle_path 3 -through mod1/in1 ;# -- M2
Although a specification error in different multicycle counts on the same path is expected for M0 and M2, since
M1 and M2 are mixed together, errors are detected both for M0 and M1 and for M0 and M2.

2) Rule-set V02.00.00 previously reported to the UIC-0009 is a double at the time of the check at the SDC
read (UserMessage Browser to display). This issue is resolved in the Rule-set V02.01.00.
In addition, the contents of the UserMessage Browser of the GUI, can be output in
"report_constraint_analysis -output <output file name> -include {user_messages}"

3) GCA is not recognize the forced start / end point by set_min_delay / set_max_delay. Therefore, it can not
be detected even if there is a duplicate of the associated path to it.

4) Rule-set V02.00.00 earlier is very time consuming to detect the duplication of the path. It takes very run time
depending on this for design. This issue is solved in the Rule-set V02.01.00.
When performing SDC verification (analyze_design), be sure to enable EXC_0014 and verify this rule. If you
use the Renesas standard Template (IP/Layout/STA), there is no additional setting.
 217/257頁
R0078 set_multicycle_path setup or hold over or under defined
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA UDEF_InvalidValueMultiPath
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
This rule detects the set_multicycle_path command in which the value specified in the -setup option is not
greater than the value that is set in the -hold option. When the start and end clocks have different waveforms,
this rule has meaning if the -start and -end options are explicitly specified.

◼ Sample circuit configuration and constraints

set_multicycle_path command with both -setup and -hold options are set to value 1

-from option setting point D Q

clk2 CK
I1 out1
in1 D Q
D Q
Z clk3 CK
clk1 CK

set_multicycle_path 1 -setup -from [get_ports {in1}] -through [get_pins {I1/Z}]

set_multicycle_path 1 -hold -from [get_ports {in1}] -through [get_pins {I1/Z}]

GCA Message

UDEF_InvalidValueMultiPath ：
The multiplier of set_multicycle_path command is set on invalid value.
Setup[Rise] : %d, Setup[Fall] : %d, Hold[Rise] : %d, Hold[Fall] : %d.
Source File. file , Line number

set_multicycle_path command with only -setup

-from option setting D Q

point clk2 CK
I1 out1
in1 D Q D Q
Z clk3 CK
clk1 CK

set_multicycle_path 1 -setup -from [get_ports {in1}] -through [get_pins {I1/Z}]

# set_multicycle_path 1 -hold -from [get_ports {in1}] -through [get_pins {I1/Z}]

GCA Message

UDEF_InvalidValueMultiPath ：
The multiplier of set_multicycle_path command is set on invalid value.
Setup[Rise] : %d, Setup[Fall] : %d, Hold[Rise] : %d, Hold[Fall] : %d.
Source File. file , Line number

◼ Action
Please check the cycle number of the multi-cycle path on the same timing path.
 218/257頁

R0080 Prohibition of specification for the output pin of cell on clock line
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC EXC_0008
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
There are cases in which the layout tool and PrimeTime make different interpretations if the output pin of a cell
on the clock line is specified in the -from option of set_min/max_delay. While PrimeTime performs timing
analysis using the the path delay from the specified pin up to the clock pin of the sequential cell and the
maximum and minimum delay constraints, the layout tool behaves differently. For this reason, do not designate
the output pin of a cell on the clock line as the starting point.

◼ Sample circuit configuration and constraints

The output pin of the cell on the clock line is specified for the object of optional -from

set_min_delay 1.0 -from [get_pins l1/Q]

The output pin of the cell on the clock line

The output pin of the cell on the clock line is specified.

l1
CLK
Q

In the above case, the specified point is valid as the PrimeTime start point, but the clock latency is different
because it is invalid in the layout tool.

GCA/PTC MESSAGE
EXC_0008 :
A exception is forcing start and/or end points, breaking the clock network.

◼ Related message
If set_input_delay, set_min_delay, set_max_delay is given to a place that is not a start point, it will be forced
to start point. For these limitations, GCA /PTC reports UIC-011 when reading SDC. UIC-011 can be confirmed
with “UserMessageBrowser”.

UIC-001 (wraning) %s is forcing pin '%s' to be a timing %s.

ex) Forcibly set output pin as start point with set_min_delay command
ptc_shell> set_min_delay 1.0 -from [get_pins mux_clk/Z]
Warning: set_min_delay is forcing pin 'mux_clk/Z' to be a timing startpoint. (UIC-011)
 219/257頁
R0082 Reporting any set point that is specified in set_min/max_delay as the start point
with an object other than the clock to an FF/Latch/hard module or external input
R0082
Severity RTL Layout I/F STA IP
n/a Warning Warning Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UDEF_ReportFromNonClkSetMinMaxDly
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When giving the minimum/maximum delay as constraint values to between 2 points on a timing path with
set_min_delay/set_max_delay, the starting point of the path is specified using the -from option. It must be
noted that the path subject to timing constraints varies depending on the starting point. This rule reports the
point that is specified in the -from option to urge the user to check the path under the timing constraint when
an object other than the clock of an FF or latch or external input port is specified in the -from option.

◼ Sample circuit configuration and constraints

Specification for the input terminal of not gate

set_min_delay 0.5 -from [get_pins INV/I]

set_max_delay 1.0 -from [get_pins INV/I]

timing constraint path

starting point

FF0 FF1
D Q D Q
I INV
CK CK

Not target path for timing constraint

“FF0/CK -> INV/I” is not target path for timing constraint

GCA/PTC MESSAGE
UDEF_ReportFromNonClkSetMinMaxDly :

set_max_delay and set_min_delay of -from option is not set on neither the clock pin of registers nor input
ports pin.
 220/257頁
R0084 When the ending point of the timing constraint path is set to besides a data pin of FF and an
output port, the setting point specified by -to option is reported.
Severity RTL Layout I/F STA IP
n/a Warning Warning Info
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UDEF_ReportToNonDataSetMinMaxDly
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
set_min_delay/set_max_delay command specifies the required minimum/maximum delay for timing path in
the current design. And -to option specifies ending point of the timing path. It is necessary to note the setting
point, because a path for the timing constraint is different according to the place in the ending point. When the
ending point of the timing constraint path is set to besides a data pin of FF and an output port, this rule report
the setting point specified by -to option for confirmation of timing constraint path.

◼ Sample circuit configuration and constraints

Specification for the output pin of not gate

set_min_delay 0.5 -to [get_pins INV/ZN]

set_max_delay 1.0 -to [get_pins INV/ZN]

timing constraint path

Non target path for timing constraint

INV
FF0 ZN FF1
D Q D Q
CKend point CK

INV/ZN -> FF1 is not target path for timing constraint

GCA/PTC MESSAGE
UDEF_ReportToNonDataSetMinMaxDly :
set_max_delay and/or set_min_delay of -to option are not set on neither the data pin of registers nor output
ports "pin" in the SDC file "SDCfile".

R0086 Inconsistent set_max_delay and set_min_delay commands

Severity RTL Layout I/F STA IP
n/a Error Error Error/Info
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXC_0009 (IP: Error)
EXC_0010 (IP: Info)
EXC_0011 (IP: Info)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
This rule flags paths with set_max_delay and set_min_delay constraints set but the maximum delay value is
less than the minimum delay value.
 221/257頁
This rule does not check for existence of the path; it just checks whether both maximum and minimum
delay values are specified for the path and the maximum delay value is not less than the minimum delay value.

◼ Sample circuit configuration and constraints

BLK1
I1 Z
in1 out1

set_min_delay command is not specified.

set_max_delay 2.0 -from [get_ports in1] -to [get_ports out1]

GCA/PTC MESSAGE

EXC_0010 ：
A 'exception' has no corresponding min_delay for a max_delay exception.

EXC_0011 ：
A 'exception' has no corresponding max_delay for a min_delay exception.

Specification for the path and the maximum delay value is not less than the minimum delay value.

set_max_delay 2.0 -from [get_ports in1] -to [get_ports out1]

set_min_delay 3.0 -from [get_ports in1] -to [get_ports out1]

GCA/PTC MESSAGE

EXC_0009 ：
Inconsistent 'exception'; min_delay must be less than max_delay.
 222/257頁
R0087 set_min/max_delay reference points are not connected
R0087
Severity RTL Layout I/F STA IP
n/a Warning Warning Error/Warning
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC EXC_0006 (IP:Error)
UDEF_InvalidPartialException (IP:Warning)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If you specify set_min_delay/set_max_delay to a point where there is no path in the specified section,
PrimeTime does not generate an error. If the layout tool is executed with the same constraints, the processing
time may be long, so you should not specify set_min_delay/set_max_delay to a point where there is no path
in the specified section.
Detected when set_min_delay/set_max_delay is specified for a point where there is no path in the specified
section.
In this rule, when points are set using “*” (wild card), points that do not have a physical path are also detected.

◼ Sample circuit configuration and constraints

Specification for path reference points are not connected

set_min_delay 5.0 -from [get_pins {FF1/CK}] -to [get_pins {FF2/D}]
set_min_delay 5.0 -from [get_pins {FF1/CK}] -to [get_pins {FF4/D}]

Path reference points are not connected

FF1 FF2
D Q D Q
CK CK

FF3 FF4
D Q D Q
CK CK

GCA/PTC MESSAGE

EXC_0006 ：
A 'exception' does not specify any valid paths.

UDEF_InvalidPartialException:
Exception defined at 'file_line" is not specify partially valid paths.

◼ GCA/PTC LIMITATIONS
EXC_0006 cannot detect any partially nonexistent paths.
 223/257頁
R0092 Timing Constraints Are Given to Paths Consisting Only of Combinational Logic
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category □consistency □semantics □unclear □TDL ■check rule user’s manual
GCA/PTC UDEF_ComboPath_001
UDEF_ComboPath_002
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If no timing constraint is given to a path consisting only of combinational logic, timing analysis may not be
performed correctly for the path. For this reason, checks are made for the following items to see if timing constraints
are given to paths consisting only of combinational logic:
• Whether a constraint is given to paths consisting of combinational logic
• Whether both max delay and min delay constraints are given to paths consisting of combinational logic

◼ Sample circuit configuration and constraints

In the following circuit configuration, when no constraint is defined for the path from DATA1 to DATAOUT, the
following message is output.

DATA1
DATAOUT

DATA2

GCA/PTC MESSAGE

UDEF_ComboPath_001：
There are no timing constraints set for a combinational path from input port 'input' to output port 'output'.

In the above circuit configuration, when either of "set_max_delay" and "set_min_delay" is only given for the
path from DATA1 to DATAOUT, the following message is also output.

set_max_delay -from DATA1 -to DATAOUT1 10

GCA/PTC MESSAGE

UDEF_ComboPath_002：
There are no timing constraints set for a combinational path from input port 'input' to output port 'output'.
Min-Max delay are not fully specified for a combinational path from port/pin " from_port_pin" to port/pin
" to_port_pin". MaxRise/MaxFall/MinRise/MinFall "SpecVal".

◼ Action
Check each detection path consisting of combinational logic to see whether there is no problem when no
constraint is given.
If there is a problem, modify the SDC description.
 224/257頁
R0093 No Inconsistent Constraint Is Given to Paths Consisting Only of Combinational Logic
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXC_0009
EXC_0010
EXD_0014
EXD_0013
EXD_0015
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If an inconsistent constraint is given to a path consisting only of combinational logic, timing analysis may not be
performed for the path under the condition the designer intends.
For this reason, checks are made for the following items to make sure that there is no inconsistency in constraints
given to paths consisting only of combinational logic:
• Whether there is no min value greater than the relevant max value
• Whether the sum of the "set_input_delay" and "set_output_delay" values does not exceed the relevant
clock period
• Whether the sum of the "set_input_delay" and "set_output_delay" values does not exceed the
"set_max_delay" value.
◼ Sample circuit configuration and constraints

When the "set_max_delay" value is smaller than the "set_min_delay" value as shown below, the following
message is output.

set_max_delay -from DATA1 -to DATAOUT1 5

set_min_delay -from DATA1 -to DATAOUT1 10

GCA/PTC MESSAGE
EXC_0009 :
Inconsistent 'exception'; min_delay must be less than max_delay.

ex)
Inconsistent 'max_min_delay exception at test.sdc, line 33; test.sdc, line 34'; min_delay must be less
than max_delay.

When the sum of the "set_input_delay" and "set_output_delay" values exceeds the clock period, the following
message is also output.

create_clock -period 15 -waveform {0 7.5} -name VCLK

set_input_delay 7 [get_ports DATA4] -clock [get_clocks VCLK]
set_output_delay 10 -clock [get_clocks {VCLK}] -max [get_ports {DATAOUT1}]

GCA/PTC MESSAGE
EXD_0014:

The input/output delay set on the combinational path from 'from_object_type' 'from_object' to
'to_object_type' 'to_object' is incorrect.
 225/257頁
When the sum of the "set_input_delay" and "set_output_delay" values exceeds the "set_max_delay" value, the
following message is also output.

set_input_delay 7 [get_ports DATA4] -clock [get_clocks VCLK]

set_max_delay -from DATA4 -to DATAOUT1 15

GCA/PTC MESSAGE
If the sum of set_input_delay and set_output_delay exceeds the value of set_max_delay, it is not checked.

When the min value in set_output_delay is greater than max value

GCA/PTC MESSAGE
EXD_0013:
The output delay at 'object_type' 'object' has inconsistent values.

◼ Action
Check if there is a problem with the reported content of the path detected by the combinational logic.
If there is a problem, correct the SDC.
◼ GCA/PTC LIMITATIONS
This rule does not check any condition in which the sum of set_input_delay and set_output_delay exceeds the
value of set_max_delay. It does not check any condition when the min value of set_input_delay is greater than
the max value.
 226/257頁
R0095 A Combinational Circuit Contains No Timing Loop.
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category consistency semantics ◼unclear TDL check rule user's manual
GCA/PTC LOOP_001
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When a loop circuit consists of only a combinational circuit, tools automatically cut a timing loop at a point on
the loop path. At this time, a timing path to be verified may be cut. The cut point is different among tools, so
the timing analysis result becomes inconsistent.

◼ Sample circuit configuration and constraints

GCA/PTC MESSAGE
LOOP_001 :
Arc from pin 'from_pin' to 'to_pin' is disabled due to combinational loop.

◼ Action
Use the set_disable_timing command to cut the timing loop.
Cut and carry out the timing loop from an input pin to the output pin of a cell of a cell by a set_disable_timing
command. When only an input pin is set up, there are the following limitations.

◼ Limitations

If only the input pin of a cell is set up when check_timing -loop and a report_disable_timing command are used
by PrimeTime and loop information is checked (restrictions 1), There is fault reported without disabl(ing) the
timing arc of input pin "output pin from A"" Y", and it is.
It is during an improvement of a function at a tool vendor.

STAR-9000793578 : check_timing/report_disable_timing to report the loop disabled

Originally, the restrictions as which the set_disable_timing command specified only the "pin" also become
effective. The false error was outputted on the problem of check_timing or a report_disable_timing command.
At the time of a set_disable_timing command setup, it is specifying the input pin (-from) of a cell, and the output
pin (-to) of a cell (restrictions 2).

Constraint 1 The fault example of a report_disable_timing command

set_disable_timing [ get_pins I1/U1/A ]

Result) Constraint 1 “report_disable_timing [get_pins I1/U1]”

Cell or Port From To Sense Flag Reason
---------------------------------------------
I1/U1 A Y positive_unate l
I1/U1 A * * u

Constraint 2 Recommended settings

 227/257頁
set_disable_timing –from [ get_pins I1/U1/A ] –to [ get_pins I1/U1/Z ]

Result) Constraint 2 report_disable_timing [get_pins I1/U1]

Cell or Port From To Sense Flag Reason
---------------------------------------------
I1/U1 A Y positive_unate l
 228/257頁
R0121 set_false_path Must Not Be set to Net With ‘-through’
Severity RTL Layout I/F STA IP
- - - -
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
PrimeTime enables false paths if a net is specified in the -through option. ICC (DC) supports no net with the -
through option. Therefore, PrimeTime and ICC (DC) yield different timing analysis results.
PrimeTime accepts the constraint, but ICC（DC) does not support false path through nets. This causes
discrepancy between PrimeTime and ICC（DC) timing results

set_false_path –through [get_nets NET1]

GCA/PTC MESSAGE
No applicable rule

◼ Limitations
This is a timing exception constraint that should be reported in UIC-076 (Error Messages) of GCA/PTC, but is
not reported in GCA/PTC (up to 2016.12-SP1).

UIC-076 (Information) The '-through' option for net '%s' is interpreted to imply its load pins.
 229/257頁
R0122 Set Value to Cell and Clock Pin for set_mux_delay or set_min_delay Must Be Same
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency □semantics ■unclear □TDL □check rule user’s manual
GCA/PTC UDEF_exception_pin_cell
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description

PrimeTime takes the latest settings; ICC（DC) takes the most pessimistic settings. This causes discrepancy
between PrimeTime and ICC（DC) timing results.

create_clock -period 20 -waveform {0 10} -name CK0 [get_ports CLK1]

create_clock -period 30 -waveform {0 15} -name CK1 [get_ports CLK2]
set_max_delay 2.0 -from [get_cells FF1]
set_max_delay 3.0 -from [get_pins FF1/CLK]
set_min_delay 1.5 -from [get_pins FF1/CLK]
set_min_delay 1.0 -from [get_cells FF1]

GCA/PTC Message
UDEF_exception_pin_cell
set_max_delay or set_min_delay from pin 'pin' is conflicting with another constraint specified on cell
'cell'. Please change the SDC specification: 'pin_constraint_sdc' and 'cell_constraint_sdc'.

◼ Related message・rule

GCA/PTC Message：UIC-011, UIC-056

UIC-056 (warning) Exception overwrites previous exception at %s.

UIC-011 (warning) %s is forcing pin '%s' to be a timing %s.
 230/257頁
R0130 Prohibition of specification such that both of -from/-to options are not specified in
set_min_delay/set_max_delay_path
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency semantics unclear TDL ◼check rule user’s manual
GCA/PTC UDEF_NoSetFromToSetMinMaxDly
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
It is recommended that the -from and -to options be specified in pair to minimize errors in minimum
delay/maximum delay specification. This rule detects set_min_delay or set_max_delay commands in which
either one or both of the -from and -to options are missing.

◼ Sample circuit configuration and constraints

(1) -from and -through (2) -through and -to specified

D Q
specified
clk2 CK
I2 out1
I1
in1 D Q
Z Z
clk1 CK (3) Only -through specified

1. set_max_delay specified without the -to option

set_max_delay -from [get_ports {in1}] -through [get_pins {I2/Z}]

2. set_max_delay specified without the -from option

set_max_delay -through [get_pins {I2/Z}] -to [get_ports {out1}]

3. set_max_delay specified with the -through option only

set_max_delay -through [get_pins {I1/Z}]

GCA/PTC MESSAGE

UDEF_NoSetFromToSetMinMaxDly ：
・Rule-Set V02.01.00 or later
Option "option" is not specified by the command in the SDC file "SDCfile".

・Rule-Set V02.00.00 previous

Option "option" is not specified by the command command in the SDC file "SDCfile".

◼ Action
When specifying set_min_delay or set_max_delay, specify the start and end points in pair to make the set
points clear.
 231/257頁

R0131 Prohibition of specification of set_min/max_delay that affects other paths by being specified
for a point other than start/end points
Severity RTL Layout I/F STA IP
n/a Error Error Error
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC EXC_0005
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
If points that are neither start nor end points are specified in -from and -to when the minimum and maximum
delays are given as constraint values to between two points on a timing path using
set_min_delay/set_max_delay, the specified points become the new start and end points. Unintended timing
analysis will be performed if the new start/end points exist on a path other than the path that is specified in
set_min_delay/set_max_delay.

◼ Sample circuit configuration and constraints

set_max_delay specified on a nonexistent path

The points specified in -from/-to become the new start/end points even if there is no path between BF0/Z and
BU1/A. Therefore, the default path from FF0/CLK to FF1/D is not subjected to timing analysis.
Path subject to timing constraints

FF0 BF0 FF1

set_max_delay
FF2 BF1 FF3

Path subject to timing constraints

set_max_delay 0.5 -from [get_pins BF0/Z] -to [get_pins BF1/A]

set_max_delay set for Data pin of a latch

Since latch DL1 is fixed in the through mode, the Data pin DL1/D of the latch is not an end point. Consequently,
the default path DL1/D to FF3/D is not subjected to timing analysis.

Path subject to timing constraints

set_max_delay

FF0 BF0 DL1 FF1

G

Case 0

set_max_delay 0.5 -from [get_pins BF0/Z] -to [get_pins DL1/D]

GCA/PTC MESSAGE
EXC_0005 :
A 'exception' will create startpoints or endpoints and break other timing paths through those pins.
 232/257頁
R0132 Exclusive setting must be made for convergence clocks
Severity RTL Layout I/F STA IP
n/a Warning/Info Warning/Info Warning/Info
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UDEF_ConvClkOnComb (Warning)
UDEF_ConstUnSelPinOnClkMUX (Warning)
UDEF_NoConvClkOnMUX (info)
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
For a path between F/Fs that are driven by the clock output from a MUX or similar device into which two or
more clocks merge, an error will be detected unless an exclusive setting (false path) is configured for the timing
paths between different clocks for that path. Although no asynchronous transfer occurs on this path because
the two F/Fs are configured always to be driven by the same clock, pessimistic detection is likely to bring in
because not only the timing paths between synchronous clocks but also timing paths between different clocks
are subjected to timing analysis.

◼ Sample circuit configuration and constraints

Different clock propagation to the two or more input pins of conbinational gates except for MUX gates.

Path subject

Two or more clocks

propagate FFA FFB

CLK1
D0

D1
CLK2

create_clock -period 10 -waveform {0 5} -name CLK1

create_clock -period 8 -waveform {0 4} -name CLK2

GCA/PTC MESSAGE
UDEF_ConvClkOnComb
The combinational gate (inst:'instance', lib_cell:'reference_name') has more than one input-pins w/ clocks.
Please see the input-pins list ('inputpins_list').

Clock propagation to one of the Data pin of a MUX gate with the select pin which is not fixed

Path subject
SEL =1 -> CLK
SEL =0 -> DIN

FFA FFB

CLK
D0

DIN D1
0/1
SEL

Check the clock propagation to Data pin D0 with the selecter pin which is not fixed at 0 or 1
 233/257頁
create_clock -period 10 -waveform {0 5} -name CLK

GCA/PTC MESSAGE
UDEF_NoConvClkOnMUX
The MUX gate (inst:'instance', lib_cell:'reference_name') which is on a clock-tree, has no clocks on the other
input_pin. Please check inputs list ('inputpins_list').

Clock propagation to one of the Data pin of a MUX gate with the select pin which select the clock propation
pin

Path subject
SEL =1 -> CLK
SEL =0 -> DIN

FFA FFB

CLK
D0

DIN D1
1
SEL

Check the clock propagation to Data pin D0 with the selecter pin which is fixed at 1

create_clock -period 10 -waveform {0 5} -name CLK

set_case_analysis 1 [get_ports SEL]

GCA/PTC MESSAGE
UDEF_ConstUnSelPinOnClkMUX
The MUX gate (inst:'instance', lib_cell:'reference_name') on a clock-tree has no clocks on the unselected
input_pins. Please see for information list ('inputpins_list').
◼ Action
Check the following and correct the SDC so that a false path is set up for paths between F/Fs with different
clocks if all of them are evaluated to be true:
⚫ There is a path between F/Fs.
⚫ The clock pins of the F/Fs are connected to the same line.

[Example of an action]
Add the following constraints:

create_generated_clock -name CLK1_A [get_pins MUX/D01]

set_false_path -from CLK1_A -to CLK2
set_false_path -from CLK2 -to CLK1_A
 234/257頁
R0133 Prohibition of duplicate objects in the -through timing exception option
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency semantics ◼unclear TDL check rule user’s manual
GCA/PTC UDEF_ExceptionSameThrPoint
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When there is overlap with the object that is specified by the other options, Object that is specified by the –
through option of timing exception command is prohibited becase the PrimeTime and ICC, the interpretation
is different. To detect the case where there is an overlap of the object of the same type.

◼ Sample circuit configuration and constraints

(1) Duplication of the specified Object -through option

set_multicycle_path 2–setup –through U1/Z –through U1/Z

U1

FFA FFB

CLK1

CLK2

(2) hierarchy pin and leaf pin object that is specified in the –through option

Be careful when carrying out the process of moving a constraint on the leaf pin.

set_multicycle_path 2–setup –through SUB1/U1/Z –through SUB1/OUT

SUB1

U1
OUT
IN
FFB
FFA

CLK1

CLK2

GCA/PTC MESSAGE
UDEF_ExceptionSameThrPoint
timing exception ‘exception_type’ has common objects ‘common_object’ in ‘exception’ ‘fileline’

◼ Action
Please delete the redundant object.
◼ GCA/PTC LIMITATIONS
Duplication of the same object can be detected as a hierarchy pin and hierarchy pin. However, example (2)
can not be detected.
 235/257頁

R0134 The -start/-end options must be specified explicitly for a multicycle path between clocks of
different frequencies
Severity RTL Layout I/F STA IP
n/a Warning Warning Warning
Category consistency ◼semantics unclear TDL check rule user’s manual
GCA/PTC UDEF_NoSetStartEndMultipath
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
When specifying multicycle paths between clocks of different frequencies, it is necessary to specify explicitly
which of the start or end clock is to serve as the reference clock using the -start or -end option. This rule detects
an error if either -start nor -end options is missing when the frequencies of the start and end clocks differ. An
error is also detected unless the -start or -end option is specified so that the clock with a higher frequency is
designated as the reference clock.

◼ Sample circuit configuration and constraints

Take care of (1) to (5) when the frequency of CLK1 and CLK2 is not same

FFA FFB

CLK1

CLK2

(1) No -start or –end option

Create_clock –period 20 [get_port CLK1]

Create_clock –period 10 [get_port CLK2]
set_multicycle_path 3 –setup –from [get_clocks CLK1] –to [get_clock CLK2]
set_multicycle_path 2 –hold –from [get_clocks CLK1] –to [get_clock CLK2]

(2) -start option for End point with a high clock frequency

Create_clock –period 20 [get_port CLK1]

Create_clock –period 10 [get_port CLK2]
set_multicycle_path 3 –setup -start –from [get_clocks CLK1] –to [get_clock CLK2]
set_multicycle_path 2 –hold –start –from [get_clocks CLK1] –to [get_clock CLK2]

(3) -end option for Start point with a high clock frequency

Create_clock –period 10 [get_port CLK1]

Create_clock –period 20 [get_port CLK2]
set_multicycle_path 3–setup –end –from [get_clocks CLK1] –to [get_clock CLK2]
set_multicycle_path 2–hold –end –from [get_clocks CLK1] –to [get_clock CLK2]
 236/257頁
(4) Multi frequencies at reference clock

Create_clock –period 10 [get_port CLK1]

Create_clock –period 20 [get_port CLK2]
set_multicycle_path 3–setup –start –from [get_clocks *] –to [get_clock CLK2]
set_multicycle_path 2–hold –start –from [get_clocks *] –to [get_clock CLK2]

(5) Illegal –start/-end option

Create_clock –period 10 [get_port CLK1]

Create_clock –period 20 [get_port CLK2]
set_multicycle_path 3–setup –end –from [get_clocks CLK1] –to [get_clock CLK2]
set_multicycle_path 2–hold –end –from [get_clocks CLK1] –to [get_clock CLK2]

GCA/PTC MESSAGE
UDEF_NoSetStartEndMultiPath
・Rule-Set V02.01.00 or later
'option' in the SDC file 'file_line'.

・Rule-Set V01.09.00 previous

option command in the SDC file file_line.

◼ GCA/PTC LIMITATIONS

If you set start point(-from), through point(-through) and end point(-to) are the same path. Warning report were
output in multi lines for the constraints of –setup and –hold option separately.

U1
Set the same path
① Setup FFA FFB
② Hold

CLK1

CLK2

If you set set_multicycle_path command the following two are on the same path. Therefore, during the Warning
report (2) the (1) and (2) of both command lines.
create_clock –period 10 [get_port CLK1]
create_clock –period 20 [get_port CLK2]
(1) set_multicycle_path 3 -setup -start –from [get_clocks CLK1] –through U1/X –to [get_clock CLK2]
(2) set_multicycle_path 2 –hold –from [get_clocks CLK1] –through U1/X –to [get_clock CLK2]
 237/257頁
S0004 The pin specified in FalsePath must not transition to <cycle number -1>
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual
GCA/PTC No applicable rule
LITMUS No applicable rule
ConCert FP_<Cmd-ID>(_<NUM>)
(Dynamic Simulation）
◼ Description
The verification methods using False path and Multicycle Path SVA are similar. The SVA of this rule verifies
that there is no transition at the specified pin in the time after the signal of Start point transitions on the pin
specified by the set_false_path command on the logic simulation/emulation. If the signal of the specified pin
inadvertently transits once or more on the functional simulation/emulation, there is a discrepancy between the
SDC and the functional simulation/emulation environment. The SDC constraint or the logic
simulation/emulation environment [reset signal, stable (expected number of cycles of the signal transition No
applicable rule)] must be reviewed (when SDC is as designed).

◼ Sample circuit configuration and constraints

false Paths with or without path specification are mixed

## test.sdc. in this case violation.

create_clock -name CLK1 -period 10 -waveform {0 5} [get_ports CLK1]
set_false_path -from [get_clocks CLK1] -through [get_pins AND/Y]

The above set_false_path is specified only with -through. The expected value of this constraint is that the
signal at the AND / Y pin does not change after CLK1 changes. Therefore, for this false path, use the following
SVA and confirm that there is no signal change of the specified pin.

・Properties
With this property, after one cycle of the evaluation clock (CLK) startup, excluding the non-evaluation period
(RST), the signal is output for a specific period (FP cycle number minus 1) on all pins specified by the false
path constraint. ) Can be confirmed not to transition.

property p_fp_stable_all(CLK, RST, STABLE_COND, SETUP);

@(posedge CLK) disable iff (RST)
##1 !STABLE_COND |=> STABLE_COND[*SETUP-1];
endproperty

・SVA (assertion) converted from SDC

This SVA is got by applying actual clock pins and specified pins to the above properties.

assert property
(p_fp_stable_all( `TOP_INST.CLK1,`CHK_DISABLE_FP,$stable(`TOP_INST.AND.Y),`CYCLE));

`TOP_INST,` CHK_DISABLE_FP, and `CYCLE should be defined before executing SIM/HWE using the define
macro.
・`TOP_INST ： Netlist top hierarchy name
・`CHK_DISABLE_FP ： Set a reset signal that is an FP check exclusion condition.
・`CYCLE：Set an arbitrary period specified by the user (period when the specified pin does not change).
 238/257頁

SIM/HWE result

SIM(VCS)

"tb.test.FPM__0_.FP_1_1", 374 attempts, 14 successes, 18 failures, 1 incompletes

HWE(Palladium)

Checked? Finish Failed Assertion Name

374 14 18 tb.test.FPM__0_.FP_1_1

◼ Action
The false path SVA is expected not to change the signal of the set_false_path command pin within the set
number of cycles (defined by `CYCLE in the define macro). In the case of the above example, there is a period
that is not the expected operation because there is a Fail judgment more than once. Therefore, make sure that
the selection of the reset signal is appropriate, the SVA checker input to the SIM / HWE environment is
appropriate, and whether the number of cycles is correct.

◼ Limitations

・-hold option is not subject to SVA under this rule. Please confirm the validity of SDC by rule check.
・If set_false_path is specified only with a clock, this rule does not apply to SVA. Please confirm the validity
of SDC by rule check.
 239/257頁
S0005 The pin specified in MultiCyclePath must not transition to <cycle number -1>
Severity RTL Layout I/F STA IP
n/a n/a Error n/a
Category ■consistency □semantics □unclear □TDL □check rule user’s manual

GCA/PTC No applicable rule

LITMUS No applicable rule
ConCert MCP_<Cmd-ID>(_<NUM>)
(Dynamic Simulation）

◼ Description
The verification methods using False path and Multicycle Path SVA are similar. The SVA of this rule verifies
that there is no transition in the specified pin at the time after the signal of Start point transitions on the pin
specified by the set_multicycle_path command on the logic simulation / emulation. If the signal of the specified
pin changes unintentionally on the logic simulation/emulation, there is a discrepancy between the SDC and
the logic simulation/emulation environment. SDC constraints or logic simulation/emulation environment [reset
signal, stable (expected number of cycles of signal transition No applicable rule)] must be reviewed (when
SDC is as designed).

◼ Sample circuit configuration and constraints

When the paths with or without Multicycle Path specified are mixed

## test.sdc. in this case violation.

create_clock -name CLK1 -period 10 -waveform {0 5} [get_ports CLK1]
set_multicycle_path 4 -setup -from [get_clocks CLK1] -through [get_pins AND/Y]

The above set_multicycle_path is specified only with -through option. The expected value of this constraint is
that the signal at the AND Y pin does not change after CLK1 changes. Therefore, for this multicycle path, use
the following SVA and check that there is no signal change of the specified pin.

・ Properties
With this property, except for the period not to be evaluated (RST), after one cycle of the rising edge of the
evaluation clock (CLK), the signal is output for a specific period (FP cycle number -1) on all pins specified by
the false path constraint. ) Can be confirmed not to transition.
property p_mcp_stable_all(CLK, RST, STABLE_COND, SETUP);
@(posedge CLK) disable iff (RST)
##1 !STABLE_COND |=> STABLE_COND[*SETUP-1];
endproperty
 240/257頁
・SVA (assertion) converted from SDC
This SVA is obtained by applying actual clock pins and specified pins to the above properties.

assert property
(p_mcp_stable_all( `TOP_INST.CLK1,`CHK_DISABLE_MCP,$stable(`TOP_INST.AND.Y),4));

`TOP_INST and` CHK_DISABLE_MCP should be defined before SIM/HWE execution using define macro.
・`TOP_INST ： Netlist top hierarchy name
・`CHK_DISABLE_MCP ：Set the reset signal that is an MCP check exclusion condition.
・`CYCLE：Set an arbitrary period specified by the user (period during which the specified pin does not
transition).

SIM/HWE result

SIM(VCS)

"tb.test.MCPM__0_.MCP_1_1", 374 attempts, 14 successes, 18 failures, 1 incompletes

HWE(Palladium)

Checked? Finish Failed Assertion Name

374 14 18 tb.test. MCPM __0_.MCP_1_1

◼ Action
The SVA of false path expects that the set_false_path command pin will not change during the set number of
cycles (defined by `CYCLE in the define macro). In the case of the above example, there is a period that is not
the expected operation because there is a Fail judgment more than once. Therefore, check whether the
selection of the reset signal is appropriate, whether the SVA checker input to the SIM/HWE environment is
appropriate, and whether the number of cycles is correct.
◼ Limitations

・-hold option is not subject to SVA under this rule. Please confirm the validity of SDC by rule check.
・If set_multicycle_path is specified by clock only, this rule does not apply to SVA. Please confirm the validity
of SDC by rule check.
 241/257頁
7.7. Others

7.7.1. set_disable_timing

The set_disable_timing command disables the specified timing arc. Thus, timing analysis is not applied to the
timing path including the disabled route. When a loop due to a combination circuit exists in the design, the tool
automatically determines the disconnection point and disconnects the loop. This disconnection point may vary
with tools. For this reason, engineers should use the set_disable_timing command to explicitly disconnect the
timing arc.

◆ Recommended usage

・ Specify the name of the pin on which you wish to disconnect the timing arc.

Setting example when disconnecting the timing arc from pin H02 to pin N01 of instance cell U3
set_disable_timing -from [get_pins H02] -to [get_pins N01] [get_cells U3]
◆ Recommended example of command description

・ When disconnecting the timing arc on a specific pin, set only the pin name.
set_disable_timing [get_pins <pin name>]

・ When disconnecting the timing arc in a specific instance, indicate the names of the instance and pins (-
from, -to).
set_disable_timing -from <pin name> -to <pin name> [get_cells <instance name>]

◆ Notice

・ When the set_false_path command is used, delay and noise are calculated in the timing analysis.
However, because this set_disable_timing command disables the specified timing arc, timing analysis is
not applied to the specified timing path.
・ Specific library cells (get_lib_cells) and library cell pins (get_lib_pins) can also be specified as objects for
the set_disable_timing command. However, the set_disable_timing command is applied to all instance
cells in the design that uses these library cells. Therefore, unintended timing paths may be deleted (= no
path).
 242/257頁

◆ Supplement
The following provides setting examples.

 Differences in timing path analysis depending on whether the set_disable_timing setting is present
In the following example, when set_disable_timing is not set, the timing paths F1 to F3 and F2 to F3
(Constrained Path) are analyzed. The following describes cases where the set_disable_timing command is
specified.

◼ When set_disable_timing is specified for a pin of an instance cell

When set_disable_timing is applied to I3/A, the timing path is disconnected at this pin and the timing path F1
to F3 is deleted (No Path).

◼ When set_disable_timing is specified for an instance cell

When set_disable_timing is applied to the instance cell I3, all timing arcs (I3/A to I3/Y and I3/B to I3/Y) are
disabled and the timing paths F1 to F3 and F2 to F3 are deleted (No Path).

◼ When set_disable_timing is specified for a pin of a library cell

The set_disable_timing command is set for pin A of the library cell TH2AND2XC of the library RC02BTH2_max.
In this case, set_disable_timing is applied to all cells referencing the specified library cell. In the figure below,
the timing arc (I3/A to I3/Y) is disabled and the timing path F1 to F3 is deleted (No Path).
 243/257頁

◼ When set_disable_timing is specified for a library cell

The set_disable_timing command is set for the library cell TH2AND2XC of the library RC02BTH2_max. In this
case, set_disable_timing is applied to all cells referencing the specified library cell. In the figure below, all
timing arcs (I3/A to I3/Y and I3/B to I3/Y) are disabled and the timing paths F1 to F3 and F2 to F3 are deleted
(No Path).

◼ When set_disable_timing is specified for ports

In the figure below, set_disable_timing is set for the input port D1 and the output port Q1. Before
set_disable_timing is set, timing paths (D1 to F1/DATA and F2/CLK to Q1) are analyzed as effective timing
paths. However, once set_disable_timing is set, these timing paths are deleted (No Path).

◼ When set_disable_timing is specified for a middle hierarchy pin (Prohibited)

In the figure below, set_disable_timing is set for the middle hierarchy pin H1/D. The timing path is disconnected
at this middle hierarchy pin and the timing path F1 to H1/F1 is deleted (No Path).
 244/257頁
◼ When set_disable_timing is specified for a middle hierarchy pin with a branch (Prohibited)
The following figure shows an example where set_disable_timing is set for the middle hierarchy pin. The net
branches at the front of the set_disable_timing definition point. In this case, the timing path (F1 to H1/F1) that
passes through the specified middle hierarchy pin is disconnected, but the timing path (F1 to H1/F2) that
bypasses the specified middle hierarchy pin is not disconnected.

◼ Applying to the timing arc of an instance

The set_disable_timing command is set for the timing arc CLK to DATA (checking of setup timing and hold
timing) of the instance F2. This disables checking of the setup timing and hold timing for the DATA pin of F2.
Therefore, the timing path F1 to F2 has no constraint (No Constrained Path).

◼ Applying to the timing arc of a library cell

The set_disable_timing command is set for the timing arc (B to Y) existing in the cell TH2AND2XC of the library
RC02BTH2_max. With this setting, the timing arc (B to Y) of the cell I3 that references TH2AND2XC is
disconnected and the timing arc F2 to F3 is deleted (No Path).
 245/257頁
7.7.2. Check rules

R0059 Prohibition of specification for the data pin of register

Severity RTL Layout I/F STA IP
n/a Error Error Error
Category □consistency ■semantics □unclear □TDL □check rule user’s manual
GCA/PTC UDEF_FFDataSetDisableTimingObj
LITMUS No applicable rule
ConCert No applicable rule
(Dynamic Simulation）

◼ Description
It is not effective for disable timing that set_disable_timing is specified for the data pin of a register. Therefore,
this rule reports its data pin as an error when set_disable_timing is specified
at the pin of a register.

◼ Sample circuit configuration and constraints

When FF data pin is specified
Even if the FF data pin is specified, f1/CK-> f2/D remains to be analyzed.

set_disable_timing [get_pins f2/D]

f1 f2
D Q D Q
CK CK

CLK ②

GCA/PTC MESSAGE
UDEF_FFDataSetDisableTimingObj :
set_disable_timing command is specified on the data pin of register('cell').
◼ Action
To disable the above path, specify the f2 clock as the start point and the data pin as the end point as shown
below.
set_disable_timing –from CK –to D [get_cells f2]
 246/257頁

8. Appendix
A template file is loaded during SDC checking.
It contains the flag parameters that specify whether to execute check rules and to change severity, and rule parameters that control the rule check specifications. Renesas
Electronics prepares template files corresponding for each design phases.
Table given below shows the relationship between the GCA/PTC rules and the design phases.

Litmus will be added in December 2019.

ConCert is only a method for verification using SVA. The introduction of rule check is undecided.

RUle list of Renesas Template.

RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
The value specified as a Constant logic SDC_CASE_ANALY
S0001 None None n/a n/a n/a Error
value must match the actual behavior SIS
Confirm that the pin specified as SDC_SENSE_ANAL
S0002 None None n/a n/a n/a Error
ClockSense does not transition YSIS
<Clock
Confirm that the settings specified in
Name>___<Additiona
the derived clock (items that can be
S0003 None None l information on the n/a n/a n/a Error
checked with SVA) match the actual
clock>___<checker_t
operation
ype>
The pin specified in FalsePath must FP_<Cmd-
S0004 None None n/a n/a n/a Error
not transition to <cycle number -1> ID>(_<NUM>)
The pin specified in MultiCyclePath
MCP_<Cmd-
S0005 must not transition to <cycle number - None None n/a n/a n/a Error
ID>(_<NUM>)
1>
Prohibition of set_case_analysis
R0001 HIER_001 None None n/a n/a Error Error
definition for the middle hierarchical pin
Prohibition of specification of constant
R0002 UDEF_FixedMuxSetCaseAnalysis None None n/a Error Warning Warning
for all data pins of multiplexer
Clock driven by a constant value or
R0003 CLK_0006 None None n/a Error Info Info
hanging
set_case_analysis Settings Are Not
R0004 CAS_0003 None None n/a Error Error Error
Made to Conflict with Each Othe
 247/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA

R0005 Constrained clock not used as a clock CLK_0021 None None n/a Error Warning Warning

R0005 (Same as above) CLK_0026 None None n/a Warning Warning Warning
Multiple paths exist from the clock pin
R0006 of a sequential cell to different clock CLK_0024 None None n/a Info Info Info
sources
Prohibition of
R0007 create_clock/create_generated_clock CLK_0015 None None n/a Error Error Error
definition for the middle hierarchical pin
A Clock Constraint Is Set to All
R0008 DES_0001 None None n/a Error Error Error
Register Clock Pins
R0008 (Same as above) DES_0002 None None n/a Error Error Error
It Is Specified That All Clocks Are
R0010 Treated as Ideal (before CTS CLK_0034 None None n/a Error Error n/a
Execution)
It Is Specified That All Clocks Are
R0011 Treated as Propagated (after CTS CLK_0033 None None n/a n/a n/a Error
Execution)
A Clock Does Not Converge through
R0012 CLK_0030 None None n/a Error Error Error
More Than One Path
A Clock Is Set to the Point at Which the
R0013 UDEF_ClockSetPointCheck None None n/a Error Warning Warning
Clock Signal Is Generated
Prohibition of overlap between
R0014 create_clock commands on the same UDEF_TransAnotherClock None None n/a Error Error Error
clock network
Clock Waveform Definitions Are Set as
R0016 UIC-068 None None n/a Warning Warning Warning
Clock Constraints
Prohibition of create_generated_clock
R0017 UDEF_GclockMasterPinOnHierPin None None n/a Error Error Error
definition for the middle hierarchical pin
Prohibition of specification of the -invert
option in create_generated_clock that
R0018 CLK_0036 None None n/a Error Error Error
is incompatible with the circuit
configuration
 248/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
Do not specify different value with –
divide_by option of
R0019 create_generated_clock command CLK_0020 None None n/a Error Error Error
from divide ratio which is decided by
the circuit
R0019 (Same as above) CLK_0008 None None n/a Error Error Error

R0019 (Same as above) CLK_0032 None None n/a Error Error Error
A Correct Source Clock Is Specified for
R0020 CLK_0016 None None n/a Error Error Error
a Generated Clock
R0020 (Same as above) CLK_0017 None None n/a Error Error Error
There Is One Delay Calculation Path UDEF_GclockMultiDelayCalcPathChec
R0023 None None n/a Error Warning Warning
for a Generated Clock k
Prohibition of set_clock_latency
R0024 UDEF_ClkLatOnHierPin None None n/a Error Error Error
definition for the middle hierarchical pin
Detection of the clock pin in which
R0025 clock latency is not defined (Before CNL_0005 None None n/a Info Info n/a
CTS)
Source or network latency not defined
R0026 UDEF_VclkSrcLatencyCheck None None n/a Info Info Info
for a virtual clock
Necessary Conditions Are Defined for
R0027 CNL_0005 None None n/a Info Warning Warning
Latency
R0028 A Clock Latency is Set (Before CTS) CNL_0005 None None n/a n/a Info n/a

R0028 (Same as above) CSL_0004 None None n/a n/a Info n/a
The Source Latency Is Set for a
R0029 CSL_0004 None None n/a n/a Info n/a
Generated Clock. (Before CTS)
set_clock_transition should not be set
R0030 CTR_0006 None None n/a n/a n/a Error
on clock in postlayout (After CTS)
Clock transition value set by using
R0031 set_clock_transition is outside TRN_0001 None None n/a Error Error Error
technology bounds
Clock should be set transition time
R0032 CTR_0005 None None n/a Warning Warning n/a
(Before CTS)
 249/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
Prohibition of set_clock_uncertainty
R0033 UDEF_ClkUncOnHierPin None None n/a Error Error Error
definition for the middle hierarchical pin
Uncertainty Is Defined for Clock
R0034 UNC_0003 None None n/a Error Warning Warning
Constraints
Confirm the lack of conditions in the
R0035 UNC_0003 None None n/a Error Warning Warning
definition of uncertainty
Prohibition of set_input/output_delay
R0037 EXD_0008 None None n/a Error Error Error
definition for the middle hierarchical pin
R0037 (Same as above) UDEF_EXD_0008_NoSeqPin None None n/a Error Error Error
Input/Output constraints are incorrect
R0038 UDEF_ZeroValueSetInOutDly None None n/a Error Error Error
relative to a range of clock period
R0038 (Same as above) UDEF_MinusValueSetInOutDly None None n/a Error Error Error
Necessary Conditions Are Defined for
R0040 EXD_0004 None None n/a n/a Error Error
an External Port Constraint Definition
Input/output port not constrained by
R0042 EXD_0001 None None n/a Error Warning Warning
set_input_delay/set_output_delay
R0042 (Same as above) EXD_0002 None None n/a Error Warning Warning

R0042 (Same as above) EXD_0003 None None n/a Error Warning Warning
Check conflicts in the external terminal
R0052 EXD_0009 None None n/a Error Error Error
constraint values
R0052 (Same as above) EXD_0010 None None n/a Error Error Error

R0052 (Same as above) EXD_0013 None None n/a Error Error Error

R0052 (Same as above) EXD_0015 None None n/a Error Error Error
A Required Input or Output Delay Is
R0054 UDEF_InputDelayCheck_0001 None None n/a Error Error Error
Set for All Connected Clock Domains
R0054 (Same as above) UDEF_OutputDelayCheck_0001 None None n/a Error Error Error
set_input_transition must be defined on
R0056 clock ports in postlayout stage (After DRV_0001 None None n/a Info Info Error
CTS)
 250/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
No input transition constraints defined
R0057 DRV_0001 None None n/a Info Info Error
for inputs/inouts
Load on output or inout ports not set or
R0058 CAP_0001 None None n/a Info Info Warning
zero
Prohibition of specification for the data
R0059 UDEF_FFDataSetDisableTimingObj None None n/a Error Error Error
pin of register
Prohibition of set_disable_timing
R0060 definition for the bi-directional middle HIER_001 None None n/a n/a Error Error
hierarchical pin
Specification for cells except simple
R0061 function cell like AND, NAND, OR or CLK_0035 None None n/a n/a Error Error
NOR, etc
Prohibition of specification for the
R0062 Check with report_clock_gating_check None None n/a Error Error Error
different value to the same cell
R0062 (Same as above) UIC-045 None None n/a Error Error Error
Prohibition of specification for cell for
R0063 UDEF_IntegratedCellSetClockGating None None n/a n/a Error Error
exclusive use of clock gating
Prohibition of overlap between timing
R0064 EXC_0014 None None n/a Error Info Info
exceptions commands
R0064 (Same as above) EXC_0015 None None n/a Error Info Info
UDEF_EXC_0014and15_FilterMcpOve
R0064 (Same as above) None None n/a Error Warning Warning
rlap
Prohibition of specification for the
R0067 UDEF_SyncRstSetExceptionTo None None n/a n/a Error Error
asynchronous set or reset of register
Option -from/-to not specified for
R0068 set_false_path/set_multicycle_path UDEF_NoSetFromToFalsePath None None n/a Warning Warning Warning
command
R0068 (Same as above) UDEF_NoSetFromToMultiPath None None n/a Warning Warning Warning
False/multi-cycle path reference points
R0069 EXC_0006 None None n/a Errror Warning Warning
are not connected
R0069 (Same as above) UDEF_InvalidPartialException None None n/a Warning Warning Warning
-through Is Not Used for an Object for
R0071 Which -from/-to Can Be Used in a UDEF_ReportThPointException None None n/a n/a Error Error
Timing Exception Constraint
 251/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
Prohibition of specification for the
R0072 UDEF_SyncRstSetExceptionThrough None None n/a n/a Warning Warning
asynchronous set or reset of register
Prohibition of set_false_path definition
R0073 HIER_001 None None n/a n/a Error Error
for the middle hierarchical pin
set_false_path constraint is specified
R0074 and there exists a crossing among the No corresponding rule None None n/a Warning Warning Warning
clocks
Paths between Clock Domains Are
R0075 Check with report_clock_crossing None None n/a n/a Warning Warning
Specified as a False Path
Prohibition of specification for different
R0077 values to the same path in UDEF_DiffvaluetoPathSetMultiPath1 None None n/a Error Error Error
set_multicycle_path
R0077 (Same as above) UDEF_DiffvaluetoPathSetMultiPath2 None None n/a Error Error Error
set_multicycle_path setup or hold over
R0078 UDEF_InvalidValueMultiPath None None n/a Error Error Error
or under defined
Prohibition of specification for the
R0080 EXC_0008 None None n/a Error Error Error
output pin of cell on clock line
Reporting any set point that is specified
in set_min/max_delay as the start point
UDEF_ReportFromNonClkSetMinMax
R0082 with an object other than the clock to None None n/a Info Warning Warning
Dly
an FF/Latch/hard module or external
input
When the ending point of the timing
constraint path is set to besides a data
UDEF_ReportToNonDataSetMinMaxDl
R0084 pin of FF and an output port, the None None n/a Info Warning Warning
y
setting point specified by -to option is
reported
Inconsistent set_max_delay and
R0086 EXC_0009 None None n/a Errror Error Error
set_min_delay commands
R0086 (Same as above) EXC_0010 None None n/a Info Error Error

R0086 (Same as above) EXC_0011 None None n/a Info Error Error
set_min/max_delay reference points
R0087 EXC_0006 None None n/a Error Warning Warning
are not connected
R0087 (Same as above) UDEF_InvalidPartialException None None n/a Warning Warning Warning
 252/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
Prohibition of set_min/max_delay
R0089 HIER_001 None None n/a n/a Error Error
definition for the middle hierarchical pin
Timing Constraints Are Given to Paths
R0092 UDEF_ComboPath_001 None None n/a Warning Warning Warning
Consisting Only of Combinational Logic
R0092 (Same as above) UDEF_ComboPath_002 None None n/a Warning Warning Warning
No Inconsistent Constraint Is Given to
R0093 Paths Consisting Only of EXC_0009 None None n/a Error Error Error
Combinational Logic
R0093 (Same as above) EXC_0010 None None n/a Info Error Error

R0093 (Same as above) EXD_0014 None None n/a Error Error Error

R0093 (Same as above) EXD_0013 None None n/a Error Error Error

R0093 (Same as above) EXD_0015 None None n/a Error Error Error

R0093 (Same as above) UDEF_ConstUnSelPinOnClkMUX None None n/a Warning Info Info

R0093 (Same as above) UDEF_NoConvClkOnMUX None None n/a Info Info Info
A Combinational Circuit Contains No
R0095 LOOP_001 None None n/a Error Error Error
Timing Loop
When an Object Is Specified, the
R0097 UIC-067 None None n/a Warning Error Error
Object Type Is Explicitly Specified
Prohibition of specification for clock
R0099 UDEF_definedClockMuxSelPin None None n/a Error Error Error
definition to the select pin of MUX
A Clock Does Not Converge through
R0112 CLK_0020 None None n/a Error Error Error
More Than One Path
Wildcard Which Matches Object
R0119 Besides Clock Is Prohibited for UIC-002 None None n/a Error Error Error
set_clock_latency
Prohibition of specification of a clock
R0120 port for a set_clock_uncertainty multi- UDEF_clock_uncertainty_mux None None n/a Error Error Error
clock
set_false_path Must Not Be set to Net
R0121 None None None n/a n/a Error Error
With ‘-through’
 253/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
Set Value to Cell and Clock Pin for
R0122 set_mux_delay or set_min_delay Must UDEF_exception_pin_cell None None n/a Error Error Error
Be Same
Prohibition of set_disable_timing
R0123 definition for the middle hierarchical HIER_001 None None n/a n/a Error Error
cell
A generated clock that has two or more
R0124 clock sources with branches must not UDEF_UndefinedPartClockGene None None n/a Warning Warning Warning
be present
A generated clock of which the master
R0125 clock is a multi-clock must not be CLK_0004 None None n/a Error Error Error
present
Generated clocks must be defined for
R0126 CLK_0004 None None n/a Error Error Error
all master clocks
Care must be taken with respect to
R0127 duplicated -name options for a clock UIC-034 None None n/a Warning Warning Warning
definition
R0127 (Same as above) UIC-065 None None n/a Warning Warning Warning

R0128 Defining constraints in pair EXD_0004 None None n/a Warning Warning Error/info
Inconsistency between min/max option
R0129 EXD_0013 None None n/a Error Error Error
values
R0129 (Same as above) EXD_0015 None None n/a Error Error Error
Prohibition of specification such that
both of -from/-to options are not
R0130 UDEF_NoSetFromToSetMinMaxDly None None n/a Warning Warning Warning
specified in
set_min_delay/set_max_delay_path
Prohibition of specification of
set_min/max_delay that affects other
R0131 EXC_0005 None None n/a Error Error Error
paths by being specified for a point
other than start/end points
Exclusive setting must be made for
R0132 UDEF_ConvClkOnComb None None n/a Warning Warning Warning
convergence clocks
Prohibition of duplicate objects in the -
R0133 UDEF_ExceptionSameThrPoint None None n/a Warning Warning Warning
through timing exception option
 254/257頁
RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
The -start/-end options must be
R0134 specified explicitly for a multicycle path UDEF_NoSetStartEndMultipath None None n/a Warning Warning Warning
between clocks of different frequencies
Note the size relation of skew when
R0135 UNC_0004 None None n/a Warning Warning Warning
using set_clock_uncertainty
R0135 (Same as above) UNC_0005 None None n/a Warning Warning Warning

R0135 (Same as above) UNC_0006 None None n/a Warning Warning Warning
Specified point should not be set to
R0136 jump over the frontward of the UDEF_JumpGclkForSourcePin None None n/a Warning Warning Warning
generated clock definition
Defining constraints in pair
R0137 CNL_0005 None None n/a info Warning Warning
(set_clock_latency)
Defining constraints in pair
R0138 UNC_0003 None None n/a Error Warning Warning
(set_clock_uncertainty)
Generated Clocks from the same
R0139 master clock must be declared CGR_0001 None None n/a Error Error Error
exclusive
The definition of clock exclusive
relationship between parent and child
R0140 CGR_0002 None None n/a Error Error Error
clocks should be eliminated due to
over-setting
Set up an exclusive relationship
R0141 CGR_0003 None None n/a Error Error Error
between non-interfering clocks
Confirm that there is no shortage in the
R0142 setting of exclusive relationship CGR_0004 None None n/a Error Error Error
between clocks
Confirm that there is no error in using
R0143 CGR_0005 None None n/a Error Error Error
the set_clock_groups option
Use the -physically_exclusive option
R0144 between clocks that do not physically CGR_0006 None None n/a Warning Warning Warning
interfere
Confirm that the set_clock_groups
R0145 command is set between clocks of the CGR_0007 None None n/a Warning Warning Warning
same definition location
Use the set_clock_groups command to
R0146 CGR_0008 None None n/a Warning Warning Warning
set the false value between clocks
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RuleI
Rule overview Rule Name Design phase
D
GCA/PTC Litmus ConCert RTL IP Layout STA
STA tool accuracy is difficult to
R0147 CGR_0009 None None n/a Error Error Error
guarantee
Attention to the multiple specification
R0148 order of the -through option of the None None None n/a Error Error Error
timing exception command
Do not mix ideal clock and propagate
R0150 CLK_0019 None None n/a Error Error Error
clock (after CTS execution)

The following RuleID is missing.

R0009 R0015 R0021 R0022 R0036 R0039 R0041 R0043 R0044 R0045 R0046 R0048 R0049 R0050 R0051 R0053 R0055 R0057 R0065 R0066 R0070 R0076 R0079
R0081 R0083 R0085 R0088 R0090 R0091 R0094 R0096 R0098 R0100 R0101 R0102 R0103 R0104 R0105 R0106 R0107 R0108 R0109 R0110 R0111 R0113 R0114 R0115
R0116 R0117 R0118 R0149

* R0081(UDEF_ReportFromClkSetMinMaxDly) and R0083(UDEF_ReportToDataSetMinMaxDly) are obsolete custom rules.

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Revision History
Rev. No. Date Description Approved by Checked by Written by
V2.1.0 2019/11/25 First issue Ishikawa - Yunokuchi
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SDC Description Guideline

Document No.: LLWEB-10067594

Publication Date: November 25, 2019
Published by: Renesas Electronics Corporation

© 2019 Renesas Electronics Corporation. All rights reserved