CS 6210 Fall 2024 Test 1

(120min Canvas Quiz) [Total Points: 98]

OS Structure [21 points]

Spin and Exokernel [10 points]
2. [10 points] Exokernel uses a linear vector of time slots (or time
quantum) to allot time for library OSes executing on top of
Exokernel. Currently there are two library OSes running on top of
the Exokernel.
• OS1 is running a CPU-intensive long running ML training application
• OS2 is running an interactive gaming application

(a) [4 points] What is the best strategy that OS1 and OS2 can take to
schedule these applications on top of Exokernel?

(b) [4 points] Currently OS1 is executing its ML application. Timer goes off.
List the steps taken by Exokernel upon this interrupt.

(c) [2 points] How does Exokernel maintain fairness for CPU time
consumed by library OSes

Microkernel [11 points]

You are evaluating a microkernel-based OS following the principles of the L3
microkernel. The processor architecture on which this OS is running has the
following features:

• A byte-addressable 32-bit hardware address space.

• Paged virtual memory system with a processor register called PTBR that points
to the page table in memory to enable hardware address translation.

• A TLB which DOES NOT support Address space IDs.

• A pair of hardware-enforced segment registers (lower and upper bound of virtual
addresses) which limit the virtual address space that can be accessed by a process
running on the processor. The use of segment registers can be toggled on or off by
the user.

• A virtually-indexed physically-tagged processor cache.

1. [3 points] You are in the midst of an enticing conversation with a

friend when they highlight that to realize the best performance (in
terms of CPU cycles) smaller subsystems should be packed into a
single address space. Do you agree with your friend? Why or why
not?

2. [2 points] (Select all that apply; Note: +x for correct choice; - x for
incorrect choice) Packing multiple small protection domain into
one hardware address space will result in:
Reduced explicit cost on context switch between protection domains
Reduced page faults in the system
Reduced TLB misses
Increased misses in the cache

3. (2 points) For the micro-kernel based OS design, you are

embarking on, give one example of a “mechanism” and one
example of a “policy” in designing the scheduling subsystem.

4. (2 points) (Answer True/False with justification) Since the TLB

does not support address space IDs, the TLB will always need to be
flushed upon a context switch from one protection domain to
another.
5. (2 points) (Select all that apply; Note: +x for correct choice; - x for
incorrect choice)
A context switch from one large protection domain to another will result in:

The TLB needing to be flushed

The cache needing to be flushed
 Changing the PTBR
Implicit costs decreasing

Virtualization [16 points]

Full Virtualization [6 points]
1. [2 points] Assume that in a fully virtualized environment, a guest
OS attempts to change the permissions of a virtual page (say X) to
read only. What actions ensue to make this change happen?
Solution: page table update in the guest OS traps to hypervisor. The hypervisor
updates the permissions in the shadow page table for virtual page X. If the TLB
has entry for Page X, it is modified as well.

2. [4 points] In a fully virtualized environment, consider the

following:

Two VMs are currently running. VM1 has 3 processes running; VM2 has 4
processes running.
Assume the size the hardware page table is 1 MB.

What is the total memory overhead incurred by the Hypervisor for the above
configuration? Show your work for any credit.

Memory Management [10 points]

1. (4 points) There are two guest OSes (OS1 and OS2) running on
top of the hypervisor. Assume that vpn1 of OS1 and vpn2 of OS2
are mapped to the same machine page (mpn1) through VM
oblivious page sharing. A process in OS2 attempts to write to
vpn2. List the actions that ensue as a result.
2. [4 points] A hypervisor uses ballooning mechanism to
allocate/reclaim memory from the VMs, and the memory
management policy it follows is as follows:
50% tax on idle memory of a VM
 Cycle through all VMs with idle memories before double taxing any one VM

Consider the following scenario:

VM1 requests 800 MB of memory from the hypervisor

VM2, VM3, VM4 have respectively 200 MB, 400 MB, and 1 GB of idle
memory

List the steps taken by the hypervisor to satisfy the memory request of VM1.

Parallel systems [43 points]

Shared Memory Machines [6 points]
1. [2 points] Consider a NCC-NUMA architecture for a shared
address space multiprocessor. What guarantees are needed from
the architecture to ensure that it provides sequential consistency
memory model to the programmer?

2. [2 points] Consider a CC-NUMA architecture for a shared

address space multiprocessor. What guarantees are needed from
the architecture to ensure that it provides sequential consistency
memory model to the programmer?
3. [2 points] Consider a shared address space architecture. The
address space is divided into two partitions:
• Partition A is NCC-NUMA

• Partition B is CC-NUMA

What guarantees are needed from the architecture to ensure that it provides
sequential consistency memory model to the programmer?

M.E.Lock [10 points]

1. Consider the following lock algorithm:
 1 while ((L == locked) or (T&S(L) == locked))
2
3 {
4
5 while (L == locked); // spin
6
7 delay (d[Pi]); // different delays for different processors }
8
9 // success if we are here

(a) [1 point] What hardware features and properties does this lock
algorithm require (other than calculating different delays for different
processors)?

(b) [2 points] We need to know which programs are not well-suited to use
this lock. What are the program characteristics that would negatively
impact the program’s performance with this lock algorithm
implementation? In what way does it reduce performance?

(c) [2 points] We need to know which programs are well-suited to use this
lock. What are the program characteristics that would enhance the
program’s performance with this lock algorithm implementation? In what
way does it improve performance?

Consider the ticket lock algorithm from lecture 4 (slide

108):

(a) [2 points] Compared with the lock algorithm with delay in a previous
question, what is the advantage of ticket lock’s different method of
determining the amount of delay? From a programmer’s perspective what
is the added value of this algorithm compared to the lock algorithm with
delay in the previous question?

(b) [1.5 points] What are the downsides of the ticket lock algorithm for
systems with write-update cache coherence? Briefly explain your answer.

(b) [1.5 points] What are the downsides of the ticket lock algorithm for
systems with write-invalidate cache coherence? Briefly explain your
answer.

Barriers [4 points]
2. [4 points] Given the following picture of the dissemination
algorithm, focusing on node P4, what information does P4 know
at the end of round 1? Explain your answer.

Parallel systems – Communication (LRPC) [13 points]

1. [2 points] (Answer True/ False with justification) The kernel
holds two procedure descriptors associated with Server A; one for
procedure ‘foo’ with total number of simultaneous calls set to 5
and the other for procedure ‘bar’ with total number of
simultaneous calls set to 6. Given that these are the only 2
procedures registered by this server, the total number of
simultaneous RPCs that the server can field is max(5, 6) = 6.
2. [11 points] Consider a single processor machine running a client
and server. The client calls a procedure foo on the server with the
following declaration:
void foo(data_structure a, data_structure b);

The server always expects the actual parameters of the call to be in its stack.

Consider the following variables representing average times to complete the

described operations.

T1 : Average time to copy a variable of type data_structure from user space

to kernel space and vice versa.
T2 : Average time to copy a variable of type data_structure from user space
to user space.
T3: Average time the server takes to execute the procedure foo
T4: Average time to switch between user-space domains (averaged over
thread-doctored and normal thread-scheduled workflows).
T5: Average time for a kernel trap and associated validation (averaged over
binding object and non-binding object workflows).
Answer the questions below based on the information and average times
given above. You should give an explanation of the component times that
make up your answer to get any credit. Consider any other time that is not
mentioned above as negligible.

a. [2 point] Calculate the total client wait time after calling the procedure
‘foo’, if the server and client were collocated in the same process.

b. [3 points] Calculate the total client wait time after calling the procedure
‘foo’, if the server and client were two different processes, and the OS does
not optimize the RPC workflow for processes running on the same
machine.

c. [3 points] Calculate the total client wait time after calling the procedure
‘foo’, if the server and client were two different processes, and the OS
optimizes the RPC workflow for processes running on the same machine
(Lightweight-RPC). Note that this is not the first time this client is calling
the procedure ‘foo’ on the server.
d. [3 points] What architectural change is required to further reduce the
total wait time of the client? Calculate the wait time after calling procedure
‘foo’ in this case.

Parallel Systems (Scheduling) [6 points]

1. (6 points) (From Fedarova paper) Consider a multi-threaded
multicore CPU is one which each chip has multiple cores and each
core has multiple hardware threads. The OS chooses the set of
application threads to be scheduled on the hardware threads in
each core. Given that the hardware threads share a single
processor pipeline on the core,
(a) [2 points] What purpose is served by the hardware threads?

(2) [4 points] What should the OS do ensure that processor pipeline is

utilized well? Why?

Parallel System Case Studies [4 points]

1. (4 points) (Tornado) Tornado uses the concept of a “clustered”
object which has the nice property that the object reference is the
same regardless of where the reference originates. However, a
given object reference may be de-referenced to a specific
representation of that object. A processor makes a reference to an
object i. It is not currently in its translation table. Give the steps
involved in helping this processor to access the specific
representation for this object.

[HIDDEN] Potpourri [18 points]

[6 points] Consider the programmer’s intent and the
corresponding code fragment below that they have written to
work on top of DSM software.
Programmer’s intent:
Node N1 Node N2
Modify shared struct A Wait for modification to be complete

Use A

Code fragment:

Node N1 Node N2
Modify(A); Lock (L);

Lock (L) while (Flag == 0) Flag = 1; wait(C, L);

Signal(C); Unlock(L);

Unlock (L); Use (A) ;

(a) [2 points]: The DSM software uses SC memory model. Will the
above program fragment work per programmer’s intent? Why or
Why not?
(b) [2 points]: The DSM software uses RC memory model. Will the
above program fragment work per programmer’s intent? Why or
Why not?
(c) [2 points]: The DSM software is Treadmarks which uses LRC
memory model. Will the above program fragment work per
programmer’s intent? Why or Why not?
1. [2 points] (Answer True/False with justification) “SPIN and
Exokernel are fair in comparing the superiority of their respective
specialization approaches for OS services relative to Mach micro-
kernel.”

2. [2 points] (Answer True/False with justification) In a fully

virtualized environment, the hypervisor uses the Physical Page
Number (PPN) generated by the Guest Operating system to index
into the Shadow Page Table and map it to the corresponding
Machine Physical Number (MPN).

3. [2 points] (Answer True/False with justification. Zero credit

without justification.) “MCS barrier will not work on a NCC-
NUMA architecture.”

4. [2 points] (Answer True/False with justification. Zero credit

without justification.) “The total communication complexity of
dissemination barrier is O(N*Log2N)”

5. [2 points] (Answer True/False with justification. Zero credit

without justification.) “The tournament barrier works with both
shared memory and message passing (i.e., clusters) architectures.”

6. [8 points] I/O ring data structures can be used to facilitate data

transfer between paravirtualized guest OSs and the hypervisor.
Consider a guest OS making a hypercall to the hypervisor to write
some data to disk. The process begins with the guest making the
write request, followed by the hypervisor processing the request
and responding. Finally, the guest consumes this response.
(a)[2 points] What information is conveyed by the guest OS via the I/O ring
data structure when making the write request?

A descriptor of the data to be written, not the data itself. [+2] The student might
also mention that the request contains some metadata describing the write
request, but this is not required.

(b)[4 points] Access to the ring data structure is through several pointers.
For the disk write, describe in order the sequence of pointer modifications
from request production to response consumption. Assume that there is
space in the I/O ring for the Guest OS to enqueue a new request. For each
modification, state: a. who makes the modification (guest or hypervisor). b.
which pointer is modified. c. what the pointer modification is.

Now consider an I/O ring that is used by a paravirtualized guest

OS to send network requests and to receive corresponding
responses. At time 0, the guest enqueues requests A, B, and C in
that order. The hypervisor receives the responses corresponding
to A, B, and C from the network at times shown in the table below:

Response ID Time when response received by hypervisor

A 100 ms
B 10 ms
C 60 ms

(c) [1 point] How long from time zero does it take for the first response to be
available to the guest OS?

(d) [1 point] How long from time zero does it take for the last response to be
available to the guest OS?