IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

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Ultra-Slim Packages
Presented by:
Bernd Appelt
March 7, 2012

001477
 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Outline

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 what is thin or ultra-slim?
 a-S3™
 coreless substrate
 a-EASI™
 summary

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Introduction – Electronic Devices

Cell phone

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iPhone 4 = 9.5 mm
iPhone 4S = 8.8 mm
Galaxy = 11.5 mm
Moto = 8.8 mm
Thickness: < 9.0 mm
SonyEricsson = 8.7mm
HTC = 9.9 mm
iPad = 14.3 mm LG = 12.0 mm
iPad2 = 8.8 mm Nokia = 15.5 mm
Galaxy = 8.6 mm
Moto = 8.8 mm
Tablet PC Blackberry = 10.5 mm

Asus = 8.3 mm
Acer = 12.7 mm
LG = 12.0 mm Thickness < 8.5mm
Lenovo = 11.5 mm
Hannspree = 12.0 mm

Hard Disk Drive

7.0 mm

© 2011 ASE Group. All rights reserved. 001479

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Introduction – Industry Reports

A5 : TMV POP BGA 12x13mm x1.1mm

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Top
PKG Memory die: 75um

0.6mm 4L substrate: 215um

FC die: 115um ( 4.5 mil)

Bottom Bump height: 60um
PKG
1/2/1 substrate: 240um
0.5mm Solder ball height < 80um

PCB

Source: Prismark, Aug, 2011

© 2011 ASE Group. All rights reserved. 001480
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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Introduction – Industry Reports

Qualcomm Snapdragon CPU TMV POP 14x14mmm x1.4mm

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3 Memory Die
0.7mm Top Memory die = 50-60um
PKG
2L, Substrate 130um

FC die = 85um (3.5 mil)

0.7mm 85um
FC bump = 80-85um
Bottom
PKG 4L, Substrate 285um

Solder Ball

Memory Die thickness = 50-60um, with 60um film

Memory Substrate = 2 layer , 130um, with 50um core

Flip Chip Die thickness = 85um

Flip Chip Substrate = 1 / 2 / 1 layer , 285um, with 90um core, 100um laser via
Source: Prismark, Aug, 2011

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Introduction – Industry Reports

Samsung 64G NAND eMMC

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1.2mm
25um
Substrate

125um

•64G NAND: 16 die (16x32G) + Controller

•PKG: 14x18x1.2 mm thickness

•Die: 25um thickness

•Substrate: 2L 125um thickness with 50um core

© 2011 ASE Group. All rights reserved. 001482
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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Introduction – Industry Trends

ITRS Roadmap 2010 Version

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Package Thickness Roadmap

QFN

WLP

PBGA

PBGA

CPU
FCBGA

Lowe-nd Package Thickness : 0.5  0.4  0.3 mm

Highe-nd Package Thickness : 1.2  1.0  0.8 mm

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

JEDEC Definition of Packages

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 Package: getting thinner and thinner
IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

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Thin Packaging

aCSP
aCSP

aS3
aS3
aS3

X-aQFN
U-aQFN
aQFN
aWLP
aWLP

aWLP
aEDSi PoP
aWLP PoP
Bare-die Exposed-die
PoP aMAP PoP
aMAP PoP

XFBGA
UFBGA
WFBGA
VFBGA
LFBGA TFBGA

1.4mm 1.2mm 1.0mm 0.8mm 0.65mm 0.5mm 0.4mm

© 2011 ASE Group. All rights reserved. 001485

 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Trend of PKG Profile vs SBT

Thickness

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1.40 Unit: mm

1.20

1.00
0.36 0.80
0.26 0.65
0.50
0.21

0.17

0.13
0.11
0.10 0.09 (a-S3TM)

LF / TF / VFBGA WFBGA UFBGA XFBGA

Available 2009 2010 2011

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-S3 : Package Outline & X-section

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Package Outline
Total Mold Cap Substrate Ball Stand
BPO
Thickness Thickness (A) Thickness (B) Size Off (C)

0.4 mm Max. 0.2 mm 0.095mm 0.155mm / 0.25 mm 0.08mm Max.

0.5 mm Max. 0.25 mm 0.095mm 0.25mm / 0.3 mm 0.14mm Max.

0.65 mm Max. 0.3 mm 0.095mm 0.25mm / 0.25 mm 0.17mm Max.

0.8 mm Max. 0.45 mm 0.095mm 0.3mm / 0.275 mm 0.23mm Max.

1 mm Max. 0.53 mm 0.095mm 0.35mm / 0.3mm 0.29mm Max.

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-S3 - type substrate process flow

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Fix Cu Foil Pattern Plate Laminate Selective
to Carrier Cu Studs drilled prepreg NiAu Plating

Pattern Cu FVI (Final Routing

Assembly
Foil Visual Inspect) (into strips)

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Process flow
Material issue cu foil

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SM
Cu pillar plating

Ni/Au plating

PP lamination

Alkaline etching

Conformal mask & Laser via

OSP
Pattern plating & Flash etching

© ASE
© 2011 ASE Group.
Group. All rights
All rights reserved.
reserved. 001489 12
ASE Confidential / Security-B
 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

What is a-S3 TM ?
 Single Sided Substrate

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Substrate is made by single side build-up flow

 Traditional technology  a-S3TM technology

 Laser ablation  PP lamination
 Via filled copper plating  Cu pillar plating

© 2011 ASE Group. All rights reserved. 001490

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Design Feasibility—4 : 2L BGA vs. a-S3

Substrate technology – 80um trace pitch

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Max. 3D total
Package Package SBS IO
Layer Pitch wire wire
type size thickness count
length length
Original 2 8x8mm 105um 81 0.4mm 836um 57mm
a-S3 1 8x8mm 95um 81 0.4mm 836um 57mm
a-S3 1 7x7mm 95um 98 0.5mm 836um 57mm
a-S3 Proposal
Original BGA (8x8) Same net list (8x8) New Net list (7x7)

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Design Feasibility—3 : QFN vs. a-S3

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Package Package Ball/ Lead Ball Max. 3D total
 Reduce package size type size count pitch wire length wire length
 Reduce wire length QFN 9x9mm 64 0.5mm 3500um 213 mm

 Enhance the BLR performance LGA (S3) 9x9mm 64 0.5mm 323um 47 mm

 Allow more lead count BGA (S3) 8x8mm 105 0.5mm 323um 47 mm

BGA (S3) 6x6mm 64 0.65mm 1183um 88 mm

QFN
a-S3 option-1

a-S3 option-2

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-S3TM – 1L substrate
 Reliability Test ( in customer site )

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PKG info:
PKG size
Die size
: 5x5x0.6mm, 49io
: 3.6x3.75mm
Pass
Mold cap thickness : 0. 30mm MSL3 / HAST 168 / PCT 168
Substrate thickness : 0.095mm
Solder ball : 0.25mm, LF35 TCT 1000 / HTST 1000

© 2011 ASE Group. All rights reserved. 001493

 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-S3TM – 1L Substrate
 Board Level Test

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Thermal Cycling: Ongoing, due Dec ’09

Drop Test: JEDEC No. (JESD 22-B111)

• Direction: Facing downward
• Test condition: Peak acceleration 1500G,
pulse duration 0.5 ms.
• Test duration: 30 times drop or until 80% failure
(generally)
• Failure criteria: exceed 1000 ohm for
followed by 3 additional such events
during 5 subsequent drops.

Pass
Criteria : 30 drop
1’st failure : 375 drop

© 2011 ASE Group. All rights reserved. 001494

 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Thin Packages – a-S3

 Single Sided Substrate

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Substrate is made by single side build-up flow

 a-S3
 1L - 90µm 90um
500um

Core
 2L - 105µm

 3L - 165µm
Compound
 4L - 230µm 500um
90um
Core Solder
 5L – 300µm Mask

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-S3TM - Multi-Layers Substrate (Coreless)

 Features

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1. Vias anywhere
2. Stacked vias
3. Thin dielectrics
4. Fine trace/space pattern
5. Unlimited layer count
6. Better thermal performance , solid heat spreader at die flag area .

Core with Build-Up Layers Substrate Core-less Substrate

ASE patent pending

© 2011 ASE Group. All rights reserved. 001496 20
 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-EASI Technology Development

( advanced- Embedded Assembly Solution Integration )

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As Is 2011 2012

LGA Type
MCM Type

BGA Type MCM Type

Substrate + Embedded Die = PKG

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-EASI Application

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 Embedded Chip Package
Embedded chip package is single PKG with one chip
embedded, or 2 ~ 3 side-by-side embedded chips.

System-in-Package Modules
The embedding substrate with single die, or several
die/passive embed and surface with I/O pad for die/passive
for other components integration using assembly or SMT
technology. Die / WLP

Passive Passive
component component

Passive
Die
component

© 2011 ASE Group. All rights reserved. 001498

 EDS IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Embedded Chip Package

- Concept

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The concept is to embed thin chips into

substrate build-up layers using well-established
substrate technology. Electrical contacts to the chips are
realized by laser-drilling and metallizing of micro-vias.
 Large batch size processing substitute sequential wire
bonding process.

© 2011 ASE Group. All rights reserved. 001499 23

 EDS IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Real Product Photo

Post D/A

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Post Cu Plating Post Cu Plating
- Via on Die - Via on LF

Post Strip Lamination Si Dummy Die

Post Patterning Post SM

Post Drilling
- Via on Chip

© 2011 ASE Group. All rights reserved. 001500 24

 EDS IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

X-section

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250 um copper foil
100x

Green : Die
Red : L1
Dark green : Laser

die

200x 500x

© 2011 ASE Group. All rights reserved. 001501 25

 EPS IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Embedded Passive / Die Substrate

- Structure & Features

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Passive
Die
component

Features
 Yield enhancement by Known good substrate.

 Prefabricated known good substrate, before die / component embed,

substrate inter-connection and out layer build-up process.

• High density circuit / multiple layer design in base substrate
• The base substrate manufacture by existing panel type production line.
• Following component embedding and out layer processing at embedded line.
 Enable highly integration 3D PKG solution with assembly and SMT
technology.
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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

a-EASI Technology Development

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As Is 2012 2013 2014

Substrate + Embedded Die/Passive = Embedded Substrate

Die / WLP Die / WLP Passive
component

Passive Passive
component component

Die / WLP Passive Passive

component component
Die / WLP Die / WLP Passive Passive
component component

Die

Die

Die / WLP Passive Passive

component component
Die
Die / WLP Die
Passive
component

Passive
Die
component

Die / WLP Passive

Embedded Substrate + ASSY Tech = System Module

© 2011 ASE Group. All rights reserved. 001504
 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

Summary

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 a-S3™ package is qualified and in HVM
 a-S3™ land-less substrate qualified
 5L coreless substrate in package qualification
 a-EASI™ substrates in customer evaluation with
embedded passives and with embedded actives

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 IMAPS International Conference & Exhibition on Device Packaging | March 5-8, 2012 | Fountain Hills, AZ USA

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Thank You
www.aseglobal.com

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