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TECHNICAL NOTE
Reset Synchronization
TN005, File created: 2009-11-07, last modified: 2010-01-24, ver.00 by pb

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Table of Contents
1 2 3 4 Abstract...............................................................................................................................................2 Reset Synchronization Overview........................................................................................................2 No Oscillation on the Reset................................................................................................................2 Conclusions.........................................................................................................................................5 4.1 Oscillations.....................................................................................................................................5 4.2 Metastability...................................................................................................................................6 5 References...........................................................................................................................................6

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Abstract

A good design practice for FPGA design is to synchronize the asynchronous input reset to the clock domain where it will be used before applying the reset itself to the implemented Finite State Machines or other synchronous circuit. This technical note analyzes the reset synchronization circuit with focus on the possibility of the circuit oscillating or going metastable when the asynchronous reset violates the reset removal or recovery parameters of the flip-flop (specified by the FPGA data sheet).

Reset Synchronization Overview

SET

SET

FPGA_Internal_Reset
Global Buffer

CL R

CL R

Reset

Clock
Global Buffer

FPGA_Internal_Clock

Figure 1 - Reset Synchronization circuit

The circuit shown in Figure 1 implements the preferred synchronizer for asynchronous resets in FPGAs [Ref.1] [Ref.2]. This circuit asserts the FPGA_Internal_Reset asynchronously (as soon as the external Reset is asserted the FPGA_Internal_Reset will also be asserted), but deassert it synchronously with the clock, thus avoiding the violation of the reset removal and reset recovery time of the flip-flops used in the rest of the FPGA.

No Oscillation on the Reset

We can prove that the 2nd flip-flop in the chain cannot have oscillations on its output due to the deassertion of the input Reset (whereas the 1st flip-flop can), which could lead to catastrophic errors. The following figure shows the schematic of a D flip-flop with asynchronous Reset and Preset (not used in our example and it is kept to its inactive value).

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Preset

NAND_Pre

NAND_1

clk
NAND_2

Q_inv

D Reset

NAND_3

Figure 2 - D flip-flop implementation with NAND3 gates

The simulation of that circuit shows that: When the Reset signal is released coincidently with the clock and the output does not have to change there are no oscillations (see Figure 3). When the Reset signal is released coincidently with the clock and the output should change there are oscillations (see Figure 4). Note: For illustration purposes the propagation delay of NAND3_1, NAND_2 and NAND_3 is 5 ns, and that of NAND_Pre, Q and Q_inv is 1 ns.

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0ns

50ns

100ns

150ns

200ns

clk D Recovery time Reset Preset NAND_Pre NAND_1

NAND_2 NAND_3 Q Q_inv

Figure 3 - Recovery Violation when output does NOT change

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c lk D R c v ry e o a tim e o e /R m v l e Rst ee P se re t

NN P A D_ re

NN _ A D1

NN _ A D2

NN _ A D3

Q in _ v

Figure 4 - Recovery Violation when output changes

4
4.1

Conclusions
Oscillations

Going back to Figure 1, we can see that the input of the 2nd flip-flop is always set to '0' while the reset is asserted, and that it will not change to '1' until one or two rising edges of the clock after the reset deassertion; this is because the 1st flip-flop is also in reset (and its output is '0'). When the reset is deasserted without violating the removal or recovery time, the output from the 1st flip-flop will not change until the next clock rising edge, passing the '1' attached to its input to the output. If the reset is removed violating the removal or recovery time, the input of the 2nd flip-flop will still see a logic '0' due to the reset-to-output and the propagation time (which adds a delay between the two flipflops), and therefore its output will remain to '0' until the next rising edge or, in the worst case, the one after that (depending on when the 1st Flip-Flop recovers). Fifure 2 shows that the Reset signal only affects the outputs of NAND_1 and NAND_3, and Figure 3 shows that neither of them changes when reset is asserted or deasserted and D is '0'. This means that no glitches can occur due to a change in Reset (when D is '0') because no internal signals will change.

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4.2

Metastability

The output of a flip-flop can go metastable when the reset is deasserted close (or coincident) with the rising edge of the clock and the output to the flip-flop must change (in our example when D is '1'). This means that the output would take an undefined voltage, which could be interpreted as a logic '1' or a logic '0'. The reset-to-output and routing delay between the flip-flops insure that the input of the 2nd flip-flop is always '0' when the reset is deasserted, avoiding the possibility of having a metastability effect. The only remaining doubt is what happens if the 1st flip-flop goes metastable. And the answer is that it depends. If the metastability is resolved before one clock period (minus jitter, minus the 2nd flip-flop set-up, minus the propagation delay) then there is no problem, because the input of the 2nd flip-flop will see a stable value (either '1' or '0') when the clock edge comes. If the metastability is not resolved in that time, then the 2nd flip-flop could go metastable. There are many papers about this topic [Ref.4] [Ref.5] where it is stated that the possibility of a 2nd flip-flop on the chain going metastable when enough slack is provided is almost negligible ("When granted 2 ns of extra settling delay, the problems caused by metastability are almost eliminated, as their MTBF exceeds millions of years" [Ref.4]). Because there is no logic between these two flip-flops the designer should be able to apply constraints to minimize the routing delay, therefore giving the maximum possible slack.

5
[Ref.1] [Ref.2] [Ref.3] [Ref.4] [Ref.5]

References
Clifford E. Cummings and Don Mills, "Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?" SNUG San Jose 2002 Rev 1.1 Steve Kilts, Advanced FPGA Design Architecture, Implementation and Optimization, John Wiley & Sons, Inc., Publication, 2007, pg. 140 - 145. Howard Johnson and Martin Graham, High-Speed Digital Design a Handbook of Black Magic, Prentice Hall PTR, 1993, pg. 123 127. Peter Alfke, "Metastable Recovery in Virtex-II Pro FPGAs" XAPP094 (v3.0) February 10, 2005 Altera, "Understanding Metastability in FPGAs" WP-01082-1.2 July 2009, ver. 1.2

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