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DLD Assignment 2

This document outlines an assignment for a Digital Logic Design course at ITER, SIKSHA 'O' ANUSANDHAN University for B.Tech students. It includes various questions related to gate-level minimization and combinational logic, along with course outcomes and learning levels. The assignment is due on December 3, 2022, and carries a weightage of 20 marks out of 100.

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4 views4 pages

DLD Assignment 2

This document outlines an assignment for a Digital Logic Design course at ITER, SIKSHA 'O' ANUSANDHAN University for B.Tech students. It includes various questions related to gate-level minimization and combinational logic, along with course outcomes and learning levels. The assignment is due on December 3, 2022, and carries a weightage of 20 marks out of 100.

Uploaded by

paradoxbhumi18
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ITER, SIKSHA ‘O’ ANUSANDHAN (Deemed to be

Assignment
University)

Branch Computer Science and Engineering Programme B.Tech


Course Name Digital Logic Design Semester III
Course Code EET1211 Academic Year 2022/Odd
Topic- Gate-level Minimization and
Assignment-2 GP-1
Combinational Logic
Learning Level L1: Remembering L3: Applying L5: Evaluating
(LL) L2: Understanding L4: Analysing L6: Creating

Q’s Questions COs LL

1 CO2 L2

2 CO2 L4

3 CO2 L2

4 CO2 L2

5 CO2 L3

6 CO2 L2
7 CO2 L3

8 CO2 L2

9 CO2 L2

10 CO2 L3

11 CO2 L3
12 CO3 L4

Consider the combinational circuit shown above.


a. Derive the Boolean expressions for T1 through T4. Evaluate the outputs F1 and F2
as a function of the four inputs.
b. List the truth table with 16 binary combinations of the four input variables. Then
list the binary values for T1 through T4 and outputs F1 and F2 in the table.

Design a combinational circuit with three inputs, x, y , and z , and three outputs, A,
B , and C . When the binary input is 0, 1, 2, or 3, the binary output is two greater
13 CO3 L6
than the input. When the binary input is 4, 5, 6, or 7, the binary output is three less
than the input.
Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers. Use block
14 CO3 L6
diagrams
Design a combinational circuit that converts a four-bit Gray code to a four-bit
15 L6
binary number. Write a Verilog dataflow model of the circuit. CO3,CO6
Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a
16 2-to4-line decoder. Use block diagrams for the components. CO3 L6

17 CO3 L6

18 CO3 L3

Write the HDL gate-level description of 4bit priority encoder circuit given below.

19 CO6 L4

20 CO3 L2

Assignment 2 Topic: Gate-level Minimization and Date of Assignment2: Date of Submission:


Combinational Logic 24.11.2022 03.12.2022
Note:
1. assignment carries weightage of 20 marks out of 100
2. Course outcome CO1 to CO2 was covered.

CO1 Able to State and explain different number systems, binary codes
Able to apply the principles of Boolean algebra and Karnaugh map to simplify logic
CO2
expressions and implement it using gates
CO3 Able to Analyse and design various combinational circuits
Course
Outcomes Able to Analyse and design different synchronous and asynchronous sequential
CO4
circuits
Able to Analyse and design various Memory, Programmable Logic circuits and
CO5
register transfer level
CO6 Able to implement various digital circuits using HDL and Standard ICs.

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