Module 1 Dsd
Module 1 Dsd
Module-1
1 Part-1
Part
(Number System)
1*20 + 1+
0*21 +
1*22 + 4+
0*23 +
0*24 +
1*25 32
3710
Binary to Decimal Conversion
Example 1 Convert binary 101112 to decimal
positional powers of 2: 24 23 22 21 20
decimal positional value: 16 8 4 2 1
Ans 101112 = 2310
binary number:
1 0 1 1 1
16 + 4 + 2 + 1 = 2310
Example 2 Convert binary 100112 to decimal
positional powers of 2: 24 23 22 21 20
decimal positional value: 16 8 4 2 1 Ans 100112 = 1910
binary number:
1 0 0 1 1
16 + + +1 =1910
+2
Example 3: Convert binary 1100102 to decimal
positional powers of 2: 25 24 23 22 21 20
decimal positional value: 32 16 8 4 2 1
Ans 1100102 = 5010
binary number: 1 1 0 0 1 0
32+ 16 + 2 = 5010
1(b) Decimal to Binary Conversion
(i) Division Method
Decimal to Binary Conversion
The Division Method:
1) Start with your number (call it N) in base 10
2) Divide N by 2 and record the remainder
3) If (quotient = 0) then stop
else make the quotient your new N, and go back to step 2
The remainders comprise your answer, starting with the last remainder as your
first (leftmost) digit.
In other words, divide the decimal number by 2 until you reach zero, and
then collect the remainders in reverse.
reverse
Converting a decimal number to a number in base r
Positional powers of 8: 82 81 80
Decimal positional value: 64 8 1
Octal number: 3 5 7
Value of 357 = (3 x 64) + (5 x 8) + (7 x 1)
= 192 + 40 + 7 = 23910
Positional powers of 8: 8 3 82 81 80
Decimal positional value: 512 64 8 1
Octal number: 1 2 4 6
Value of 12468 (1 x 512) + (5 x 64) + (0 x 8) + (3 x 1)
= 512 + 320 + 0 + 3 = 83510
In other words, divide the decimal number by 16 until you reach zero, and then
collect the remainders in reverse.
So using 3 bits we can represent values from 0 to 7=8 Digits which are the digits of the Octal
numbering system.
101001102 = 2468
101001102 = 4468
5(a) Binary to Hex Conversion
Binary to Hex Conversion
The maximum value represented in 4 bit is: 24 – 1 = 15
So using 4 bits we can represent values 0 to 15=16 Digits which are the digits
of the Hexadecimal numbering system.
Thus, four binary digits can be converted to one hexadecimal digit.
1 1010 0110
0110 = 6
1010 = A
0001 = 1 (pad empty digits with 0)
Then re-group
group obtained binary number in group of 4 bits
convert from binary to the Hex number system starting on the right
Hex to Octal Conversion
Example 1 : Convert E8A16 to octal
First convert the hex to binary:
(E 8 A )16
1110 1000 10102
111 010 001 010 and re-group
re by 3 bits
Then convert the binary to octal:
7 2 1 2 (starting on the right)
Ans E8A16 = 72128
Answers
xample
-1
(1011.101)2 =(?)10
Ex-2
Conversion of Fractional Part
(N)10 (fractional)= (M)b (fractional)
ecimal to binary
The procedure for converting this is to multiply (N)10 (fractional) by b.
f the resulting product is less than 1, then the most significant (leftmost) digit of the
fractional part is 0.
f the resulting product is greater than 1, the most significant digit of the fractional par
the integer part of the product.
The next most significant digit is formed by multiplying the fractional part of this prod
by b and taking the integer part.
The remaining digits are formed by repeating this process.
The process may or may not terminate.
n general,
Consider the number of integer part of the resulting product
Conversion of Fractional Part
• Weighted
• Non-weighted
• 8 4 2 1 (Binary Coded Decimal)
Weighted: • 24 2 1
• Decimal • 8 4 -2 -1
• Other
• Binary
• Octal
• Hexadecimal
Non-Weighted:
• Gray Code [consecutive number differs by one bit]
• Excess-3 code [8421 CODE+3]
• ASCII code
Gray code
The reflected binary code or Gray code is an ordering of the binary nume
system such that two successive values differ in only one bit (binary digit).
Gray codes are very useful in the normal sequence of binary numbers generat
by the hardware that may cause an error or ambiguity during the transition fro
one number to the next.
ASCII code
• ASCII,, stands for American Standard Code for Information
Interchange
• It's a 7-bit
bit character code where every single bit represents a
unique character.
• In standard ASCII-encoded
encoded data, there are unique values for 12
alphabetic, numeric or special additional characters and control
codes.
Addition Subtraction
Binary Arithmetic:
• Addition
• Subtraction
• Multiplication
• Division
Multiplication
EC203 Digital System Design
Module-1 1 Part-2
Part
(Basics, logic families)
Distributive Law:
x*(y.z)=(x*y).(x*z)
As, x+yz=(x+y)(x+z)
x(y+z)=x.y+x.z
Theorems of Boolean algebra
Duality
F1=xyz’
F2=x+y’z
F3=x’y’z+x’yz+xy
x’y’z+x’yz+xy’
F4=xy’+x’z
Logic Family
Digital IC gates are classified by logic operation and logic family
Each logic family has its own basic circuit based on which digital circuit and
functions are developed
The basic circuit in each logic family is NAND gate or NOR gate
The logic family is named by the components it uses
Different logic families of digital ICs:
peed: Speed of a logic circuit is determined by the time between the application of inpu
nd change in the output of the circuit.
an-in: It determines the number of inputs the logic gate can handle.
oise margin/ immunity: Maximum noise that a circuit can withstand without affecting th
utput.
ower: When a circuit switches from one state to the other, power dissipates.
Transistor-Transistor
Transistor Logic (TTL)
mprovement over DTL
everal sub-families
families were developed based on reduced power consumption, increased s
nd driving capacity
Most basic version of TTL is standard-TTL,
TTL, developed in 1965
Hence, Vout=High
ase-2: When, Vin=high, Q2 is off
Now, VBQ2≈ 5 v
It is sufficient to make Q1 on, hence Q1 is on
Hence, Vout=low
Since, Rc (high) is used, the capacitor charges through a high resistance path, but discha
through very low resistive path [unequal charging and discharging time]
Also, in ON-condition,
condition, both transistor current and capacitor current (discharging) may fl
n BJT leading to its damage
he solution for the second problem:
The combined solution
Method to reduce the turnoff time more for transistor in TTL gate
When a transistor is ON (i.e. in deep saturation), charges get stored near base region
To switch it to cut-off mode (i.e 0 to 1) quickly, these charges need to be removed
Solution: A low cut-in
in voltage diode between base and collector may be used to
divert the stored charges towards collector
his can be achieved by
i) Ge-diode (ii) Schottky Diode
A) Propagation delay
MOS LOGIC FAMILY
Classification of MOS
Enhancement type PMOS
Enhancement type NMOS
Symbols for MOS
[mostly used in enhancement type in digital circuits]
MOS as a resistor
PMOS inverter and NAND gates
Vin
Basic drawbacks of NMOS/ PMOS based design
NMOS is not capable of passing good logic 1 due to
threshold voltage effect
VOH=VDD-VT,LOAD
VT,LOAD
1
0 VDD-V
VT,LOAD
PMOS is not capable of passing good logic 0 due to threshold
voltage effect
S
Vin 0
D
1
-VT,LOAD
-VT,LOAD
Solution: Pseudo NMOS
EXAMPLE: NMOS GATE IMPLEMENTATION
XOR GATE
EC203 Digital System Design
Module-1
1 Part-3
Part
(VHDL)
It allows the user to define data types. It does not allow the user to define
data types.
It supports the Multi-Dimensional It does not support the Multi-
array. Dimensional array.
It allows concurrent procedure calls. It does not allow concurrent calls.
A mod operator is present. A mod operator is not present.
Unary reduction operator is not Unary reduction operator is present.
present.
It is more difficult to learn. It is easy to learn.
hardware description language allows a digital system to be designed and debugged a
higher level of abstraction than schematic capture with gates, flip-flops, and standar
MSI building blocks. The details of the gates and flip-flops do not need to be handle
uring early phases of design.
ext, a designer moves into specific realizations of the design. A design can be implemen
several different target technologies (next slide).
slide) It could be a completely custom IC o
uld be implemented in a standard part that is easily available from a vendor.
o most common target technologies nowadays are FPGAs and ASICs. The initial steps in
ign flow are largely the same for either realization.
realization Toward the final stages in the des
w, different operations are performed depending on the target technology. This is indica
igure 2-1. The design is mapped into specific target technology and placed into spe
ts in the target ASIC or FPGA. The paths taken by the connections between compone
decided during the routing. If an ASIC is being designed, the routed design is used
erate a photomask that will be used in the IC manufacturing process. If a design is to
lemented in an FPGA, the design is translated to a format specifying what is to be don
ous programmable points in the FPGA.
FPGA is a device that contains a matrix of re-configurable gate array log
cuitry. When a FPGA is configured (say, by VHDL), the internal circuitry
nnected in a way that creates a hardware implementation of the softwa
plication.
Basics of VHDL
Source: https://www.tutorialspoint.com/vlsi_design/vlsi_design_vhdl_introduction.htm
Video: https://www.youtube.com/watch?v=BDq8
https://www.youtube.com/watch?v=BDq8-QDXmek
VHDL Data type
ata types used are namely, STD_LOGIC and BIT, as well as their vector form
TD_LOGIC_VECTOR and BIT_VECTOR.
BIT_VECTOR
IT
he BIT data type can only have the value 0 or 1. When assigning a value of 0 o
a BIT in VHDL code, the 0 or 1 must be enclosed in single quotes: '0' or '1’.
IT_VECTOR
he BIT_VECTOR data type is the vector version of the BIT type consisting of two
ore bits. Each bit in a BIT_VECTOR can only have the value 0 or 1.
When assigning a value to a BIT_VECTOR, the value must be enclosed in dou
uotes, e.g. "1011" and the number of bits in the value must match the size of
IT_VECTOR.
VHDL Data type
TD_LOGIC
he STD_LOGIC data type can have the value X, 0, 1 or Z. There are other values that this dat
ype can have, but the other values are not synthesizable – i.e. they can not be used in VHD
ode that will be implemented on a CPLD or FPGA.
FPGA
hese values have the following meanings:
X – unknown
0 – logic 0
1 – logic 1
Z – high impedance (open circuit) / tristate buffer
When assigning a value to a STD_LOGIC data type, the value must be enclosed in single quotes
X', '0', '1' or 'Z’.
TD_LOGIC_VECTOR
he vector version of the STD_LOGIC data type. Each bit in the set of bits that make up the vecto
an have the value X, 0, 1 or Z.
When assigning a value to a STD_LOGIC_VECTOR type, the value must be enclosed in doubl
uotes, e.g. "1010", "ZZZZ" or "ZZ001". The number of bits in the value must match the size of th
TD_LOGIC_VECTOR.
Waveforms