This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LES.2015.2499207, IEEE
Embedded Systems Letters

A New XOR-Free Approach for

Implementation of Convolutional Encoder
G. Purohit, Member, IEEE, K. S. Raju, V. K. Chaubey, Member, IEEE

Abstract— This letter presents a new algorithm to construct an WCDMA and the other wireless standards. The Algorithm
XOR-Free architecture of a power efficient Convolutional description, its HW implementation and outcome of the
Encoder. Optimization of XOR operators is the main concern
results are presented in the following subsections.
while implementing polynomials over GF (2), which consumes a
significant amount of dynamic power. The proposed approach
completely removes the XOR-processing operation of a chosen II. Algorithm Design and Implementation
non-systematic, feed-forward generator polynomial and reduces
the logical operators, thereby the decoding cost. Hardware Convolution operation is realized using a deterministic finite
(HW) implementation of the proposed design uses Read-only state machine (DFSM). Its hardware implementation requires
memory (ROM) with a pre-processed addressing operations to a combinational circuit and memory elements. The discrete
reduce ROM size by nearly 50%. The results of the new
convolution for the encoded sequence (CJ) can be expressed
architecture reduce the dynamic power up to 21.4% and HW
cost up to 15% with lesser design complexity as compared to in terms of information sequence (II) with the generator
conventional method. The Hardware co-simulation of the sequences (GI) by the following equation,
architecture is first validated and then implemented with Xilinx
Virtex-V FPGA. (1)

Index Terms—Convolutional Codes, Common Subexpression Further Shift register (SR) based realization of (1) for
Elimination, Finite State Machine, Forward Error Correction, encoded sequence (Cjβ) depends upon the length (L) of SR,
FPGA, HDL, Modulo Adder. the present input Ij and M previous input blocks [I j−1, ··, Ij−M]
to yield (2).
I. INTRODUCTION
Data transmission reliability and stringent QoS are two main (2)
requirements of modern 3GPP and 3GPP2 standards over
unreliable wireless channels. These standards require to The shift register, α Є for each bits of the input and
develop and innovate efficient, cost effective forward error only memories for which are connected to adder β.
correction (FEC) codes for the mobile equipment [1-2]. The (2) is used to realize a CDMA2000 Convolutional
Among the conventional FECs, the Convolutional codes are Encoder with g0(x) = (753)8 and g1(x) = (561)8 as generator
usually preferred over Block codes due to its economical soft polynomials, K=9 and code rate k=1/2 as shown in Fig. 1.
decoding capability and inherent higher coding gain [3]. The
error correction capabilities of such codes rely upon its
Constraint length (K) and maximum free distance (dfree) [4].
The key operation of convolution is multiplication, which is
implemented using shifts and adds. Usually multiple addition
operations, increase complexity and consumes a significant
amount of dynamic power [5-7]. Hence the mitigation of
such complexities by reducing the number of logical
operators is the prime focus in the encoder design. Common
Subexpression Elimination (CSE) methods have been used to Fig. 1 Conventional Convolutional Encoder for CDMA-2000. [4]
eliminate such redundant computation using the most
common bit pattern to optimize the XOR count [8-9]. A deterministic finite automaton of convolution transducer
consists of a finite set of input symbols alphabet (Σ), output
This letter proposes a novel algorithmic approach that finds alphabet Γ, a finite set of states (S), Start state (S0 ∈ S),
an XOR-Free processing architecture for non-systematic, Transition function (δ: S × Σ → S) and the output function ω.
feed-forward Convolutional encoder polynomial represented These six-tuple symbols along with (1) & (2) are used to
over GF (2). However, some concatenated codes such as describe the algorithm 1.
turbo code demands systematic and feedback generator
polynomial over GF (2). In this paper effective The proposed algorithm can be summarized as follows,
implementation of non-recursive convolutional codes is
Step I: Assignment: Assign the information bit as logic ‘0’,
focused. The approach completely replaces modulo-2 based
for all possible encoder states (S), whose next state follows
realization of a standard GF (2) based polynomial into a previous state incremented by one. Compute the output
ROM with parity bits as its elements. The ROM based response using basic convolution process. The encoded
architecture provides ease in FPGA implementation with an output with its encoding states is then arranged in a tabular
additional feature of dynamic reconfiguration. The algorithm form.
is successfully applied with different code rate and constraint
length for CDMA2000, Step II: Grouping: Group the encoder states based on their
1

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LES.2015.2499207, IEEE
Embedded Systems Letters

similar encoded output (Γ).

This architecture includes SR with K-1 memory elements
Step III: Decomposition: Splits the encoder state assignment and multiplexers to decode the encoded sequences from the
bits into two subparts. The First is a Row Tag (RT) as most ROM. Here a 32:1 MUX is used to select new RT from one
significant bits and Column Tag (CT) as the least significant of its inputs in accordance with isomorphic states of table 2.
bits. In the second stage a 2:1 MUX is used to process the output
RT = [K – {(k-1) +1)}] Bits (3) of the first MUX in accordance with the input. The output of
second MUX is combined with the CT coming as LSB bits
CT= k-1 Bits (4) of SR to get the final encoded bits.

Step IV: Finding Isomorphs: Finds the isomorph RT pairs

which have same output bits w.r.t CT and then merge them
to create an array (ROM).

Step V: Restoring: To regain the full functionality for any

input bit, i.e. Logic ‘0’ as well as logic ‘1’, the even and odd
concept is used output is flipped.

The first step of the algorithm, finds output response of the

chosen polynomial using C–code. The code assumes an input
bit as static logic ‘0’, for the possible combinations of SR
state and convolve them to compute the encoded output. The
second step is based on grouping of SR states having a
Fig. 2 XOR - Free Convolutional Encoder architecture for CDMA-2000
similar output state with possible values as {00, 01, 10, and standard with generator polynomial g0(x) = (753)8 and g1(x) = (561)8.
11} for code rate ½. This results in four groups, each with 25
states. The third step splits the encoder state assignment bits
The HW cost of the above architecture can be improved by
into two sub-parts RT and CT as shown in table 1.
reducing the ROM size using a pre-processing logic. That
Table 1: It shows the split of encoder state bits in subparts RT and CT. logic is formed by observing anti-symmetric CT relations of
either even or odd row pairs of ROM. The MSB of second
CT stage MUX and input bit are used to develop modified logics
RT 00 01 10 11 of table 4.
000000 00 11 10 01 Table 4: Modified RT-CT for Reduced ROM Architecture.
000001 00 11 10 01
000010 01 10 11 00 IP New RT (1) Mod. RT (1 bit) Mod. CT (2 bits)
000011 01 10 11 00 0 0
     0 1
111111 01 10 11 00 1 0
1 1
The isomorphic states, observed in the table 1 are merged
into four different groups with the new RT as given in table This logic reduces a sixteen element ROM into an eight
2. Using table 1 and 2, the array of table 3 is formed and elements which consumes lesser power and improves
implemented as ROM, as shown in Fig. 2. propagation delay. The modified architecture uses 4:1 MUX
at the second stage as shown in Fig. 3. This ROM based
Table 2: Assignments of New RT for the Isomorphic RT-CT groups. architecture can be reconfigured by modifying polynomial of
same constraint length and code rate.
New RT Isomorph states (in Decimal)
00 0,1,14,15,22,23,24,25,34,35,44,45,52,51,58,59
01 2,3,12,13,20,21,26,27,32,33,46,47,54,55,56,57

10 4,5,10,11,18,16,28,29,38,39,40,41,48,49,62,63

11 6, 7, 8, 9,16,17,30,31,36,37,42,43,50,51,60,61

Table 3: Array with new RT assignments based on Isomorphs.

CT 00 01 10 11
New RT
00 00 11 10 01 Fig. 3 Reduced Rom XOR-Free Architecture for CDMA-2000 Standard.
01 10 01 00 11
10 01 10 11 00 The algorithm is further tested for CDMA2000 with
11 10 01 00 11 generator polynomials g0(x) = (557)8, g1(x) = (663)8 and g2(x)
2

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LES.2015.2499207, IEEE
Embedded Systems Letters

= (711)8 having k=1/3, K=9. The table 5 assigns RT to the Figs. 4 and 5 respectively. The Power estimation relies
isomorphic states. The Isomorphs are extracted by the states equally upon signal and logic power, IO activity and the
formed by combining the RT and MSB of CT i.e. first 6 bits clock toggling rate. It is interesting to note that a significant
of the shift register. Further the RT is modified using the reduction of Clock Domain Power (CDP) up to 38% for
logics of table 6 and results in the array of table 7. The table k=1/2 is achieved. Thereby improving the overall DPC up to
7 is implemented as a ROM. 21.4% as is evident from Fig. 4. However, as code rate
reduces to k=1/3, the CDP reduces to 1.06% leaving the
Table 5: Assignments of RT for the Isomorphic RT-CT groups. overall DPC to only 5% as depicted in the Fig. 5. The
resource utilization for new architecture has been computed
RT Isomorph states (in Dec.) for different rates as reported in the Tables 8 & 9. It is
000 0,13,18,31,39,42,53,56 inferred from the tables that the proposed architecture claims
001 1,12,19,30,38,43,52,57 15% improvement in the HW area for k=1/3 whereas it is
10% for k=1/2. It is observed from the above results that for
010 4,9,22,27,35,46,49,60
a given constraint length, the decrease in code rate improves
011 5,8,23,26,34,47,48,61
the HW cost significantly as compare to the power and delay,
100 3,14,17,28,36,41,54,59 whereas an increase in code rate improves the dynamic
101 2,15,16,29,37,40,55,58 power and the delay as compare to the area.
110 7,10,21,24,32,45,50,63
111 6,11,20,25,33,44,51,62 Table 8: Comparison of Resource Utilization for the Architectures.

Table 6: Modified RT-CT for Reduced ROM Architecture. Conventional Reduced ROM
Parameter
Encoder (k=1/2) XOR-FREE
IP RT(2) Mod. RT (2 bits) Mod. CT (2 bits) FFs 12 11
0 0 LUTs 03 03
1 LUT-FF Pairs 13 11
0
BUFG/BUFGCTRLs 01 01
1 0
Fmax (MHz) 444.6 585.5
1 1

Table 7: Array with new RT assignment based on Isomorphs

CT 00 01 10 11
New RT
00 000 111 110 001
01 100 011 010 101
10 010 101 100 011
11 101 001 000 111
Fig. 5 Comparison of Dynamic power consumption for two different
III. Results architectures for k=1/3 with 1000 ns run at 500 MHz clock frequency.

Table 9: Comparison of Resource Utilization for the Architectures.

The modified Reduced ROM XOR-Free architecture is
implemented on Xilinx Virtex-5 Genesys Board using HDL
Conventional Reduced ROM
code. The implementation provides an improvement up to Parameter
Encoder (k=1/3) XOR-FREE
32% in propagation delay as compared to conventional FFs 14 12
architecture. The Xilinx XPower Analyser is used to estimate LUTs 04 04
the dynamic power of system using a test stimuli with LUT-FF Pairs 15 12
random input sequence of 1000 ns clocking at 200 MHz & BUFG/BUFGCTRLs 01 01
500 MHz. The dynamic activity at different levels viz. Fmax (MHz) 564.0 600.2
Signal, IOs, Logic and Clock Domain is calculated and
compared for different encoder architectures. Usually the size of the hardware grows with the increment of
constraint length (K), however, for the same K, the
consumable area can be reduced with the lower k and the
appropriate chosen generator polynomials. The present
algorithm is validated up to K=9 for 3GPP and 3GPP2
standards and claims a significant improvement in the
performance.

IV. Conclusion

The letter addresses the problem of optimization of modulo-2

Fig. 4 Comparison of Dynamic power consumption for two different adder and proposes a novel algorithm to implement XOR-
architectures for k=1/2 with 1000 ns run at 200 MHz clock frequency. Free architecture for Convolutional Encoder. The approach
reduces the standard polynomial into a ROM and eases the
The estimated Dynamic Power Consumption (DPC) under FPGA implementation. The architecture is successfully
above constrains for k=1/2 and k= 1/3 have been depicted in tested for 3GPP and 3GPP2 wireless standards.
3

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LES.2015.2499207, IEEE
Embedded Systems Letters

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Gaurav Purohit received his B.E degree

in ECE from Rajasthan University in
2006 and M.E. in communication
system in 2010 from BITS, Pilani. He is
currently pursuing his PhD degree in
Department of EEE, BITS, Pilani, as a
Senior Research Fellow, CSIR. His
research interests include Reconfigurable and Energy
efficient digital baseband architectures, Wireless
communication and Digital design with FPGAs.

Prof. Vinod Kumar Chaubey received

his master’s degree with specialization
in Electronics & Radio Physics and PhD
Degree in the field of Fiber optics
communication from BHU, Varanasi,
India in 1985 and 1992 respectively. Dr.
Chaubey joined BITS, Pilani in 1994 and presently working
as Professor in the Department of EEE. His research interest
include Wireless Communication, Embedded system, and
Optical Communication Network Design.

Dr. Kota Solomon Raju has received

the Bachelor of Engineering degree in
1997 from Andhra University, Master
of Engineering in 2003 from BITS
Pilani and Ph.D. in 2008 from
Department of ECE, IIT Roorkee. He is
currently working as Principal Scientist
in Digital Systems Group, CSIR- CEERI, Pilani, Rajasthan,
India. His research interest include on reconfigurable
computing with FPGAs, embedded systems design,
hardware/software co-design, parallelizing applications,
customized computing, high-level synthesis.

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