Lecture-03

Microprocessor
ESE PYQs Part-03
Question-01
How many times will the following loop be executed?
LXIB 0010H
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
Select the correct answer using the code given below:
(a) 10
(b) 100
(c) 16
(d) 15
[ESE-2006]
Question-02
In 8085, the DAA instruction is used for

(a) Direct Address Accumulator

(b) Double Add Accumulator

(c) Decimal Adjust Accumulator

(d) Direct Access Accumulator

[ESE-2006]
Question-03
Consider the following statements:
1. Indirect addressing is not possible for 1/0 mapped I/O port
addresses
2. Pointers cannot be used to access memory mapped I/O
addresses
3. Fewer machine instructions can be used with I/O mapped I/O
addressing as compared to memory mapped I/O addressing
4. With an 8085 microprocessor, one can access at the most 512
devices with unique addresses using I/O mapped I/O addressing
Which of these statements are correct?
(a) 1, 2 and 3
(b) 2 and 4
(c) 3 and 4
(d) 1 and 3
[ESE-2006]
Question-04
Which one of the following instructions is a 3-byte instruction?

(a) MVI A

(b) LDAXB

(c) JMP 2050

(d) MOV A, M

[ESE-2006]
Question-05
Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085
microprocessor?

(a) It points to top of the stack

(b) It is UP/DOWN counter

(c) It is automatically initialized to 0000 H on power-on

(d) It is a 16-bit register

[ESE-2007]
Question-06
On execution of the following segment of instructions in sequence
MVI A, 91H
XRI 91H
Which one of the following is correct?
(a) Content of accumulator is 00 H . Carry, Auxiliary Carry and
Zero flag set to 0, 1 and 0 , respectively.
(b) Content of accumulator is 91 H. Carry, Auxiliary Carry and
Zero flag set to 0,0 and 1 , respectively.
(c) Content of accumulator is 00H. Carry, Auxiliary Carry and Zero
flag set to 0,0 and 1 respectively
(d) Content of accumulator is 91 H. Carry Auxiliary Carry and
Zero flag set to 0, 1 and 0 respectively
[ESE-2007]
Question-07
Read the following Assembly Language Program Segment of 8085 Micro-
processor:
LXI H, 2501 H
MOV A, L
ORI FOH
MOV L, A
MOV A, H
ANI FOH
MOV H, A
HLT
What are the contents of A,H and L registers after executing the above set of
instructions in sequence?
(a) Contents of A, H and L registers are 25, 20 and F1, respectively
(b) Contents of A, H and L registers are 05, 25 and 01, respectively
(c) Contents of A, H and L registers are 20, 20 and F1, respectively
(d) Contents of A, H and L registers are 25, 05 and 01, respectively
[ESE-2007]
Question-08
Assertion (A): A subroutine is a program written separately from
the main program to perform a function that occurs repeatedly in
the main program.

Reason (R): A subroutine can be called by a CALL instruction.

(a) Both A and R are true and R is the correct explanation of A

(b) Both A and R are true but R is NOT the correct explanation of A

(c) A is true but R is false

(d) A is false but R is true

[ESE-2007]
Question-09
The content of the Program Counter of an intel 8085 A
microprocessor specifies which one of the following?
(a) The address of the instruction being executed
(b) The address of the instruction executed earlier
(c) The address of the next instruction to be executed
(d) The number of instructions executed so far
[ESE-2008]
Question-10
In an Intel 8085 A, what is the content of the Instruction Register
(IR)?
(a) Op-code for the instruction being executed
(b) Operand for the instruction being executed
(c) Op-code for the instruction to be executed next
(d) Operand for the instruction to be executed next
[ESE-2008]
Question-11
Match List-I (Feature of instruction) with List-II (Instruction) and select the
correct answer using the code given below the lists:
List-I
A. Maskable interrupt
B. Signal
C. Instruction
D. Memory location 002 CH
List-II
1. RST 5.5
2. XTHL
3. SID
4. RST 6.5
Codes:
A B C D
(a) 4 1 2 3
(b) 2 3 4 1
(c) 4 3 2 1
(d) 2 1 4 3
[ESE-2008]
Question-12
The stack pointer of an 8085 A microprocessor contains ABCD H .
PUSH PSW
XTHL
PUSH D
JMP EC75H
At the end of the execution of the above instructions, what would
be the content of the stack pointer?
(a) ABCB H
(b) ABCA H
(c) ABC9 H
(d) ABC8 H
[ESE-2008]
Question-13
If the HLT instruction of an Intel 8085A microprocessor is executed

(a) the microprocessor is disconnected from the system bus till the
RESET is pressed.

(b) the microprocessor halts the execution of the program and

(c) the microprocessor enters into a HALT state and the buses are
tri-stated.

(d) the microprocessor reloads the program counter from the

[ESE-2008]
Question-14
The contents of Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be

(a) 2 FFEH

(b) 2 FFFH

(c) 3000 H

(d) 3001 H

[ESE-2008]
Question-15
Carry flag is not affected after the execution of

(a) ADD B

(b) SBB B

(c) INR B

(d) ORA B

[ESE-2008]
Question-16
The addressing mode used in the instruction JMP F347 H in case of an
Intel 8085A microprocessor is which one of the following?

(a) Direct

(b) Register-indirect

(c) Implicit

(d) Immediate

[ESE-2008]
Question-17
Which one is the indirect addressing mode in the following
instructions?

(a) LXIH 2050 H

(b) MOV A, B

(c) LDAXB

(d) LDA 2050 H

[ESE-2008]
Question-18
In an instruction of 8085 microprocessor, how many bytes are
present?

(a) One or two

(b) One, two or three

(c) One only

(d) Two or three

[ESE-2009]
Question-19
Match List-I (Instruction code) with List-II (Addressing mode) and select the
correct answer using the code given below the lists:
List-I
A. JUMP 2021 H
B. LDAX B
C. IN 10 H
D. RLC
List-II
1. Direct addressing
2. Immediate addressing
3. Indirect Register addressing
4. Implicit addressing
Codes:
A B C D
(a) 4 3 1 2
(b) 2 3 1 4
(c) 4 1 3 2
(d) 2 1 3 4
[ESE-2009]
Question-20
Which one of the following addressing technique is not used in
8085 micro-processor?
(a) Register
(b) Immediate
(c) Register indirect
ത 𝛻(∈
𝛻. ത 𝑉) = −𝜌
(d) Relative
[ESE-2009]
Question-21
When the operand requires for an instruction is stored inside the
processor, then what this addressing mode is called?
(a) Direct
(b) Register
(c) Implicit
(d) Immediate
[ESE-2009]
Question-22
Match List-I (Microprocessor pin) with List-II (Signals on pin) and select the
correct answer using the code given below the Lists:
List-I
A. TRAP
B. HLDA
C. RESET
D. ALE
List-II
1. Interrupt
2. Initializing
3. Enable
4. Memory access
Codes:
A B C D
(a) 1 2 4 3
(b) 3 2 4 1
(c) 1 4 2 3
(d) 3 4 2 1
[ESE-2009]
Question-23
What is the correct 8085 assembly language instruction that stores
the contents of H and L registers into the memory locations 1080 H
and 1081 H respectively?

(a) SPHL 1080 H

(b) SHLD 1080 H

(c) STAX 1080 H

(d) SPHL 1081 H

[ESE-2009]
Question-24
The stack pointer of an 8085 micro-processor is ABCDH . At the
end of execution of the sequence of instructions, what will be the
content of the stack pointer?
PUSH PSW
XTHL
PUSHD
JMP FC70H
(a) ABCBH
(b) ABCAH
(c) ABC 9 H
(d) ABC 8 H
[ESE-2009]
Question-25
An 8085 microprocessor is executing the programme as follows:
MVI A, 20 H
MVI B, 10 H
BACK : NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
(a) 4
(b) 3
(b) 2
(d) 1
[ESE-2009]
Question-26
For which one of the following, the instruction XRA A in 8085
microprocessor can be used?

(a) Set the carry flag

(b) Set the zero flag

(c) Reset the carry flag and clear the accumulator

(d) Transfer FFH to the accumulator

[ESE-2009]
Question-27
MVI A, AAH
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the
above set of instructions in sequence?
(a) AAH and 00H
(b) FFH and 66 H
(c) 00H and 54 H
(d) 00H and 00H
[ESE-2010]
Question-28
The opcode for the instruction "Add Immediately to Accumulator
with carry" in 8085 microprocessor is

(a) ADI

(b) ACI

(c) ADC

(d) ADD

[ESE-2010]
Question-29
The content of the programme counter of an 8085 microprocessor
is

(a) the total number of instructions in the program already

(b) the total number of times a subroutine is called.

(c) the memory address of the instruction that is being currently

(d) the memory address of the instruction that is to be executed

[ESE-2010]
Question-30
Assertion (A) : The port address in IN/Our instruction is 8 bit.
Reason (R) : The address byte is duplicated in machine cycle for
IN/OUT instruction.
(a) Both A and R are true and R is the correct explanation of A
(b) Both A and R are true but R is NOT the correct explanation of A
(c) A is true but R is false
(d) A is false but R is true
[ESE-2010]
 Answer Keys (Q. No. – 01 to Q. No. – 30)
1. C 11. C 21. B
2. C 12. C 22. C
3. D 13. C 23. B
4. C 14. C 24. C
5. C 15. C 25. B
6. C 16. D 26. C
7. C 17. C 27. C
8. B 18. B 28. B
9. C 19. B 29. D
10. A 20. D 30. B
Question-31
LXI SP, 7FFFH
MVI A, 25H
XRI O2H
PUSH PSW
POP H
MOV A, L
ORI 10H
HLT
What are the contents of A, H, L, SP and PSW registers after
executing the above set of instructions? Assume undefined flags
always remain cleared.
(a) 10H,25H,00H,7FFFH,00H respectively
(b) 14H,27H,04H,7FFFH,04H respectively
(c) 14H,25H,00H,7FFFH,04H respectively
(d) 10H,27H,04H,7FFFH,00H respectively
[ESE-2010]
Question-32
If the status of the control lines S1 and S0 is LOW, then 8085
microprocessor is performing

(a) Reset operation

(b) HOLD operation

(c) Halt operation

(d) Interrupt acknowledge

[ESE-2011]
Question-33
The description of a program counter (PC) in 8085 microprocessor
is

(a) An up/down counter

(b) An 8-bit register

(c) Initialized automatically by microprocessor

(d) Used to point to stack memory area

[ESE-2011]
Question-34
While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
(a) The memory address of the instruction that is being currently
executed.
(b) The memory address of the instruction that is to be executed
next.
(c) The number of instructions that have already been executed.
(d) The total number of instructions in the current program still to
be executed.
[ESE-2011]
Question-35
In 8085 microprocessor, during PUSH/PSW operation, stack
pointer is

(a) Decremented by one

(b) Decremented by two

(c) Incremented by one

(d) Incremented by two

[ESE-2011]
Question-36
Assertion (A): STACK is used to temporarily store the data in a
RAM locations specified by the programmer in main program.
Reason (R): PUSH and POP instructions are used to send or
retrieve the data from the STACK.
(a) Both A and R are true and R is the correct explanation of A
(b) Both A and R are true but R is NOT the correct explanation of A
(c) A is true but R is false
(d) A is false but R is true
[ESE-2011]
Question-37
The instruction that exchanges top of stack with HL , pair is

(a) XTHL

(b) SPHL

(c) PUSHH

(d) POPH

[ESE-2012]
Question-38
The following instruction copies a byte of data from the
accumulator into the memory address given in the instruction

(a) STA address

(b) LDAX B

(c) LHLD address

(d) LDA address

[ESE-2012]
Question-39
Tho instruction PCHL, in 8085 is used for

(a) Load PC with contents of HL.

(b) Load HL with contents of memory location pointed by PC.

(c) Load HL with contents of PC.

(d) Load PC with the contents of memory location pointed by HL

[ESE-2012]
Question-40
The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a
frequency of 2.5 MHz , how long is an instruction cycle?
(a) 2.8 s
(b) 2.5 ns
(c) 2.8 ns
(d) 2.8μs
[ESE-2013]
Question-41
What is content of accumulator of 8085μP after the execution of
XRI F0 H instruction?
(a) Only the upper nibble of accumulator is complemented
(b) Only the lower nibble is complemented
(c) Only the upper nibble is reset to zero
(d) Only the lower nibble is reset to zero
[ESE-2013]
Question-42
A software delay subroutine is written as given below:
DELAY: MVI H, 255 D
MVI L, 255 D
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
(a) 255
(b) 510
(c) 65025
(d) 65279
[ESE-2013]
Question-43
The content of accumulator are 70 H. Initially all flags are zero.
What will be values of CY and S after executing instruction RLC?
(a) CY=0 and S=0
(b) CY=1 and S=1
(c) CY=1 and S=0
(d) CY=0 and S=1
[ESE-2013]
Question-44
The difference between 8085 instructions RST n and PCHL is

(a) RST n is equivalent to a sub-routine call while PCHL is

(b) RST n uses direct addressing while PCHL uses register indirect
addressing.

(c) RST n is a software interrupt while PCHL simulates a hardware

(d) RST n resets the processor while PCHL restarts the processor.

[ESE-2013]
Question-45
The following program starts at location 0100 H
LXI SP, 00FFH
LXIH, 0107H
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches
0107 H is
(a) 20 H
(b) 02 H
(c) 00 H
(d) FF H
[ESE-2013]
Question-46
Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
(a) 00H
(b) F0H
(c) 0FH
(d) FFH
[ESE-2013]
Question-47
It is desired to multiply the numbers 0 AH by OB H and store the result
in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, 00H
Loop; ________
________
________
HLT END
The sequence of instruction to complete the program would be
(a) JNZ LOOP; ADD B, DCR C
(b) ADD B; JNZ LOOP; DCR C
(c) DCR C; JNZ LOOP; ADD B
(d) ADD B; DCR C; JNZ LOOP
[ESE-2013]
Question-48
Assume that the accumulator and the register C of 8085
microprocessor contain respectively FOH and OFH initially. What
will be the content of accumulator after execution of instruction
ADD C ?

(a) 00 H

(b) FF H

(c) EF H

(d) FE H

[ESE-2013]
Question-49
Statement (I): Program counter is a register the contains the
address of the next instructions to be executed
Statement (II): IR (Instruction Register) is no accessible to
programmer.
(a) Both Statement (I) and Statement (II) are individually true and
Statement (II) is correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) individually true but
Statement (II) is not for correct explanation of Statement (I).
(c) Statement (I) is true but Statement (II) is false.
(d) Statement (I) is false but Statement (II) is true.
[ESE-2013]
Question-50
With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
(a) 1 and 2 only
(b) 2 and 3 only
(c) 1 and 3 only
(d) 1, 2 and 3
[ESE-2014]
Question-51
In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
(a) Direct addressing
(b) Register addressing
(c) Indirect addressing
(d) Immediate addressing
[ESE-2014]
Question-52
Which of the following 8085 instruction will require maximum T-
states for execution?

(a) XRI byte

(b) STA address

(c) CALL address

(d) JMP address

[ESE-2014]
Question-53
How many machine cycles are required by STA instruction?
(a) 2
(b) 3
(c) 4
(d) 5
[ESE-2014]
Question-54
Which of the following instructions is closes match to the
instruction POP PC?
(a) RET
(b) PCHL
(c) POP PSW
(d) DAD SP
[ESE-2014]
Question-55
LOADER is a program that
(a) loads the memories and generates a hex file
(b) loads the hex file and coverts to the executable file
(c) loads the COM file and generates the binary code
(d) loads English like command and generates the binary code
[ESE-2014]
Question-56
Which of the following data transfer is not possible in
microprocessor?

(a) Memory to accumulator

(b) Accumulator to memory

(c) Memory to memory

(d) I/O device to accumulator

[ESE-2014]
Question-57
Statement (I): Branch instructions in a microprocessor are used to
change the sequence of program.
Statement (II): All logical instructions are branch instructions.
Codes:
(a) Both Statement (I) and Statement (II) are individually true and
Statement (II) is the correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) are individually true but
Statement (II) is not the correct explanation of Statement (I).
(c) Statement (I) is true but Statement (II) is false.
(d) Statement (I) is false but Statement (II) is true.
[ESE-2014]
Question-58
When a program is being executed in an 8085 microprocessor, its
program counter contains
(a) the memory address as the instruction that is to be executed
next.
(b) the memory address of the instruction that is being currently
matched.
(c) the total number of instructions in the program being executed.
(d) the number of instructions in the current program that have
already been executed.
[ESE-2015]
Question-59
A 'DAD H' instruction is the same as shifting each bit by one
position to the
(a) left
(b) right
(c) left with a zero inserted in LSB position
(d) right with a zero inserted in LSB position
[ESE-2015]
Question-60
Which one of the following statement is correct about 8086?
(a) It is 46 PIN IC and uses 5 V dc supply
(b) It uses 20 lines for data bus
(c) It multiplexes status signals with address bus
(d) It is manufactured using CMOS technology
[ESE-2015]
Question-61
In 8085 microprocessor, the address for 'TRAP' interrupt is
(a) 0024H
(b) 002CH
(c) 0034H
(d) 003CH
[ESE-2015]
Question-62
What will be the contents of DE and HL register pairs respectively after
the execution of the following instructions?
LXIH, 2500 H
LXID, 0200H
DAD D
XCHG
(a) 0200H, 2500H
(b) 0200H, 2700H
(c) 2500H, 0200H
(d) 2700H, 0200H
[ESE-2015]
Question-63
Direction flag is used with
(a) String instructions
(b) Stack instructions
(c) Arithmetic instructions
(d) Branch instructions
[ESE-2015]
Question-64
XCHG instruction of 8085 exchanges the content of
(a) top of stack with contents of register pair
(b) BC and DE register pairs
(c) HL and DE register pairs
(d) None of the above
[ESE-2015]
Question-65
Among the given instructions, the one which affects maximum
number of flags is
(a) RAL
(b) POP PSW
(c) XRA A
(d) DCR A
[ESE-2015]
Question-66
Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS
instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps. Which of the above
statements are correct?
(a) 1,2 and 3
(b) 1 and 2 only
(c) 1 and 3 only
(d) 2 and 3 only
[ESE-2016]
Question-67
Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then
which of the above interrupt is/are correct?
(a) 1 and 2 only
(b) 1, 2, 3 and 4
(c) 5 only
(d) 1 only
[ESE-2016]
Question-68
The instruction JNC 16-bit refers to jump to 16-bit address if

(a) Sign flag is set

(b) CY flag is reset

(c) Zero flag is set

(d) Parity flag is reset

[ESE-2016]
Question-69
Which one of the following statements is correct regarding the
instruction CMP A?
(a) Compare accumulator with register A
(b) Compare accumulator with memory
(c) Compare accumulator with register H
(d) This instruction does not exist
[ESE-2016]
Question-70
The instruction RET executes with the following series of machine
cycle
(a) Fetch, read, write
(b) Fetch, write, write
(c) Fetch, read, read
(d) Fetch, read
[ESE-2016]
 Answer Keys (Q. No. – 31 to Q. No. – 70)
31. B 41. A 51. C 61. A
32. C 42. D 52. C 62. D
33. C 43. D 53. C 63. A
34. B 44. A 54. A 64. C
35. B 45. C 55. B 65. C
36. B 46. C 56 C 66. B
37. A 47. D 57. C 67. D
38. A 48. B 58 A 68. B
39. A 49. B 59. C 69. A
40. D 50. D 60. C 70. C