Finolex Academy of Management and Technology, Ratnagiri

Department of Computer Science and Engineering (AI & ML)

Class: SE - CSE-AIML / Semester – III (CBCGS) Subject Code

Digital Logic & Computer Organization and
Subject: Architecture CSC304

Academic Year: 2023-24 (SH2023)

…………..Assignment Solution……………….

Sr.No Questions Marks

Q.1 Convert the given decimal number 35 into Gray code, Excess-3 code. 2
Gray Code: First converting Decimal number into Binary (35)10 = (100011)2
Ans:
It is a 6 bit Binary, therefore representing it as B5B4B3B2B1B0
Therefore Gray code will also be represented by 6 bits G5G4G3G2G1G0. The
conversion is as follows:-
G5 = B 5 , G4 = B 5 B4, G3 = B4 B3, G2 = B3 B2, G1 = B2 B1, G0 = B1 B0
B5 B4 B3 B2 B1 B0 1 0 0 0 1 1
G5 G4 G3 G2 G1 G0 1 1 0 0 1 0
(35)10 = (110010)GRAY
Excess-3 Code: To convert the decimal number into XS-3, add (3)10 to each decimal
digit and write that decimal digit in four bit binary.
(35)10 = (3+3,5+3) = (68)10 = (01101000)XS-3
Q.2 Convert the given binary number (1011011.0111)2 into Hexadecimal code, decimal 2
code.
Hexadecimal code: For integer make a group of four binary bits and represent it in
Ans:
Hex and proceed making such groups towards left. Similarly for fractions make a
group of four binary bits and represent it in Hex and proceed making such groups
towards right.
Hence, (1011011.0111)2 = (5B.7)H
Decimal code:- Multiplying each binary bit by its positional weight and adding
them.
(1011011.0111)2 = 1x26 + 1x24 + 1x23 + 1x21 + 1x20 + 1x2-2 + 1x2-3 + 1x2-4
= 64 + 16+ 8 + 2 + 1 + 0.25 + 0.125 + 0.0625
= (91.4375)10
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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Q.3 Convert the given Gray code (101010101) into XS-3 code, Octal code. 2
XS-3 code:- Gray code is to be converted into binary first then to decimal code and
Ans:
then into XS-3 code.
1 0 1 0 1 0 1 0 1

1 1 0 0 1 1 0 0 1
Hence, (101010101)GRAY = (110011001)2
Binary to decimal is (110011001)2 = (409)10
Decimal to XS-3 is by adding 3 to each decimal digit and representing each digit in
a four bit binary:
(409)10 = (7 3 12) = (0111 0011 1100)XS-3
Octal code:- Gray code need to convert into binary and then to Octal by making a
group of three binary bits.
As per the above conversion technique: (101010101)GRAY = (110011001)2
Therefore, (110011001)2 = (631)8
Q.4 Convert the given Hexadecimal Number (DADA)16 into decimal, BCD code. 2
Decimal Code:- Multiply each Hex digit by its positional weight and add them.
Ans:
(DADA)16 = 13x163 + 13x162 + 13x161 + 13x160
(DADA)16 = (56026)10
BCD code:- Hex number need to be converted into Decimal and then to BCD.
Hence as per the above conversion:
(DADA)16 = (56026)10 = (0101 0110 0000 0010 0110)BCD
Q.5 Convert the given BCD number (011010000001) into Binary and Octal code. 2

Ans:
Binary code: BCD number is to be converted into decimal and then to binary.
(011010000001)BCD = (681)10
Since the number is larger converting Decimal to Hea and then Hex to binary.
Conversion of decimal to Hex is is successive division by 16 on the decimal number.

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

16 681
16 42 9
16 2 10=A
16 0 2
(681)10 = (2A9)H = (0010 1010 1001)2
Therefore, (011010000001)BCD = (0010 1010 1001)2
Octal code:- BCD code is to be converted into Decimal, then to Binary and then into
Octal. As per the above calculations:-
(011010000001)BCD = (681)10 = (2A9)H = (0010 1010 1001)2 = (1251)8
Q.6 Implement two input XOR gate using a Multiplexer. 2
Two input XOR gate requires a MUX with two select inputs, S = 2, and we know
Ans:
the relation between select inputs and data inputs of the MUX, which is 2S >= D
hence, 22 = 4, hence using 4:1 MUX.
Truth Table:- Circuit Diagram:
Inputs O/P 0 D0
A B y 1 D1
1 D2 4:1
0 0 0 y
0 D3 Mux
0 1 1
0 EN'
1 0 1 S1 S0

1 1 0 A B
Q.7 Draw a circuit using only NAND gates that will function as an OR gate. 2
OR gate equation is Y = A+ B
Ans: To implement using NAND modifying the above equation without changing its
value and eliminating the OR using De-Morgans Theorem.
Y=A+B=A.B

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Q.8 Implement NAND functionality using only NOR gates. 2

NAND function equation is Y = A.B
Ans:
To implement using NOR modifying the above equation without changing its value
and eliminating the AND using De-Morgans Theorem.
Y=A.B=A + B

Q.9 According to De-Morgans Theorem AND gate and OR gate can be replaced by 2
which gate respectively? Prove it.
Ans:
AND gate is replaced by Bubbled NOR OR gate is replaced by Bubbled NAND
gate. gate.

A B AB A' B' (A'+B')' A B A+B A' B' (A'. B')'

0 0 0 1 1 0 0 0 0 1 1 0

0 1 0 1 0 0 0 1 1 1 0 1

1 0 0 0 1 0 1 0 1 0 1 1

1 1 1 0 0 1 1 1 1 0 0 1

Since the output column AB and Since the output column A+B and
(A'+B')' are the same, Hence proved (A'.B')' are the same, Hence proved OR
AND gate is replaced by Bubbled NOR gate is replaced by Bubbled NAND
gate. gate.

Q.10 Implement z = AB + (C + D)' using only NAND gates and using only NOR gates. 2
To implement the equation using only NAND gates the OR terms in the equation
Ans:
should be eliminated. So modifying the equation without changing its value.

z = AB + (C + D)'
z = AB .(C D)

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

To implement the equation using only NOR gates the AND terms in the equation
should be eliminated. So modifying the equation without changing its value.

z = AB + (C + D)'
z = AB . (C+D)
z = (A+B ) + (C+D)

Q.11 Draw the gate diagram of negative edge triggered JK Flip-Flop. 2

C = Clock input and negative Edge detector circuit/Pulse Detector circuit
Ans:

Q.12 Write the output Boolean equation for a 4:1 Multiplexer. Assume any variables for 2
inputs and output of MUX.
Assuming D0, D1, D2, D3 are the inputs, S0 (LSB), and S1 (MSB) are the select inputs
Ans:
and Y is the output.
Truth Table is :
Inputs O/P
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Then, the output Boolean equation for a 4:1 Multiplexer is

Y = S1' S0' D0 + S1' S0 D1 + S1 S0' D2 + S1 S0 D3
Q.13 Represent (0.26)10 in Signed Magnitude, One’s Complement and Two’s 2
Complement form.
Ans:
Writing the given decimal number into binary (0.26)10 = (0.0100001)2
It is a positive number therefore Sign bit = 0
Signed Magnitude representation = (0 0.0100001)2
One’s Complement representation = (0 0.0100001)2
Two’s Complement representation = (0 0.0100001)2
Q.14 Represent (-67.35)10 in Signed Magnitude, One’s Complement and Two’s 2
Complement form. (Any two will be asked).
Writing the given decimal number into binary (67.35)10 = (1000011.0101)2
Ans:
It is a negative number therefore Sign bit = 1
Signed Magnitude representation = (1 1000011.0101 )2
One’s Complement representation is as follows:-
(+67.35)10 = (0 1000011.0101 )2, Taking its One’s Compliment
(-67.35)10 = (1 0111100.1010 )2
Two’s Complement representation is obtained by adding 1 to One’s complement
number = (1 0111100.1010 )2 + (1)2 = (1 0111100.1011 )2
Q.15 List the IC number of the standard IC’s available for Decoders and Multiplexers. 2
For Decoders:
Ans:
1. IC 74139 – Dual 2:4 Decoder
2. IC 74138 – Single 3:8 Decoder
3. IC 74154 – Single 4: 16 Decoder
For Multiplexers:-
1. IC 74157 – Quad 2: 1 MUX
2. IC 74153 – Dual 4: 1 MUX
3. IC 74151 – Single 8:1 MUX
4. IC 74150 – Single 16:1 MUX
Q.16 Perform the following. 5
i. (10111)2 ÷ (101)2 ii. (10111)2 × (101)2
Ans:

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

(100.1001)2 (10111)2
× (101)2
(101)2 (10111)2
10111
- 101
00000+
000110
10111++
- 101
(1110011 )2
001000
- 101
011

Q.17 State and Prove De-Morgan’s Theorem 5

1.Complement of ANDed variables is 2.Complement of ORed variables is
Ans:
equal to the ORing of the equal to the ANDing of the
complemented variables. complemented variables.

From the above Truth Tables The L.H.S side equation and R.H.S side equation have
same Logic values for both the theorems. Hence De-Morgans Theorem is proved.
Q.18 Using Boolean algebra reduce the given Boolean equation.(Any one will be asked) 5

Ans:
A+B[AC+(B+C')D] A[B + C(AB+ AC)']
=A+B[AC+BD+C'D]–Distributive Law, And =A[B+C((AB)'.(AC)')]-De-Morgans
=A+ABC+BD+BC'D–Distributive Law =A[B+C(A'+B').(A'+C')]-De-Morgans
=A(1+BC)+ BD+BC'D =A[B+C(A'+A'C'+A'B'+B'C')]-
Distributive,And Law

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

=A+BD(1+ C')-OR Law =A[B+C(A'+ B'C')] – Distributive,Or

=A+BD =A[B+A'C] –-- C.C'=0 And Law
=AB ---And Law, Distributive Law

Q.19 State and prove Consensus Theorem. 5

It is the conjunction(combination) of all the unique literals(variables) of the terms,
Ans:
excluding the literal that appears unnegated in one term and negated in the other.
This combination of literals is redundant(un-necessary hence not needed) hence can
be eliminated.
 𝐴𝐵 + 𝐴′𝐶 + 𝐵𝐶 = 𝐴𝐵 + 𝐴′𝐶
 (𝐴 + 𝐵). (𝐴′ + 𝐶). (𝐵 + 𝐶) = (𝐴 + 𝐵). (𝐴′ + 𝐶)
Proving :AB+A'C+BC = AB+A'C
L.H.S = AB+A'C+BC(A+A')
= AB+A'C+ABC+A'BC
= AB(1+C) +A'C(1+B)
= AB+ A'C
= R.H.S
Q.20 Draw the gate diagram of a positive edge triggered D FF using Master-Slave 5
configuration.
Ans:
Master is a Low level(negative) D latch and slave is a High level(positive) SR latch.
Block Diagram:

D Qm S Qs
D

CLK
Qmb R Qsb

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Q.21 Implement XOR gate using only NAND gates and using only NOR gates. 5
Can draw any one variety of XOR and XNOR using only NAND gates. Similarly
Ans:
draw any one variety of XOR and XNOR using only NOR gates.
Showing both XOR and XNOR.
But the question has asked only XOR. Draw accordingly.

Using NAND Gates Using NOR Gates

XOR
XOR

XOR
XOR

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

XNOR XNOR

XNOR XNOR
Q.22 Explain Octal to Binary Priority Encoder. 5
1. It is a combinational circuit which converts input Octal number into a three
Ans:
bit binary,
2. There are eight inputs(I0 to I7) and three outputs(B2B1B0) to this encoder.
3. Input I7 has the highest priority and I0 the least. Thus if multiple inputs are
activated at the same time, the highest priority input is selected and its
corresponding binary is available at the output.
4. It is used in key encoding.
5. The standard available Octal to Binary priority encoder is IC 74148 which
has active low eight inputs and active low three binary outputs. Its function
table is given below. If enable input EI = 0 the Encoder enables. Logic 0 on
input is recognized and based on the priority its complemented binary output
is generated. GS ( Group Select) and EO (Enable Output) are used for
cascading the Encoders to obtain larger input key encoding.

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

You can design your Encoder if asked for 10 Marks.

You can also show only your design of Encoder for 5 marks.
Q.23 Design Full Adder using appropriate size decoder. 5
Design:
Ans:
Step1] Block diagram of Full Adder
A Sum
B FA

Cin Carry

Step2] Truth Table of Full Adder

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Step3] Minterm list of the outputs Sum and Carry

Sum = Σm(1,2,4,7)
Carry = Σm(3,5,6,7)
Since Full Adder has three inputs we use a decoder with three inputs and hence using
3:8 Decoder, IC 74138.

Step4] Circuit Diagram:

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Q.24 Design Full Adder using Half Adders and few gates. 5
Design:
Ans:

Step 1] Block diagram of Full adder

A Sum
B FA

Cin Carry

Step2] Truth Table of Full Adder

Step 3] Logic Step4] Block Diagram

A
+ B
C1 S1
+ Cin
C2 S2

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 Finolex Academy of Management and Technology, Ratnagiri
Department of Computer Science and Engineering (AI & ML)

Q.25 Assume the given decimal numbers are represented in Binary One’s Complement 5
form, perform the following arithmetic. (Any one)
Ans:
i. (26.5)10 - (16.75)10 ii. (-62)10 - (39)10
Step1] Writing both the numbers in 1’s Step1] Writing both the numbers in 1’s
complement form. complement form. And since the
(26.5)10 = (0 11010.10)2 arithmetic is of same signed number
(16.75)10 = (010000.11)2 hence using one more bit 0 to represent
(-16.75)10 = (101111.00)2 the magnitude of 62.
Step2]Adding both the numbers (+62)10 = (0 0111110)2
(26.5)10 = (0 11010.10)2 (-62)10 = (1 1000001)2
(-16.75)10 = (101111.00)2 (+39)10 = (0 0100111)2
Cy=1 (001001.10)2 (-39)10 = (1 1011000)2
Add the carry back to the result Step2] Adding them
Therefore Result = (-62)10 = (1 1000001)2
(001001.11)2=(9.75)10 (-39)10 = (1 1011000)2
Since the Sign bit =0, Result is Cy=1 (10011001)2
positive and has true magnitude. Add the carry back to the result
Hence (26.5)10 - (16.75)10 = (+9.75)10 Result = (10011010)2
Sign bit =1, hence result is negative and
the result magnitude is in 1is
complement form.
To find true magnitude find its 1’s
complement again.
True
magnitude=(01100101)2=(101)10
iii. Hence, (-62)10 - (39)10 = (-101)10

Subject Teacher
Assistant Prof. V V Nimbalkar

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