1

FPGA
Evolution of implementation technologies

• Logic gates (1950s-60s)

• Regular structures for two-level logic (1960s-70s)
 muxes and decoders, PLAs

• Programmable sum-of-products arrays (1970s-80s)

 PLDs, complex PLDs

• Programmable gate arrays (1980s-90s)

 densities high enough to permit entirely new
class of application, e.g., prototyping, emulation,
acceleration
 Types of PLD Devices
3

• PROM
• PAL
• PLA
• SPLD
• CPLD
Can handle more complex design from top to bottom
Common feature is, all use Two level Logic
First – Array of And Gates
Second – Array of Or gates
 PLD
4

Fixed AND Programmable

Inputs Array OR Array Outputs

Programmable Read Only Memory (PROM)

Programmable Fixed
Inputs AND Array OR Array Outputs

Programmable Array Logic (PAL)

Programmable Programmable
Inputs AND Array OR Array Outputs

Programmable Logic Array (PLA)

 PROM
5

• A PROM is a SOP logic device with a fixed AND array and a

programmable OR array N1 N0
PROM of 2^N by M, N =2, M=2
M0 = N1.N0 + N1.N0’
M1 = N1.N0 + N1’.N0’

= Fixed Connection
= Programmable
Connection

M1 M0
 PLA
6

• A PLA is a SOP logic device with a programmable AND array

and a programmable OR array N1 N0
PROM of 2^N by M, N =2, M=2
M0 = N1.N0 + N1.N0’
M1 = N1.N0 + N1’.N0’

= Fixed Connection
= Programmable
Connection

Note: Less Gates here

M1 M0
 CPLD
7

• Logical Blocks consist of PAL or PLA

structure and sequential circuits
• Switch Matrix is also called as

programmable interconnect which is

a set of interconnecting metallic paths
that are “reprogrammable”
• I/O Block – communicates with
external source. An IO block consist of Buffers
I/P buffers – connects to I/P - IBUF
O/P buffers – connects to O/P - OBUF
Bidirectional buffers – connects to I/O
 CPLD Flow
8

Files generated during the

Synthesis
CPLD flow .ngc(native generic constraint)
Constraints
.ucf(user constraint file)
After constraint
Translate
Next implementation phase .ngd(native generic database)
First phase - .ngc, .ucf
Mapping
Second Phase – mapping
.ncd(native circuit description)

Using JTAG cable data Programming

Transfer from Host to target .Jed --- ASCII File

device
 FPGA
9

• Logical Blocks(Configurable) consist

of LUTs, embedded logic and F5,F6 etc
A configurable logic is made up of
logic element(LE) – FF + LUT
(combo logic)

• Switch Matrix – segmented

interconnects
• LUT – are the kind of logic that are

Used in SRAM based fpga’s.

Each LUT is a bunch of single bit
Memory cells storing individual bit values in each of the cells
 FPGA Flow
10

In FPGA path delay can be

Synthesis
Predicted only after the place .ngc(native generic constraint)
And route Constraints
.ucf(user constraint file)
Because it is broken segments
Translate
So the path is not fixed .ngd(native generic database)
Like in CPLDs, it may use
Mapping
Shorter or longer path
.ncd(native circuit description)
Which we will know only
After the Routing Programming

.bit --- Bit File

 LUT
11

In CPLD - AND or OR
IN FPGA - LUTs
0
0
0 It will store
1 information like this

a b

Single Memory cell for storing

 FPGA – SRAM based
12

• Memory Configuration in FPGAs

1) SRAM Based - Volatile, reprogrammable
Xilinx, Altera, Atmel, Lattice
2) Anti fuse based – Non volatile, 1 time programmable
Actel, Qlogic
3) Flash Based – Non volatile, reprogrammable
lattice - best but too costly
 Granularity of FPGAs
13

• Three types of structures (the lowest level of abstraction for

a design)
1) Fine grained structure – Logic available is in form of gates
(LUTs) and FFs
2) Coarse grained structure – The logic available is in the form
of functional units – ALUs, counters etc
3) Mixed grained structure
 LUT - Example
14

X = (a & b) | ( ~b & c)
module LUT_exa ( input a,b,c, output x);
LUT #(.INIT (8’h47))
LUT3_inst ( .O(x), I0(c), I1(b), I2(a));
A B C X
endmodule 0 0 0 0
O,I0,I1,I2 are FPGA primitives so Uppercase 0 0 1 1
0 1 0 0
1
0 1 1 0
2
x 1 0 0 0
3 1 0 1 1
4 1 1 0 1
1 1 1 1
 FFs in FPGA
15

FDC – Asycnhronous Clear ----- first priority

FDCP – Asynchronous Preset ------ has second priority

FDR – Synchronous Set -- first priority No FDS or

FDRS – Synchronous Reset -- second priority No FDP alone

FDC_1 – Active Low Asynchronous clear

FDCP_1 – Active Low Asynchronous Preset

FDR_1 – Active Low Synchronous Set

FDRS_1 – Active Low Synchronous Reset
 Types of Simulations in FPGA
16

• Functional Simulation – RTL(Source code), No changing in TB

Pre Synthesis
• Gate level Simulation – Netlist as a source code
Post Synthesis
• Timing Simulation – Netlist with a timing delay as source
code
Post – Place and Route
 Gate Level Simulation
17

Isim > netgen –ofmt verilog module_name.ngc

netgen( generate the netlist)
ofmt(output netlist format)

converting .ngc to verilog .v format

Observation:
The functional simulation waveform and the netlist
simulation waveform has to be the same
What to predict: The timing delays of the design are not
extracted in the netlist simulation
 Timing Simulation
18

Timing simulation is done to extract the actual delays during the

simulation process
Implement design:
Place and Route:
Generate Post –Place and route:
Now it create a netlist file with a timing delay
with internally reading .sdf file.
.sdf file created inside ../syntn/netgen/par
(standard delay format)
Now in simulation mode – post route simulation – PAR (
static timing report)
 Xilinx FPGAs
19

Spartan3, Spartan 3A, Spartan3E, Vertex3, Vertex4, Vertex5

CMOS technology for Spartan 3( 90nm)
Packages: PQ208 - plastic quad 208
208 – total number of ports available
TQ144(Thin Quad)
FT256(Fine Thin)
FG456(Fine thin grid structure)
FPGA criteria: Family, Device, Package, Speed Grid
Spartan or vertex, XC400( Linux corporation), FG456, -4 or -5
Speed grid define the complexity of design
-4 = low complicated, -5: high complicated design
depends on high performance -5,
but for internal general purpose -4
Withstanding temperature for Spartan3 ( 0 to 85degrees C)
 CLB
20

• The CLB categorized with two reasons

1) SLICEL: Supports LUTs and sequential elements
2) SLICEM: Supports LUTs, sequential , memory blocks
each CLB consists of 4 Slices
each slice consists of 2 LUTs , 2 D FFs, & 1 Dedicated Mux
Example: Draw the Equivalent RTL & LUT schematic of 4:1 Mux
It is not optimized structure
LUT4 In terms of power dissipation,
Because LUT4 has its own
LUT4
component delay

LUT4 The largest Mux that a single

LUT4 support is 2:1 mux
 Dedicated Mux(F5 Mux)
21

The power dissipation has minimized in spartan architecture by

using dedicated Mux’s.
It has “0” wiring delay ( almost negligible)
Now redraw the same using F5 Mux
F5 Mux means it can handle 5
I/P functions at a time

To store the data incoming we

LUT4 need LUT4, next needed to be
F5 driving so F5 mux

F5 mux always combines

LUT4 output of two LUTs in a SLICE,
Can drive only F6 Mux,
F6 cannot drive F5
 Example…
22

Draw the equivalent FPGA structure of 8:1 Mux??

 Computer-aided Design

• Can't design FPGAs by hand

1) Way too much logic to manage, hard to make changes
• Hardware description languages
1) Specify functionality of logic at a high level
• Validation - high-level simulation to catch specification errors
1) Verify pin-outs and connections to other system components
2) Low-level to verify mapping and check performance
• Logic synthesis
1) Process of compiling HDL program into logic gates and flip-flops
• Technology mapping
1) Map the logic onto elements available in the implementation technology
(LUTs for Xilinx FPGAs)
 CAD Tool Path (cont’d)

• Placement and routing

1) Assign logic blocks to functions
2) Make wiring connections
• Timing analysis - verify path
1) Determine delays as route
2) Look at critical paths and ways to improve
• Partitioning and constraining
1) If design does not fit or is un routable as placed split into multiple chips
2) If design it too slow prioritize critical paths, fix placement of cells, etc.
3) Few tools to help with these tasks exist today
• Generate programming files - bits to be loaded into chip for configuration
 Xilinx CAD Tools

• Verilog (or VHDL) use to specify logic at a high-level

1) Combine with schematics, library components
• Syncplicity
1) Compiles Verilog to logic
2) Maps logic to the FPGA cells
3) Optimizes logic
• Xilinx APR - Automatic place and route (simulated annealing)
1) Provides controllability through constraints
2) Handles global signals
• Xilinx Xdelay - Measure delay properties of mapping and aid in iteration
• Xilinx XACT - Design editor to view final mapping results
 Applications of FPGAs
• Implementation of random logic
1) Easier changes at system-level (one device is modified)
2) Can eliminate need for full-custom chips
• Prototyping
1) Ensemble of gate arrays used to emulate a circuit to be manufactured
2) Get more/better/faster debugging done than possible with simulation
• Reconfigurable hardware
1) One hardware block used to implement more than one function
2) Functions must be mutually-exclusive in time
3) Can greatly reduce cost while enhancing flexibility
4) RAM-based only option
• Special-purpose computation engines
1) Hardware dedicated to solving one problem (or class of problems)
2) Accelerators attached to general-purpose computers