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 Excellence in World class
VLSI Training & Placements

Advanced Verification
Workshop

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WELCOME to ProV LOGIC
A very warm welcome to all!
We are excited to have you with us as we step into the fascinating realm of VLSI
Technology. Together, let’s embark on a journey of learning, innovation, and
growth in this dynamic field. We look forward to an inspiring and enriching
experience with all of you!

Our Vision Welcome to ProV Logic

Our Mission
To make ProV Logic as a global To deliver high-class quality sessions
leader in VLSI training, empowering that focus on areas where students
students and professionals to excel in often lag in meeting industry standards
the dynamic semiconductor industry. at a highly affordable budget

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THE VISIONARY Duo BEHIND ProV LOGIC

Meet the Founders

Prasanthi Chanda
Founder & CEO
Expert in VLSI, Proven Mentor,Visionary
Welcome
Leader, PassionatetoEducator
ProV Logic

Vishwa Arya
Co-Founder & Marketing Head
Marketing Strategist, Visionary Partner,
Student-Centric, Dynamic Leader

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 About Our CEO: PRASANTHI CHANDA

Passionate trainer
Expertise in DV
Prasanthi is a dedicated trainer with a
Prasanthi brings exceptional expertise
passion for mentoring students, known for
in System On Chip verification and
her patience and understanding. She has
debugging, with strong knowledge in
trained over 2000+ students, achieving an
RTL design and verification. She is
impressive 85% placement success.
proficient in SystemVerilog and UVM Welcome to ProV Logic
methodologies, making her a specialist
Work Experience
in developing and verifying IPs. A
Prasanthi has gained extensive knowledge
proven track record in leading
by working with various leading companies
complex projects involving ASIC
in the VLSI industry. As the Ex-Co-Founder
Designs and Various IPs.
& Managing Director of Semidesign.

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SESSION AGENDA

Limitations of Verilog HDL

Features of SystemVerilog
Why UVM Verification
SV & UVM at SOC | IP Level
System on chip Design
Communication & Bus Protocols
Open forum for Q/A discussions.

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RTL DESIGN USING VERILOG HDL

SYNTHESIS SIMULATION
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LIMITATIONS OF VERILOG HDL

Ineffective randomization.
No construction of constraints in order to control over randomization.
Once an array's dimensions are declared, we can't change the dimensions of it.
There is no effective way of validating the functionality of design.
There is no standardized interface for easy connection of TB and DUT.
Reuse/Repetitive of similar code is very minimal by using the Verilog concepts.
There is only code coverage verification but no functional coverage.

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VERIFICATION APPROACH IN VLSI

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WHAT IS SYSTEMVERILOG

SystemVerilog, standardized as IEEE 1800, is a hardware description and

hardware verification language used to model, design, simulate, test and
implement electronic systems. SystemVerilog is based on Verilog and some
extensions, and since 2008, Verilog is now part of the same IEEE standard. It
is commonly used in the semiconductor and electronic design industry as an
evolution of Verilog.

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EVOLUTION OF SYSTEMVERILOG

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SYSTEM VERILOG FEATURES OVER VERILOG
HDL
Dynamic data types and dynamic creation of arrays.
Allows OOPS concept.
Constraint Randomization to get desired values for random variables.
Allows Functional coverage constructs.
It is good only if code written for the functional coverage.
Allows Assertions to validate the behavior/properties of design and throws
severity over assertion failure.
Allows Interface to easy connection of TB and DUT

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SYSTEMVERILOG TB ARCHITECTURE

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UVM TB ARCHITECTURE

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SYSTEM VERILOG FEATURES OVER VERILOG
HDL
Reusability, Modularity
Standardized Base Classes
Object-Oriented Programming (OOP)
Transaction-Level Modeling (TLM)
Factory Pattern
Constrained Random Stimulus Generation, Functional Coverage
Messaging and Reporting Mechanism
Phasing Mechanism
Sequence-Based Stimulus Generation
Register Abstraction Layer (RALModel)

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SYSTEM ON CHIP DESIGN

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SYSTEM ON CHIP DESIGN

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DIFFERENCE B/W TESTPLAN & VERIFICATION PLAN

A Test plan is a document that describes the overall approach for testing a design.
Objectives
Test cases
Test Environment
Test Methodology
Test Metrics

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DIFFERENCE B/W TESTPLAN & VERIFICATION PLAN

A V-plan, is a document that describes the verification plan for a specific design
module.
Functional specification
Verification objectives
Verification methodology
Verification environment
Test cases
Test metrics

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DIFFERENCE B/W TESTPLAN & TEST STRATEGY

A Test Plan is a document that describes the objective, scope, and weight of
the software testing task. However, a Test Strategy explains how the testing
part needs to be completed.
It is possible to change a Test Plan, but you can’t change your Test Strategy.
At the project level, you need a Test Plan. On the other hand, a Test Strategy
you need at the organization level.
Test managers make the Test Plan, whereas the responsibility of building the
Test Strategy is of the project manager

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TEST SCENARIO

A test scenario is a document that describes the end-to-end functionality of a

software application. Whereas Test cases are the set of steps to determine
how to execute the scenarios in order. Test scenario consists of a detailed test
procedure. We can also say that a test scenario has many test cases
associated with it. Before executing the test scenario we need to think of test
cases for each scenario.

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TEST CASE

Test cases are low level actions and it can be derived from test scenarios. Test
cases are set of steps which performed on system to verify the expected output.
Writing test cases is one time effort which can be used in future while executing
regression test case.

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HOW TEST EXECUTED | CHECKING MECHANISM | PASS / FAIL

Makefile : Run the Testcases using commands

Test Execution :
Check for Failures - Compilation Error
Test Entered into Main execution
Did test crossed Initialization stages or not ?
Test Entered into Main sequence ?
Test PASS / FAIL

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