To receive or send data The number of locations with which a CPU can communicate is always

equal to 2x, where x is the address lines, regardless of the size of the data bus
ex. a CPU with 24 address lines and 16 data lines can provide a total of 224 or 16M bytes of
addressable memory
Each location can have a maximum of 1 byte of data, since all general-purpose CPUs are byte
addressable

• Internal Organization of Computers

ALU (arithmetic/logic unit)
 Performs arithmetic functions such as add, subtract, multiply, and divide, and logic functions
such as AND, OR, and NOT
ROM provides information that is fixed and permanent
• Tables or initialization program
RAM stores information that is not permanent and can change with time
Program counter
 Points to the address of the next instruction to be executed
 As each instruction is executed, the program counter is incremented to point to the address of
the next instruction to be executed
Instruction decoder
 Interprets (‫)يفسر‬the instruction fetched into the CPU

Registers
 The CPU uses registers to store information temporarily
• Values to be processed
• Address of value to be fetched from memory
 Registers are used to store information temporarily, while the
information could be a byte of data to be processed, or an address
pointing to the data to be fetched
 There is only one data type, 8 bits
 The most widely used registers

• A (Accumulator)
• For all arithmetic and logic instructions B, R0, R1, R2, R3,
R4, R5, R6, R7

• DPTR (data pointer), and PC (program counter)

Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory.
B register is used along with Accumulator for multiplication and division.
A and B registers together is also called MATH registers.
 THE 8051 ARCHITECTURE
8051 microcontroller is designed first by Intel in 1981.
microcontrollers are classified based on size of data bus
It is an 8-bit microcontroller.
THE 8-BIT MICROCONTROLLER/Eight bit ALU: ALU can perform arithmetic and logic functions on 8 bit
variables at an instruction.
 It is built with 40 pins DIP (dual inline package)
An on-chip crystal oscillator is integrated in the microcontroller having crystal frequency of 12 MHz
The system bus consists of an 8-bit data bus
16-bit address bus and bus control signals.
4Kbytes of internal program memory (code memory) [ROM]
128 bytes of internal data memory [RAM]
32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O lines)
Two 16 Bit Timer/Counter :T0, T1
Full Duplex serial data receiver/transmitter
Four Register banks with 8 registers in each bank.
Sixteen bit Program counter (PC) and a data pointer (DPTR)
8 Bit Program Status Word (PSW)
8 Bit Stack Pointer
64 Kbytes of external program memory address space.
64 Kbytes of external data memory address space.
Control Registers : TCON,TMOD,SCON,PCON,IP and IE
Two External and Internal Interrupt sources
Oscillator and clock circuits

8051 has 128 bytes of internal RAM which is divided into

o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
80C51 Block Diagram

6
Page 7
Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.
Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the
contents of most registers. In other words, the positive voltage(for two
machine cycle) on this pin resets the microcontroller.
Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or
output. Besides, all of them have alternative functions
Pin 10 RXD. Serial asynchronous communication input or Serial synchronous
communication output.
Pin 11 TXD. Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12 INT0.External Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies operating
frequency is usually connected to these pins.
Pin 20 GND. Ground.
Pin 21-28 Port 2. inputs/outputs or In case external memory is used, the higher address byte, i.e. addresses A8-A15
will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all
eight port bits are used for its addressing, the rest of them are not available as inputs/outputs.
Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0) appears on it every time the
microcontroller reads a byte from memory.
Pin 30 ALE.(address latch enable) Prior to reading from external memory, the microcontroller puts the lower
address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the
external latch latches the state of P0 and uses it as a memory chip address. Immediately after that, the ALE
pin is returned its previous logic state and P0 is now used as a Data Bus.
Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard
to whether there is internal memory or not. It means that even there is a program written to the
microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By
applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if
exists).
Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs.
Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data
output (Data Bus) when the ALE pin is driven low (0).
Pin 40 VCC. +5V power supply.
Ports
• Port 0 - external memory access
• low address byte/data
• Port 2 - external memory access
• high address byte
• Port 1 - general purpose I/O
• Port 3 - Special features
• 0 - RxD: serial input
• 1 - TxD: serial output
• 2 - INT0: external interrupt
• 3 - INT1: external interrupt
• 4 - T0: timer/counter 0 external input
• 5 - T1: timer/counter 1 external input
• 6 - WR: external data memory write strobe
• 7 - RD: external data memory read strobe
10
MEMORY ORGANIZATION
Internal RAM organization
R7 1F
R6 1E
2F
7F 78 7F
R5 1D
R4 1C 2E
77 70 7E

BANK 3
R3 1B
2D
6F 68 .
R2 1A
R1 19 2C
67 60 .
R0 18 2B
5F 58 .
R7 17
2A
57 50 .
R6 16
R5 15 BANK 2 29 4F 48 .
R4 14 28 47 40 .
R3 13
27 3F 38 .
R2 12
R1 11 26 37 30 .
R0 10 2F 28
R7 0F
25 32
BANK 1

27 20
R6 0E 24 31
R5 0D 1F 18
23 30
R4 0C 17 10
22
R3 0B
21 0F 08
R2 0A
BANK 0

R1 09 07 00 General purpose memory

R0 08
R7 07
R6 06
R5 05 Bit addressable memory
R4 04
R3 03
R2 02
R1 01
R0 00
Working Registers
 Internal RAM 128 Byte (Lower)
1. First Part

• 32 bytes from address 00h to 1fh that make up 32 working registers organized as 4
memory banks of 8 registers each.
• The 4 register banks are numbered 0 to 3 and are made up of 8 registers named R0 to R7.
• Each register can be addressed by name or by its RAM addresses.
• Thus R0 of bank3 is R0 (if bank3 is selected) or address 18h (where bank3 is selected).
• Bits RS0 and RS1 in the PSW determine which bank of registers is currently in use at any
time when program is running.
• Register banks not selected can be used as general purpose RAM.
• Bank0 is selected by default on reset..
2. Second part
• Bit addressable area of 16 bytes occupies RAM byte addresses 20h to 2fh, forming total of 128 bits.
• An addressable bit may be specified by its bit address of 00h to 7fh or 8 bits may form any byte address
from 20h to 2fh.
• For example bit address 4fh is also bit 7 of byte address 29h.
• Addressable bits are useful when the program need only remember a binary event.
• A bit variable can be set with a command such as SETB and cleared with a command such as CLR.
• Example instructions are:
• SETB 25h ; sets the bit 25h (becomes 1)
• CLR 25h ; clears bit 25h (becomes 0)
• Note, bit 25h is actually bit 5 of Internal RAM location 24h.
3. Third part
General Purpose RAM: A general purpose RAM area above the bit area from 30h to
7f h, addressable as byte.

30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for general-purpose
data storage, user should take care while using the memory location from 00 -2Fh
• since these locations are also the default register space, stack space, and bit addressable
space. It is a good practice to use general purpose memory from 30 – 7Fh.
• The general purpose RAM can be accessed using direct or indirect addressing modes.
 Program Status Word
• Register set select
• Status bits

16
 PSW (Program Status Word). This is an 8 bit register which contains the arithmetic
status of ALU and the bank select bits of register banks.

CY - carry flag
AC - auxiliary carry flag
F0 - available to the user for general purpose
RS1,RS2 register bank select bits
OV overflow
P parity
 READ OPERATIONS retrieve a byte of data from memory at the location specified
and place it on the data bus.
• CPU reads the data and places it in one of its internal registers.
 WRITE OPERATIONS put data from CPU on the data bus and store it in the location
specified.
• ADDRESS BUS carries the address of a specified location.
• For n address lines, 2n locations can be accessed. E.g., A 16-bit address bus can
access 216 = 65,536 locations or 64K locations (210 = 1024 = 1K, 26 = 64).
• DATA BUS carries information between the CPU and memory or between the CPU
and I/O devices.
• CONTROL BUS carries control signals supplied by the CPU to synchronize the
movement of information on the address and data bus.
Memory basic concepts

19
 Stack Pointer (SP) –
 It contains the address of the data item on the top of the stack. Stack may reside
anywhere on the internal RAM.
 On reset, SP is initialized to 07 so that the default stack will start from address 08
onwards.
 Data Pointer (DPTR) –
 DPH (Data pointer higher byte), DPL (Data pointer lower byte).
 This is a 16 bit register which is used to furnish address information for internal and
external program memory and for external data memory.
 Program Counter (PC) –
 16 bit PC contains the address of next instruction to be executed.
 On reset PC will set to 0000. After fetching every instruction PC will increment by
one.
 STACK LIFO
• A stack is a last in first out memory.
• In 8051 internal RAM space can be used as stack(‫)دفتر‬.
• The address of the stack is contained in a register called stack pointer.
• Instructions PUSH and POP are used for stack operations.
• When a data is to be placed on the stack, the stack pointer increments before storing the data
on the stack so that the stack grows up as data is stored (pre-increment).
• As the data is retrieved from the stack the byte is read from the stack, and then SP
decrements to point the next available byte of stored data (post decrement).
• The stack pointer is set to 07 when the 8051 resets. So that default stack memory starts from
address location 08 onwards (to avoid overwriting the default register bank ie., bank 0).
• The Stack and Stack pointer:

• The stack refers to an area of internal RAM that is used in conjunction(‫ )بالتزامن مع‬with certain opcodes to store and retrieve
data quickly.
• The 8 bit Stack Pointer (SP) register is used by the 8051 to hold internal RAM address that is called the top of the stack.
• The address in SP register is the location in internal RAM where the last byte of the data was stored by stack operation.

• When data is to be placed on the stack , the SP increments before storing data on the stack so that the stack grows up as
data is stored.
• Whenever data is retrieved from the stack, the byte is read from the stack and then the SP decrements to point to the next
available byte of stored data.

• Operation of the Stack and Stack Pointer:

• The SP is set to 07 when the 8051 is reset and can be changed to any internal RAM address by the programmer.
• The stack is limited in height to the size of internal RAM.
• The stack can overwrite valuable data in register banks, bit addressable RAM and scratched pad RAM areas.It is
programmer‘s responsibility to make it sure that the stack does not grow beyond predefined bounds.
• The stack is normally placed high in the internal RAM by an appropriate choice of the number placed in SP register, to
avoid conflict with registers or RAM.
 • Eg; Show the stack and SP for the following.
[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H

PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H

PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H

PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H

POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H
8051 Clock and Instruction Cycle:

 The heart of 8051 is the circuitry that generates the clock pulses by which all
internal operations are synchronised.
 Pins XTAL1 and XTAL2 are provided for connecting resonator to form an
oscillator.
 The crystal frequency is the basic internal frequency of the microcontroller.
 8051 is designed to operate between 1MHz to 16MHz and generally operates with
a crystal frequency 11.04962 MHz.

• The oscillator formed by the crystal , capacitor and an on-chip inverter generates a
pulse train at the frequency of the crystal.
• The clock frequency f establishes the smallest interval to accomplish any simple
instruction.
• The time taken to complete any instruction is called as machine cycle or
instruction cycle.
• In 8051 one instruction cycle consists of 6 states or 12 clock cycles, instruction
cycle is also referred as Machine
Instruction Timing

25
Instruction Timing
• One “machine cycle” = 6 states (S1 - S6)
• One state = 2 clock cycles
• One “machine cycle” = 12 clock cycles
• Instructions take 1 - 4 cycles
• e.g. 1 cycle instructions: ADD, MOV, SETB, NOP
• e.g. 2 cycle instructions: JMP, JZ
• 4 cycle instructions: MUL, DIV

26