FUJITSU SEMICONDUCTOR

DATA SHEET DS07-12547-4E

8-bit Original Microcontroller

CMOS

F2MC-8L MB89530A Series

MB89535A/537A/537AC/538A/538AC/F538
MB89P538/PV530
■ DESCRIPTION
The MB89530A series is a one-chip microcontroller featuring the F2MC-8L core supporting low-voltage and high-
speed operation. Built-in peripheral functions include timers, serial interface, A/D converter, and external interrupt.
This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household
to industrial equipment, as well as use in portable devices.

■ FEATURES
• Wide range of package options
• Two types of QFP packages (1 mm pitch, 0.65 mm pitch)
• LQFP package (0.5 mm pitch)
• SH-DIP package
• Low voltage, high-speed operating capability
• Minimum instruction execution time 0.32 µs (at base oscillator 12.5 MHz)
• F2MC-8L CPU Core
• Instruction set optimized for controller operation
• Multiplication/division instructions
• 16-bit calculation
• Branching instructions with bit testing
• Bit operation instructions, etc.
• Five timer systems
• 8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer)
• Pulse width count timer (supports continuous measurement or remote control receiving applications)
• 16-bit timer counter
• 21-bit time base timer
• Watch prescaler (17-bit)
• UART
• Synchronous or asynchronous operation, switchable
• 2 serial interfaces (Serial I/O)
• Selection of transfer direction (specify MSB first or LSB first) for communication with a variety of devices
(Continued)
 MB89530A Series

(Continued)
• 10-bit A/D converter (8 channels)
• External clock input for startup support
• Time base timer output for startup support (except MB89F538)
• Pulse generators (PPG) with 2-program capability
• 6-bit PPG with selection of pulse width and pulse period
• 12-bit PPG (2 channels) with selection of pulse width and pulse period
• I2C interface circuits
• External interrupt 1 (single-clock system : 4 channels, dual-clock system : 3 channels)
• 4 or 3 independent inputs, release enabled from standby mode (includes edge detection function)
• External interrupt 2 (8 channels)
• 8 independent inputs, release enabled form standby mode (includes level edge detection function)
• Standby modes (low power consumption modes)
• Stop mode (oscillator stops, virtually no power consumed)
• Sleep mode (CPU stops, power consumption reduced to one-third)
• Sub clock mode
• Watch mode
• Watchdog timer reset
• I/O ports
• Maximum ports
Single-clock system : Except MB89F538 53 ports
: MB89F538 52 ports
Dual-clock system : Except MB89F538 51 ports
: MB89F538 50 ports
• 38 general-purpose I/O ports (CMOS) (MB89F538 : 37 general-purpose I/O ports)
• 2 general-purpose I/O ports (N-ch open drain)
• 8 general-purpose output ports (N-ch open drain)
• General-purpose input ports (CMOS) : single-clock system : 5 ports, dual-clock system : 3 ports

■ PACKAGES
64-pin, Plastic SH-DIP 64-pin, Plastic LQFP 64-pin, Plastic QFP

(DIP-64P-M01) (FPT-64P-M03) (FPT-64P-M06)

64-pin, Plastic QFP 64-pin, Ceramic MDIP 64-pin, Ceramic MQFP

(FPT-64P-M09) (MDP-64C-P02) (MQP-64C-P01)

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 MB89530A Series

■ PRODUCT LINEUP
Part number
MB89537A/ MB89538A/
MB89535A MB89F538 MB89P538 MB89PV530
537AC 538AC
Parameter
One-time
Type Mass produced (Mask ROM) Flash memory Evaluation
programmable
48 K × 8-bit
48 K × 8-bit
(built-in
16 K × 8-bit 32 K × 8-bit 48 K × 8-bit (built-in ROM) 48 K × 8-bit
Flash memory)
ROM capacity (built-in (built-in (built-in (write from (external
(write from
ROM) ROM) ROM) general purpose ROM) *2
general purpose
EPROM writer)
EPROM writer)
512 byte ×
RAM capacity 1 K × 8-bit 2 K × 8-bit
8-bit
2.2 V to 5.5 V *1
Operating voltage 3.5 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V
(MB89535A/537A/538A/537AC/538AC)
Basic instructions : 136
Instruction bit length : 8-bits
Instruction length : 1 bit to 3 bits
CPU functions
Data bit length : 1, 8, 16-bits
Minimum instruction execution time : 0.32 µs / 12.5 MHz
Minimum interrupt processing time : 2.88 µs / 12.5 MHz
Input ports : single-clock system : 5 (4 also usable as external interrupts)
dual-clock system : 3 (3 also usable as external interrupts)
Output-only ports (N-ch open drain)
: 8 (8 also usable as ADC input)
I/O ports (N-ch open drain) : 2 (2 also usable as SO2/SDA or SI2/SCL)
I/O ports (CMOS) (Except MB89F538)
Ports : 38
I/O ports (CMOS) (MB89F538)
Peripheral functions

: 37 (21 have no other function)

Total (except MB89F538) : single-clock system : 53
dual-clock system : 51
Total (MB89F538) : single-clock system : 52
dual-clock system : 50
21 bits
Time base
Interrupt periods at main clock oscillation frequency of 12.5 MHz
timer
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Watchdog Reset period of approx. 167.8 ms to 335.6 ms at main clock frequency of 12.5 MHz
timer Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
8-bit interval timer operation
(supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3)
PWM timer Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 tinst*3)
2 channels (can also be used as interval timer, can also be used as ch1 output and ch2 count
clock)
Interval times at 17-bit sub clock base frequency of 32.768 kHz
Watch prescaler
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
(Continued)

3
 MB89530A Series

(Continued)
Part number
MB89537A/ MB89538A/
MB89535A MB89F538 MB89P538 MB89PV530
537AC 538AC
Parameter
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit reload timer operation
Pulse width
(supports square wave output, operating clock period : 1, 4, 32 tinst*3, external)
count timer
8-bit pulse width measurement operation
(continuous measurement, H width measurement, L width measurement, ↑ to ↑, ↓ to ↓, H
width measurement and ↑ to↑)
16-bit timer operation (operating clock period : 1 tinst*3, external)
16-bit timer/
16-bit event counter operation (select rising, falling, or both edges)
counter
16-bit × 1 ch
8 bit length
Serial I/O Selection of LSB first or MSB first
Transfer clock (2, 8, 32 tinst*3, external)
CLK synchronous/CLK asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8 bit
UART/SIO without parity bit) .
Peripheral functions

Built-in baud rate generator provides selection of 14 baud rate settings.

CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8 bit with parity bit, or 5,
7, 8, 9 bit without parity bit) .
UART Built-in baud rate generator provides selection of 14 baud rate settings.
External clock output, 2-channel 8-bit PWM timer output also available for baud rate
settings.
Single-clock system : 4 channels independent, dual-clock system : 3 channels independent.
External
Selection of rising, falling, or both edge detection.
interrupt 1
Can be used for recovery from standby mode (edge detection also available in stop mode)
External Except MB89F538 : 8 ch, MB89F538 : 7 ch
interrupt 2 Can be used for recovery from standby mode.
6-bit PPG, Can generate square wave signals with programmable period.
12-bit PPG 6-bit × 1 channel or 12-bit × 2 channels.
1-channel , compatible with Intel System Administrator bus version 1.0 and
I2C bus
 Philips I2C specifications.
interface
2-line communications (on MB89PV530/P538/F538/537AC/538AC)
10-bit resolution × 8 channels.
A/D conversion functions (conversion time : 60 tinst*3)
A/D converter Supports repeated calls from external clock (except MB89F538) .
Supports repeated calls from internal clock.
Standard voltage input provided (AVR)
Standby modes
(power saving Sleep mode, stop mode, sub clock mode, watch mode.
modes)
Process CMOS
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : tinst represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock cycle
or 1/2 of the sub clock cycle.
Note : MB89535A/537A/538A have no built-in I2C functions.
To use I2C functions, choose the MB89PV530/MB89P538/F538/537AC/538AC.
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 MB89530A Series

■ MODEL DIFFERENCES AND SELECTION CONSIDERATIONS

Part number MB89537A/ MB89538A/

MB89535A MB89F538 MB89P538 MB89PV530
Package 537AC 538AC

DIP-64P-M01 O O O O O X
FPT-64P-M03 O O O X X X
FPT-64P-M06 O O O O O X
FPT-64P-M09 O O O O O X
MDP-64C-P02 X X X X X O
MQP-64C-P01 X X X X X O
O : Model-package combination available
X : Model-package combination not available
Conversion sockets for pin pitch conversion (manufactured by Sunhayato Corp.) can be used.
Contact : Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp

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 MB89530A Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Capacity
When this product is used in a piggy-back or other evaluation configuration, it is necessary to carefully confirm
the differences between the model being used and the product it is evaluating. Particular attention should be
given to the following (see “ CPU CORE 1.Memory Space”) .
• The program ROM area starts from address 4000H on the MB89F538, MB89P538 and MB89PV530 models.
• Note upper limits on RAM, such as stack areas, etc.
2. Current Consumption
• On the MB89PV530, the additional current consumed by the EPROM is added at the connecting socket on
the back side.
• When operating at low speed, the current consumption in the one-time PROM or EPROM models is greater
than on the mask ROM models. However, current consumption in sleep or stop modes is identical.
For details, refer to “ ELECTRICAL CHARACTERISTICS”.
3. Mask Options
The options available for use, and the method of specifying options, differ according to the model. Before use,
check the “ MASK OPTIONS” specification section.
4. Wild Register Functions
The following table shows areas in which wild register functions can be used.
Wild Register Usage Areas
Part number Address space
MB89PV530 4000H to FFFFH
MB89P538 4000H to FFFFH
MB89F538 4000H to FFFFH
MB89537A/537AC 8000H to FFFFH
MB89538A/538AC 4000H to FFFFH
MB89535A C000H to FFFFH

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 MB89530A Series

■ PIN ASSIGNMENTS

(TOP VIEW)

P36/WTO 1 64 VCC
*4
P37/PTO1 2 63 P35/PWC
P40/INT20/EC 3 A15 65 92 VCC 62 P34/PTO2
P41/INT21/SCK2 4 A12 66 91 A14 61 P33/SI1 (UI1)
P42/INT22/SO2/SDA 5 A7 67 90 A13 60 P32/SO1 (UO1)
P43/INT23/SI2/SCL 6 A6 68 89 A8 59 P31/SCK1 (UCK1) /LMCO
P44/INT24/UCK2 7 A5 69 88 A9 58 P30/PPG03/MCO
P45/INT25/UO2 8 A4 70 87 A11 57 C/N.C. *3
P46/INT26/UI2 9 A3 71 86 OE 56 P00
P47/INT27/ADST/MOD2*1 10 A2 72 85 A10 55 P01
P50/AN0 11 A1 73 84 CE 54 P02
P51/AN1 12 A0 74 83 O8 53 P03
P52/AN2 13 O1 75 82 O7 52 P04
P53/AN3 14 O2 76 81 O6 51 P05
P54/AN4 15 O3 77 80 O5 50 P06
P55/AN5 16 VSS 78 79 O4 49 P07
P56/AN6 17 48 P10
P57/AN7 18 47 P11
AVCC 19 46 P12
AVR 20 45 P13
AVSS 21 44 P14
P60/INT10 22 43 P15
P61/INT11 23 42 P16
P62/INT12 24 41 P17
P63/INT13/X0A*2 25 40 P20/PWCK
P64/X1A*2 26 39 P21/PPG01
RST 27 38 P22/PPG02
MOD0 28 37 P23
MOD1 29 36 P24
X0 30 35 P25
X1 31 34 P26
VSS 32 33 P27

(DIP-64P-M01)
(MDP-64C-P02)

*1 : Pin 10 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 25 and pin 26 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 57 depends on the model. For details, see “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
65 A15 73 A1 81 O6 89 A8
66 A12 74 A0 82 O7 90 A13
67 A7 75 O1 83 O8 91 A14
68 A6 76 O2 84 CE 92 VCC
69 A5 77 O3 85 A10
70 A4 78 VSS 86 OE
71 A3 79 O4 87 A11
72 A2 80 O5 88 A9
N.C. : Internal connection only. Not for use.

(Continued)
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 MB89530A Series

(TOP VIEW)

P31/SCK1 (UCK1) /LMCO

P42/INT22/SO2/SDA
P43/INT23/SI2/SCL

P30/PPG03/MCO
P44/INT24/UCK2

P41/INT21/SCK2
P45/INT25/UO2

P32/SO1 (UO1)
P40/INT20/EC

P33/SI1 (UI1)
P34/PTO2
P37/PTO1

P35/PWC
P36/WTO

C/N.C.*3
VCC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P46/INT26/UI2 1 48 P00
P47/INT27/ADST/MOD2*1 2 47 P01
P50/AN0 3 46 P02
P51/AN1 4 45 P03
P52/AN2 5 44 P04
P53/AN3 6 43 P05
P54/AN4 7 42 P06
P55/AN5 8 41 P07
P56/AN6 9 40 P10
P57/AN7 10 39 P11
AVCC 11 38 P12
AVR 12 37 P13
AVSS 13 36 P14
P60/INT10 14 35 P15
P61/INT11 15 34 P16
P62/INT12 16 33 P17
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P63/INT13/X0A*2
P64/X1A*2
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
P20/PWCK

(FPT-64P-M03)
(FPT-64P-M09)

*1 : Pin 2 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 17 and pin 18 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 49 depends on the model. For details, see “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.

(Continued)

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 MB89530A Series

(Continued)

(TOP VIEW)

P31/SCK1 (UCK1) /LMCO

P42/INT22/SO2/SDA
P43/INT23/SI2/SCL
P44/INT24/UCK2

P41/INT21/SCK2

P32/SO1/ (UO1)
P40/INT20/EC

P33/SI1 (U1)
P34/PTO2
P37/PTO1

P35/PWC
P36/WTO
VCC
64
63
62
61
60
59
58
57
56
55
54
53
52
P45/INT25/UO2 1 *4 51 P30/PPG03/MCO
P46/INT26/UI2 2 50 C/N.C.*3
P47/INT27/ADST/MOD2*1 3 84 49 P00
83
82
81
80
79
78
P50/AN0 4 48 P01
P51/AN1 5 47 P02
P52/AN2 6 85 77 46 P03
P53/AN3 7 86 76 45 P04
P54/AN4 8 87 75 44 P05
P55/AN5 9 88 74 43 P06
P56/AN6 10 89 73 42 P07
P57/AN7 11 90 72 41 P10
AVCC 12 91 71 40 P11
AVR 13 92 70 39 P12
AVSS 14 93 69 38 P13
P60/INT10 15 37 P14
94
95
96
65
66
67
68

P61/INT11 16 36 P15
P62/INT12 17 35 P16
P63/INT13/X0A*2 18 34 P17
P64/X1A*2 19 33 P20/PWCK
20
21
22
23
24
25
26
27
28
29
30
31
32
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01

(FPT-64P-M06)
(MQP-64C-P01)

*1 : Pin 3 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 18 and pin 19 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 50 depends on the model. For details, see “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
65 N.C. 73 A2 81 N.C. 89 OE
66 A15 74 A1 82 O4 90 N.C.
67 A12 75 A0 83 O5 91 A11
68 A7 76 N.C. 84 O6 92 A9
69 A6 77 O1 85 O7 93 A8
70 A5 78 O2 86 O8 94 A13
71 A4 79 O3 87 CE 95 A14
72 A3 80 VSS 88 A10 96 VCC
N.C. : Internal connection only. Not for use.

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 MB89530A Series

■ PIN DESCRIPTIONS
Pin no. I/O
SH-DIP* 1
QFP*3 LQFP*5 Pin name circuit Function
MDIP*2 MQFP*4 QFP*6 type
30 23 22 X0 Connecting pins to crystal oscillator circuit or other os-
A cillator circuit. The X0 pin can connect to an external
31 24 23 X1 clock. In that case, X1 is left open.
28 21 20 MOD0 Input pins for memory access mode setting.
B
29 22 21 MOD1 Connect directly to Vss.
Reset I/O pin. This pin has pull-up resistance with
CMOS I/O or hysteresis input. At an internal reset re-
27 20 19 RST C
quest, an ’L’ signal is output. An ’L’ level input initializes
the internal circuits.
56 to 49 49 to 42 48 to 41 P00 to P07 D General purpose I/O ports.
48 to 41 41 to 34 40 to 33 P10 to P17 D General purpose I/O ports.
General purpose I/O port.Resource I/O pin (hysteresis
40 33 32 P20/PWCK E input).Hysteresis input. This pin also functions as a
PWC input.
P21/ General purpose I/O port.This pin also functions as the
39 32 31 D
PPG01 PPG01 output.
P22/ General purpose I/O port.This pin also functions as the
38 31 30 D
PPG02 PPG02 output.
37 30 29 P23 D General purpose I/O port.
36 29 28 P24 D General purpose I/O port.
35 28 27 P25 D General purpose I/O port.
34 27 26 P26 D General purpose I/O port.
33 26 25 P27 D General purpose I/O port.
P30/
General purpose I/O port.This pin also functions as the
58 51 50 PPG03/ D
PPG03 output.
MCO
P31/SCK1 General purpose I/O port.Resource I/O pin (hysteresis
59 52 51 (UCK1) / E input).This pin also functions as the UART/SIO clock in-
LMCO put/output pin.
P32/SO1 General purpose I/O port.This pin also functions as the
60 53 52 D
(UO1) UART/SIO data output pin.
General purpose I/O port.Resource input/output pin
P33/SI1
61 54 53 E (hysteresis input).This pin also functions as the UART/
(UI1)
SIO serial data input pin.
General purpose I/O port.This pin also functions as the
62 55 54 P34/PTO2 D
PWM timer 2 output pin.
General purpose I/O port.Resource I/O pin (hysteresis
63 56 55 P35/PWC E
input).This pin also functions as a PWC input.
(Continued)

10
 MB89530A Series

Pin no. I/O

Pin
SH-DIP* 1
QFP*3 LQFP*5 circuit Function
name
MDIP*2 MQFP*4 QFP*6 type
P36/ General purpose I/O port.Resource output.
1 58 57 D
WTO This pin also functions as the PWC output pin.
P37/ General purpose I/O port.Resource output.
2 59 58 D
PTO1 This pin also functions as the PWM timer 1 output pin.
P40/ General purpose I/O port.Resource I/O pin (hysteresis
3 60 59 INT20/ E input)This pin also functions as an external interrupt
EC input or 16-bit timer/counter input.
P41/ General purpose I/O port.Resource I/O pin (hysteresis
4 61 60 INT21/ E input)This pin also functions as an external interrupt
SCK2 input or SIO clock I/O pin.
P42/ N-ch open drain output.
INT22/ Resource I/O pin (hysteresis only for INT22 input) .
5 62 61 G
SO2/ This pin also functions as an external interrupt input,
SDA SIO serial data output, or I2C data line.
N-ch open drain output.
P43/
Resource I/O pin (hysteresis only for INT23 input) .
6 63 62 INT23/ G
This pin also functions as an external interrupt, SIO
SI2/SCL
serial data input, or I2C clock I/O pin.
General purpose I/O port.
P44/
Resource I/O pin (hysteresis input) .
7 64 63 INT24/ E
This pin also functions as an external interrupt input or
UCK2
UART clock I/O pin.
General purpose I/O port.
P45/
Resource I/O pin (hysteresis input) .
8 1 64 INT25/ E
This pin also functions as an external interrupt input or
UO2
UART data output pin.
General purpose I/O port.
P46/
Resource I/O pin (hysteresis input) .
9 2 1 INT26/ E
This pin also functions as an external interrupt input or
UI2
UART data input pin.

P47/ Except MB89F538

INT27/ E General purpose I/O port.
ADST Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
10 3 2
A/D converter clock input pin.
MB89F538
MOD2 B Input pins for memory access mode setting.
Connect directly to Vss.
P50/AN0 N-ch open drain output port.
11 to 18 4 to 11 3 to 10 to P57/ H This pin also functions as an A/D converter analog input
AN7 pin.
(Continued)

11
 MB89530A Series

(Continued)
Pin no. I/O
SH-DIP* 1
QFP*3 LQFP*5 Pin name circuit Function
MDIP*2 MQFP*4 QFP*6 type
P60/INT10 General purpose input port.
22 to 24 15 to 17 14 to 16 to I Resource input pin (hysteresis input) .
P62/INT12 This pin also functions as an external interrupt input pin.
General purpose input port.
Resource input (hysteresis
P63/INT13 I Single-clock system input) .
25 18 17 This pin also functions as an
external interrupt.
X0A A Dual-clock system Connected pin for sub clock.
P64 J Single-clock system General purpose input port.
26 19 18
X1A A Dual-clock system Connected pin for sub clock.
64 57 56 VCC  Power supply pin.
32 25 24 VSS  Ground pin (GND) .
19 12 11 AVCC  A/D converter power supply pin.
20 13 12 AVR  A/D converter reference voltage input pin.
A/D converter power supply pin.
21 14 13 AVSS 
Used at the same voltage level as the Vss supply.
Capacitor connection pin for
stabilization power supply.
MB89F538 Connect an external ceramic
capacitor of approximately
0.1 µF.
57 50 49 C 
MB89P538 Fixed at Vss.
MB89PV530
MB89537A/537AC
N.C. pin
MB89538A/538AC
MB89535A
*1 : DIP-64P-M01
*2 : MDP-64C-P02
*3 : FPT-64P-M06
*4 : MQP-64C-P01
*5 : FPT-64P-M03
*6 : FPT-64P-M09

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 MB89530A Series

External EPROM Socket Pin Function Descriptions (MB89PV530 only)

Pin no. I/O Circuit
Pin name Function
MDIP* 1
MQFP*2 type

65 66 A15
66 67 A12
67 68 A7
68 69 A6
69 70 A5
O Address output pins.
70 71 A4
71 72 A3
72 73 A2
73 74 A1
74 75 A0
75 77 O1
76 78 O2 I Data input pins
77 79 O3
78 80 VSS O Power supply pin (GND) .
79 82 O4
80 83 O5
81 84 O6 I Data input pins.
82 85 O7
83 86 O8
ROM chip enable pin.
84 87 CE O
Outputs an “H” level signal in standby mode.
85 88 A10 O Address output pin.
ROM output enable pin.
86 89 OE O
Outputs “L” at all times.
87 91 A11
88 92 A9 O
89 93 A8
Address output pins.
90 94 A13 O
91 95 A14 O
92 96 VCC O EPROM power supply pin.
65
76 Internally connected.
 N.C. O
81 These pins always left open.
90
*1 : MDP-64C-P02
*2 : MQP-64C-P01

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 MB89530A Series

■ I/O CIRCUIT TYPES

Type Circuit Remarks
Oscillator feedback resistance
X1 (X1A) • High speed side = approx. 1 MΩ
Nch Pch • Low speed side = approx. 10 MΩ
X0 (X0A) Pch
A
Nch

• Hysteresis input
• Pull-down resistance built-in to
B MB89535A
MB89537A/537AC
MB89538A/538AC
• Pull-up resistance approx. 50 kΩ
R • Hysteresis input
Pch

C
Nch

• CMOS I/O
• Software pull-up resistance can be
R Pull-up control
Pch used. Approx. 50 kΩ
resistor
Pch
D

Nch

• CMOS I/O
R
• Software pull-up resistance can be
Pull-up control
Pch used. Approx. 50 kΩ
resistors
Pch

Nch
Port input
Resource input

(Continued)

14
 MB89530A Series

(Continued)
Type Circuit Remarks
• N-ch open drain output
• Hysteresis input
Nch • CMOS input
G
Resource input
Port input

• N-ch open drain output

• Analog input (A/D converter)
Pch

H
Nch

Analog input

• Hysteresis input
R
• CMOS input
Pch • Software pull-up resistance can be
Pull-up control resistors
I used. Approx. 50 kΩ
Resource
Port

• CMOS input
R
• Software pull-up resistance can be
Pch used. Approx. 50 kΩ
Pull-up control resistors
J

Port

15
 MB89530A Series

■ HANDLING DEVICES
1.Preventing Latchup
Care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latchup) . When CMOS
integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other than
medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess of
rated levels are applied between Vcc and Vss, the phenomenon known as latchup can occur.
When a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor
elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also when switching power on or off to analog systems, care must be taken that analog power supplies (AVCC,
AVR) and analog input signals do not exceed the level of the digital power supply.

2.Power Supply Voltage Fluctuations

Even within the warranted operating range of the Vcc supply voltage, sudden changes in supply voltage can
cause abnormal operation. As a measure for stability, it is recommended that the Vcc ripple fluctuation (peak to
peak value) should be kept within 10% of the reference Vcc value on commercial power supply (50 Hz-60 Hz),
and instantaneous voltage fluctuations such as at power-on and shutdown should be kept within a transient
variability limit of 0.1V/ms.

3.Treatment of Unused Input Pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistance.

4. Treatment of N.C. Pins

Any pins marked ’NC’ (not connected) must be left open.

5. Treatment of Power Supply Pins on Models with Built-in A/D Converter

Even when A/D converters are not in use, pins should be connected so that AVCC = VCC, and AVSS = AVR = VSS.

6. Precautions for Use of External Clock

Even when an external clock signal is used, an oscillator stabilization wait period is used after a power-on reset,
or escape from sub clock mode or stop mode.

7. Execution of Programs on RAM

Debugging of programs executed on RAM cannot be performed even when using the MB89PV530.

8. Wild Register Functions

Wild registers cannot be debugged with the MB89PV530 and tools. To verify operations, actual in-device testing
on the MB89P538 or MB89F538 is advised.

16
 MB89530A Series

9. Details on handling the C terminal of the MB89530 series

The MB89530 series contains the following products. The regulator integrated model and the regulator-less
model have different performance characteristics.
Part No. Operation Voltage integrated model Terminal type Terminal treatments
MB89PV530 Not included N.C terminal Not required
2.7 V to 5.5 V Included Fixed to VCC
MB89P538
Not included Fixed to VSS
C terminal
0.1 µF capacitor
MB89F538 3.5 V to 5.5 V Included
connected
MB89537A/537AC
MB89538A/538AC 2.2 V to 5.5 V Not included N.C terminal Not required
MB89535A
Although these product models have the same internal resources, the operation sequence after a power-on
reset is different between the regulator integrated model and regulator-less model.
The operation sequence after a power-on reset of each model is shown below.

Voltage step-down circuit stabilization time

Power supply (VCC) + oscillation stabilization time
(219/Fch)

CPU operation of regulator Oscillation stabiliza-

integrated model (MB89F538 only) tion time (218/Fch)

CPU operation of regurator-less

model (exclude MB89F538)

CPU started on regulator-less CPU started on regulator

model (Reset vector) integrated model (Reset vector)

Fch : Crystal oscillator frequency

As avobe, the regulator integrated model starts the CPU behind the regulator-less model. This is because the
regulator requires a settling time for normal operation.
The MB89P538 offers a choice of regulator-integrated and regulator-less models selectable depending on the
C-terminal treatment. Use the right one for your mask board.

10. Note to Noise in the External Reset Pin (RST)

If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunc-
tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).

17
 MB89530A Series

■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F538

1. Flash Memory
The flash memory is located between 4000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.

2. Flash Memory Features

• 48 K byte × 8-bit configuration (16 K + 8 K + 8 K + 16 K sectors)
• Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
*: Embedded Algorithm is a trademark of Advanced Micro Devices.

3. Procedure for Programming and Erasing Flash Memory

Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.

4. Flash Memory Register

• Control status register (FMCS)

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
007AH INTE RDYINT WE RDY Reserved Reserved  Reserved 000X00-0B

R/W R/W R/W R R/W R/W  R/W

5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.

• Sector configuration of flash memory

Flash Memory CPU Address Programmer Address*
16 K bytes FFFFH to C000H 1FFFFH to 1C000H
8 K bytes BFFFH to A000H 1BFFFH to 1A000H
8 K bytes 9FFFH to 8000H 19FFFH to 18000H
16 K bytes 7FFFH to 4000H 17FFFH to 14000H

* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a general-
purpose parallel programmer.
18
 MB89530A Series

6. ROM Programmer Adaptor and Recommended ROM Programmers

Recommended Programmer
Adaptor Part No.
Part number Package Manufacturer and Model
Sunhayato Corp. Ando Electric Co. Ltd.
MB89F538-101PF
FPT-64P-M06 FLASH-64QF-32DP-8LF
MB89F538-201PF
MB89F538-101PFM AF9708*
FPT-64P-M09 FLASH-64QF2-32DP-8LF2
MB89F538-201PFM AF9709*
MB89F538-101P-SH
DIP-64P-M01 FLASH-64SD-32DP-8LF
MB89F538-201P-SH
* : For the version of the programmer, contact the Flash Support Group, Inc.

• Enquiries
Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp
Flash Support Group, Inc. : FAX : +81-53-428-8377
E-mail : support@j-fsg.co.jp

19
 MB89530A Series

■ ONE-TIME WRITING SPECIFICATIONS WITH PROM AND EPROM MICROCONTROLLERS

The MB89P538 has a PROM mode with functions equivalent to the MBM27C1001, allowing writing with a general
purpose ROM writer using a proprietary adapter. Note, however, that the use of electronic signature mode is
not supported.

• ROM writer adapters

With some ROM writers, stability of writing performance is enhanced by placing an 0.1µF capacitor between
the Vcc and Vss pins. The following table lists adapters for use with ROM writers.

ROM Writer Adapters

Part number Package Compatible adapter
MB89P538-101PF
FPT-64P-M06 ROM-64QF-32DP-8LA2*
MB89P538-201PF
MB89P538-101PFM
FPT-64P-M09 ROM-64QF2-32DP-8LA
MB89P538-201PFM
MB89P538-101P-SH
DIP-64P-M01 ROM-64SD-32DP-8LA2*
MB89P538-201P-SH
Inquiries should be addressed to Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-5396-9106
E-mail : adapter@sunhayato.co.jp
* : Version 3 or later should be used.

• Memory map for EPROM mode

The following illustration shows a memory map for EPROM mode. There are no PROM options.

Normal operating mode EPROM mode (corresponding

addresses on EPROM writer)
0000H 0000H
I/O
0080H
RAM
0100H
General
purpose Prohibited
0200H register
0880H

Prohibited
4000H 4000H

ROM Program
(EPROM)
FFFFH FFFFH
Prohibited
1FFFFH

20
 MB89530A Series

• Recommended screening conditions

Before one-time writing of microcontroller programs to PROM, high temperature aging is recommended as a
screening process for chips before they are mounted.

Program, verify

High temperature aging

+150 °C, 48 h

Read

Mount

• About writing yields

The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit
writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.

21
 MB89530A Series

■ EPROM WRITING TO PIGGY-BACK/EVALUATION CHIPS

This section describes methods of writing to EPROM on piggy-back/evaluation chips.

• EPROM model
MBM27C512-20TV

• Writer adapter
For writing to EPROM using a ROM writer, use one of the writer adapters shown below (manufactured by
Sunhayato Corp.) .
Package Adapter socket model
LCC-32 (rectangular) ROM-32LC-28DP-YG
Inquiries should be addressed to Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp

• Memory Space

(Corresponding address on
Normal operating mode ROM writer)
0000H 0000H
I/O
0080H

RAM Prohibited
0880H
Prohibited
4000H 4000H

PROM EPROM
48 KB

FFFFH FFFFH

• Writing to EPROM
1) Set up the EPROM writer for the MBM27C512.
2) Load program data to the ERPOM writer, in the area 4000H - FFFFH.
3) Use the EPROM writer to write to the area 4000H - FFFFH.

22
 MB89530A Series

■ BLOCK DIAGRAM

Sub clock
Low voltage

Port 0
P63/INT13/X0A*1 oscillator circuit CMOS I/O port 8
(32.786 kHz) P00 ∼ P07
P64/X1A*1

Clock control

Port 1
8
P60/INT10 ∼ P10 ∼ P17
Port 6

Watch prescaler
P62/INT12 CMOS I/O port
4 External interrupt 1
(edge)
12-bit PPG01

Port 2
P20/PWCK
CMOS I/O port P21/PPG01
Main clock 12-bit PPG02
P22/PPG02
X0
X1
Oscillator circuit P23 ∼ P27
CMOS I/O port
Internal databus
Clock controller
Reset circuit SIO P40/INT20/EC
RST (watchdog timer) P41/INT21/SCK2
UART
P42/INT22/
21-bit time

N-ch I/O
SO2/SDA
base timer I2C
P43/INT23/
SI2/SCL
P30/PPG03/MCO 6-bit PPF03 16-bit timer/
P44/INT24/UCK2
counter 1
P31/SCK1 (UCK1) 8-bit

Port 4
PWM timer 2 P45/INT25/UO2
/LMCO
External interrupt 2
P32/SO1 (UO1) P46/INT26/UI2
(level)
Port 3

8-bit
P33/SI1 (UI1) PWM timer 1 P47/INT27/ADST*2

P34/PTO2 UART/SIO CMOS I/O port

P35/PWC
PWC
P36/WTO
N-ch output
Port 5

8
P37/PTO1 CMOS I/O port P50/AN0 ∼
8 P57/AN7

1KB RAM/2KB RAM 10-bit AVCC

A/D converter AVR
F2MC-8L
AVSS
CPU

Wild register

32KB ROM/48KB ROM

Other pins
MOD0, MOD1, C, VCC, VSS, C/NC

*1 : P63/INT13, P64 pins for single-clock system and X0A, X1A pins dual-clock system
*2 : P47/INT27/ADST pins are MOD2 pin for MB89F538.

23
 MB89530A Series

■ CPU CORE
1. Memory Space
The MB89530A series has 64 KB of memory space, containing all I/O, data areas, and program areas. The I/O
area is located at the lowest addresses, with the data area placed immediately above. The data area can be
partitioned into register areas, stack areas, or direct access areas depending on the application. The program
area is located at the opposite end of memory, closest to the highest addresses, and the highest part of this
area is assigned to the tables of interrupt and reset vectors and vector call instructions. The following diagram
shows the structure of memory space in the MB89530A series.

• Memory Map

MB89PV530
MB89P538/F538
MB89535A MB89537A/537AC MB89538A/538AC

0000H 0000H 0000H

I/O I/O I/O
0080H 0080H 0080H
RAM RAM RAM
0100H 0100H 0100H
General General General
purpose purpose purpose
register register register
0200H 0200H 0200H

0280H
0480H
Open Open 0880H
Open
0C80H 0C80H 0C80H
Wild register Wild register Wild register
0C91H 0C91H 0C91H

Open
Open Open
4000H
8000H
C000H ROM
ROM External ROM*1
ROM

FFC0H FFC0H FFC0H

Vector tables*2 Vector tables*2 Vector tables*2
FFFFH FFFFH FFFFH

*1 : The external ROM area is on the MB89PV530 only.

*2 : Vector tables (reset, interrupt, vector call instructions)

24
 MB89530A Series

2. Registers
The F2MC-8L series has two types of registers, dedicated-use registers within the CPU, and general-purpose
registers in memory.
Program counter (PC) : 16-bit length, shows the location where instructions are stored.
Accumulator (A) : 16-bit length, a temporary memory register for calculation operations.
The lower byte is used for 8-bit data processing instructions.
Temporary accumulator (T) : 16-bit length, performs calculations with the accumulator.
The lower byte is used for 8-bit data processing instructions.
Index register (IX) : 16-bit length, a register for index modification.
Extra pointer (EP) : 16-bit length, a pointer indicating memory addresses.
Stack pointer (SP) : 16-bit length, indicates stack areas.
Program status (PS) : 16-bit length, contains register pointer and condition code.

16 bits
Initial value
PC : Program counter FFFDH

A : Accumulator Not fixed

T : Temporary accumulator Not fixed

IX : Index register Not fixed

EP : Extra pointer Not fixed

SP : Stack pointer Not fixed

PS : Program status I-flag = 0, IL1, 0 = 11

Other bits not fixed

In addition, the PS register can be divided so that the upper 8 bits are used as a register bank pointer (RP), and
the lower 8 bits as a condition code register (CCR). (See the following illustration.)

• Program status register configuration

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS RP Open Open Open H I IL1 IL0 N Z V C

RP CCR

25
 MB89530A Series

The RP register shows the address of the register bank currently being used, so that the RP value and the actual
address are related by the conversion rule shown in the following illustration.

• General purpose register area real address conversion principle

Operation code
RP upper lower
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0
Address
generated A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR register has bits that show the content of results of calculations and transferred data, and bits that
control CPU operation during interrupts.

H-flag : Set to 1 if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to 0.
This flag is used for decimal correction instructions.
I-flag : This flag is set to 1 if interrupts are enabled, and 0 if interrupts are prohibited.
The default value at reset is 0.
IL1, 0 : Indicates the level of the currently permitted interrupts.
Only interrupt requests having a more powerful level than the value of these bits will be processed.
IL1 IL0 Interrupt level Strength
0 0 Strong
1
0 1
1 0 2
1 1 3 Weak

N-flag : Set to 1 if the highest bit is 1 after a calculation, otherwise cleared to 0.

Z-flag : Set to 1 if a calculation result is 0, otherwise cleared to 0.
V-flag : Set to 1 if a two’s complement overflow results during a calculation, otherwise cleared to 0.
C-flag : Set to 1 if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to 0.
This is also the shift-out value in a shift instruction.

In addition, the following general purpose registers are available.

General purpose registers: 8-bit length, used to contain data.

The general purpose registers are 8-bit registers located in memory. There are eight such registers per bank,
and the MB89530A series have up to 32 banks for use. The bank currently in use is indicated by the register
bank pointer (RP).

26
 MB89530A Series

•Register bank configuration

Address at this location

= 0100H + 8 × (RP) R0

R1

R2

R3

R4

R5

R6

R7
32 banks

Memory area

27
 MB89530A Series

■ I/O MAP
Register
Address Register description Write/Read Initial value
name
00H PDR0 Port 0 data register R/W XXXXXXXXB
01H DDR0 Port 0 direction register W 0 0 0 0 0 0 0 0B
02H PDR1 Port 1 data register R/W XXXXXXXXB
03H DDR1 Port 1 direction register W 0 0 0 0 0 0 0 0B
04H to 06H (Reserved area)
07H SYCC System clock control register R/W X -1 MM1 0 0B
08H STBC Standby control register R/W 0 0 0 1 0 - - -B
09H WDTC Watchdog control register R/W 0 - - - XXXXB
0AH TBTC Time base timer control register R/W 0 0 - - - 0 0 0B
0BH WPCR Watch prescaler control register R/W 0 0 - - 0 0 0 0B
0CH PDR2 Port 2 data register R/W XXXXXXXXB
0DH DDR2 Port 2 direction register R/W 0 0 0 0 0 0 0 0B
0EH PDR3 Port 3 data register R/W XXXXXXXXB
0FH DDR3 Port 3 direction register R/W 0 0 0 0 0 0 0 0B
10H PDR4 Port 4 data register R/W XXXX 1 1 XXB
11H DDR4 Port 4 direction register R/W 0 0 0 0 - - 0 0B
12H PDR5 Port 5 data register R/W 11111111B
13H PDR6 Port 6 data register R XXXXXXXXB
14H to 21H (Reserved area)
22H SMC11 Serial mode control register 1 (UART) R/W 0 0 0 0 0 0 0 0B
23H SRC1 Serial rate control register (UART) R/W - - 0 1 1 0 0 0B
24H SSD1 Serial status and data register (UART) R/W 0 0 1 0 0 - 1XB
SIDR1/
25H Serial input/output data register (UART) R/W XXXXXXXXB
SODR1
26H SMC12 Serial mode control register 2 (UART) R/W - - 1 0 0 0 0 1B
27H CNTR1 PWM control register 1 R/W 0 0 0 0 0 0 0 0B
28H CNTR2 PWM control register 2 R/W 0 0 0 - 0 0 0 0B
29H CNTR3 PWM control register 3 R/W - 0 0 0 - - - -B
2AH COMR1 PWM compare register 1 W XXXXXXXXB
2BH COMR2 PWM compare register 2 W XXXXXXXXB
2CH PCR1 PWC pulse width control register 1 R/W 0 0 0 - - 0 0 0B
2DH PCR2 PWC pulse width control register 2 R/W 0 0 0 0 0 0 0 0B
2EH RLBR PWC reload buffer register R/W XXXXXXXXB
2FH SMC21 Serial mode control register 1 (UART/SIO) R/W 0 0 0 0 0 0 0 0B
30H SMC22 Serial mode control register 2 (UART/SIO) R/W 0 0 0 0 0 0 0 0B
31H SSD2 Serial status and data register (UART/SIO) R/W 0 0 0 0 1 - - -B
SIDR2/
32H Serial data register (UART/SIO) R/W XXXXXXXXB
SODR2
33H SRC2 Baud rate generator reload register R/W XXXXXXXXB
(Continued)

28
 MB89530A Series

Register
Address Register description Write/Read Initial value
name
34H ADC1 A/D control register 1 R/W 0 0 0 0 0 0 - 0B
35H ADC2 A/D control register 2 R/W - 0 0 0 0 0 0 1B
36H ADDL A/D data register low R/W XXXXXXXXB
37H ADDH A/D data register high R/W - - - - - - 0 0B
38H PPGC2 PPG2 control register (12-bit PPG) R/W 0 0 0 0 0 0 0 0B
39H PRL22 PPG2 reload register 2 (12-bit PPG) R/W 0X0 0 0 0 0 0B
3AH PRL21 PPG2 reload register 1 (12-bit PPG) R/W XX0 0 0 0 0 0B
3BH PRL23 PPG2 reload register 3 (12-bit PPG) R/W XX0 0 0 0 0 0B
3CH TMCR 16-bit timer control register R/W - - 0 0 0 0 0 0B
3DH TCHR 16-bit timer counter register high R/W 0 0 0 0 0 0 0 0B
3EH TCLR 16-bit timer counter register low R/W 0 0 0 0 0 0 0 0B
3FH EIC1 External interrupt 1 control register 1 R/W 0 0 0 0 0 0 0 0B
40H EIC2 External interrupt 1 control register 2 R/W 0 0 0 0 0 0 0 0B
41H to 48H (Reserved area)
49H DDCR DDC select register R/W - - - - - - - 0B
4AH to 4BH (Reserved area)
4CH PPGC1 PPG1 control register (12-bit PPG) R/W 0 0 0 0 0 0 0 0B
4DH PRL12 PPG1 reload register 2 (12-bit PPG) R/W 0X0 0 0 0 0 0B
4EH PRL11 PPG1 reload register 1 (12-bit PPG) R/W XX0 0 0 0 0 0B
4FH PRL13 PPG1 reload register 3 (12-bit PPG) R/W XX0 0 0 0 0 0B
2
50H IACR I C address control register R/W - - - - - 0 0 0B
2
51H IBSR I C bus status register R 0 0 0 0 0 0 0 0B
2
52H IBCR I C bus control register R/W 0 0 0 0 0 0 0 0B
53H ICCR I2C clock control register R/W 0 0 0 XXXXXB
2
54H IADR I C address register R/W - XXXXXXXB
2
55H IDAR I C data register R/W XXXXXXXXB
56H EIE2 External interrupt 2 control register R/W 0 0 0 0 0 0 0 0B
57H EIF2 External interrupt 2 flag register R/W - - - - - - - 0B
58H RCR1 6-bit PPG control register 1 R/W 0 0 0 0 0 0 0 0B
59H RCR2 6-bit PPG control register 2 R/W 0X0 0 0 0 0 0B
5AH CKR Clock output control register R/W - - - - - - 0 0B
5BH to 6FH (Reserved area)
70H SMR Serial mode register (SIO) R/W 0 0 0 0 0 0 0 0B
71H SDR Serial data register (SIO) R/W XXXXXXXXB
72H PURR0 Port 0 pull-up resistance register R/W 11111111B
73H PURR1 Port 1 pull-up resistance register R/W 11111111B
74H PURR2 Port 2 pull-up resistance register R/W 11111111B
75H PURR3 Port 3 pull-up resistance register R/W 11111111B
76H PURR4 Port 4 pull-up resistance register R/W 1 1 1 1 - -1 1 B
77H WREN Wild register enable register R/W - - 0 0 0 0 0 0B
(Continued)
29
 MB89530A Series

(Continued)
Register
Address Register description Write/Read Initial value
name
78H WROR Wild register data test register R/W - - 0 0 0 0 0 0B
79H PURR6 Port 6 pull-up resistance register R/W ---11111B
7AH FMCS Flash memory control status resister R/W 0 0 0 0 0 0 - 0B
7BH ILR1 Interrupt level setting register 1 W 1 1 1 1 1 1 1 1B
7CH ILR2 Interrupt level setting register 2 W 1 1 1 1 1 1 1 1B
7DH ILR3 Interrupt level setting register 3 W 1 1 1 1 1 1 1 1B
7EH ILR4 Interrupt level setting register 4 W 1 1 1 1 1 1 1 1B
7FH ITR Interrupt test register Access prohibited XXXXXX0 0B
C80H WRARH1 Upper address setting register 1 R/W XXXXXXXX
C81H WRARL1 Lower address setting register 1 R/W XXXXXXXX
C82H WRDR1 Data setting register 1 R/W XXXXXXXX
C83H WRARH2 Upper address setting register 2 R/W XXXXXXXX
C84H WRARL2 Lower address setting register 2 R/W XXXXXXXX
C85H WRDR2 Data setting register 2 R/W XXXXXXXX
C86H WRARH3 Upper address setting register 3 R/W XXXXXXXX
C87H WRARL3 Lower address setting register 3 R/W XXXXXXXX
C88H WRDR3 Data setting register 3 R/W XXXXXXXX
C89H WRARH4 Upper address setting register 4 R/W XXXXXXXX
C8AH WRARL4 Lower address setting register 4 R/W XXXXXXXX
C8BH WRDR4 Data setting register 4 R/W XXXXXXXX
C8CH WRARH5 Upper address setting register 5 R/W XXXXXXXX
C8DH WRARL5 Lower address setting register 5 R/W XXXXXXXX
C8EH WRDR5 Data setting register 5 R/W XXXXXXXX
C8FH WRARH6 Upper address setting register 6 R/W XXXXXXXX
C90H WRARL6 Lower address setting register 6 R/W XXXXXXXX
C91H WRDR6 Data setting register 6 R/W XXXXXXXX

• Description of write/read symbols :

R/W : read/write enabled
R : Read only
W : Write only

• Description of initial values :

0 : This bit initialized to “0”.
1 : This bit initialized to “1”.
X : The initial value of this bit is not determined.
M : The initial value of this bit is a mask option.
- : This bit is not used.

Note : Do not use reserved spaces.

30
 MB89530A Series

■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVss = Vss = 0 V)
Rating
Parameter Symbol Unit Remarks
Min Max
VCC, MB89535A/537A/538A*
VSS − 0.3 VSS + 6.0 V
AVCC MB89537AC/538AC
Supply voltage
MB89F538/P538
AVR VSS − 0.3 VSS + 6.0 V MB89PV530
VSS − 0.3 VCC + 0.3 V Other than P42, P43
Input voltage VI
VSS − 0.3 VSS + 6.0 V P42, P43
VSS − 0.3 VCC + 0.3 V Other than P42, P43
Output voltage VO
VSS − 0.3 VSS + 6.0 V P42, P43
“L” level maximum output
IOL  15 mA
current
“L” level average output Average value
IOLAV  4 mA
current (operating current × operating duty)
“L” level maximum total
ΣIOL  100 mA
output current
“L” level average total output Average value
ΣIOLAV  40 mA
current (operating current × operating duty)
“H” level maximum output
IOH  −15 mA
current
“H” level average output Average value
IOHAV  −4 mA
current (operating current × operating duty)
“H” level maximum total
ΣIOH  −50 mA
output current
“H” level average total Average value
ΣIOHAV  −20 mA
output current (operating current × operating duty)
Current consumption PD  300 mW
Operating temperature TA −40 +85 °C
Storage temperature Tstg −55 +150 °C
* : AVcc and Vcc are to be used at the same potential. AVR should not exceed AVcc + 0.3V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

31
 MB89530A Series

2. Recommended Operating Conditions

(AVss = Vss = 0 V)
Value
Parameter Symbol Unit Remarks
Min Max
Range warranted for MB89535A
2.2* 5.5 V
normal operation MB89537A/538A
RAM status in stop MB89537AC/
1.5 5.5 V 538AC
mode
Range warranted for
2.7* 5.5 V
VCC, normal operation MB89P538
Supply voltage AVCC RAM status in stop MB89PV530
1.5 5.5 V
mode
Range warranted for
3.5 5.5 V
normal operation
MB89F538
RAM status in stop
3.0 5.5 V
mode
AVR 3.5 AVCC V
Operating temperature TA −40 +85 °C
* : Varies according to frequency used, and instruction cycle.
See “Operating voltage vs. operating frequency ” and “5. A/D Converter Electrical Characteristics”.

32
 MB89530A Series

Operating voltage vs. operating frequency (MB89P538/MB89PV530)

Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V

5.5
5.0
Operating voltage VCC (V)

4.0
3.5
3.0
2.7
2.2
2.0
,,,,,,,,











1.0

0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / Fc)

4.0 2.0 0.8 0.4 0.32

,,
Minimum instruction execution time (Instruction cycles) (µs)






,,
 indicates warranted operation at TA = −10 °C to +55 °C

Operating voltage vs. operating frequency (MB89535A/537A/538A/537AC/538AC)

Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V

5.5
5.0
Operating voltage VCC (V)

4.0
3.5
3.0
2.7
2.2
2.0

1.0

0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / Fc)

4.0 2.0 0.8 0.4 0.32

Minimum instruction execution time (Instruction cycles) (µs)

33
 MB89530A Series

Operating voltage vs. operating frequency (MB89F538)

Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V

5.5
5.0
Operating voltage VCC (V)

4.0
3.5
3.0

2.0

1.0

0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)

4.0 2.0 0.8 0.4 0.32

Minimum instruction execution time (Instruction cycles) (µs)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

34
 MB89530A Series

3. DC Characteristics
(1) Supply Voltage at 5.0 (V)
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VIH  0.7 VCC  VCC + 0.3 V
P40 to P47, P60 to P64,
SI1, SI2
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
“H” level UI1, INT10 to INT13,
VIHS  0.8 VCC  VCC + 0.3 V
input voltage SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
With SMB input
VIHSMB  VSS + 1.4  VSS + 5.5 V
buffer selected*
SCL, SDA
With I2C input
VIHI2C  0.7 VCC  VSS + 5.5 V
buffer selected*
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VIL  VSS − 0.3  0.3 VCC V
P40 to P47, P60 to P64,
SI1, SI2
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
“L” level UI1, INT10 to INT13,
VILS  VSS − 0.3  0.2 VCC V
input voltage SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
With SMB input
VILSMB  VSS − 0.3  VSS + 0.6 V
buffer selected*
SCL, SDA
With I2C input
VILI2C  VSS − 0.3  0.3 VCC V
buffer selected*
Open drain VD1 P50 to P57 VCC + 0.3 V
output applied  VSS − 0.3 
voltage VD2 P42, P43 VSS + 5.5 V

P00 to P07, P10 to P17,

IOH =
P20 to P24, P30 to P37,
“H” level −2.0 mA
VOH P40, P41, P44 to P47 4.0   V
output voltage
IOH =
P25 to P27
−3.0 mA
P00 to P07, P10 to P17,
“L” level
P20 to P27, P30 to P37, IOL =
output VOL   0.4 V
P40 to P47, P50 to P57, 4.0 mA
voltage
RST
(Continued)

35
 MB89530A Series

(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)

Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
Input leak P00 to P07, P10 to P17,
current P20 to P27, P30 to P37, 0.0 V < VI < With no pull-up re-
ILI −5  +5 µA
(Hi-Z output P40 to P47, P50 to P57, VCC sistance specified
leak current) P60 to P64
Open drain
0.0 V < VI <
output leak ILIOD P42, P43   +5 µA
VSS + 5.5 V
current
P00 to P07, P10 to P17, With pull-up
Pull-up P20 to P27, P30 to P37, resistance speci-
RPULL VI = 0.0 V 25 40 100 kΩ
resistance P40, P41, P44 to P47, fied. The RST sig-
P60 to P64, RST nal is excluded.
MB89P538/
 15 20 mA
PV530
FCH = 10.0 MHz
 6 10 mA MB89F538
ICC1 VCC = 5.0 V
tinst = 0.4 µs MB89535A/7A/8A
 8 13 mA MB89537AC/
538AC
MB89P538/
 5 8.5 mA
PV530
FCH = 10.0 MHz
 1.5 3 mA MB89F538
ICC2 VCC = 5.0 V
tinst = 6.4 µs MB89535A/7A/8A
 1.5 3 mA MB89537AC/
538AC
Sleep mode
 5 7 mA MB89P538/
Supply PV530
VCC
current
FCH = 10.0 MHz Sleep mode
 3 5 mA
ICCS1 VCC = 5.0 V MB89F538
tinst = 0.4 µs
Sleep mode
MB89535A/7A/8A
 2.5 5 mA
MB89537AC/
538AC
Sleep mode
 1.5 3 mA MB89P538/
PV530
FCH = 10.0 MHz Sleep mode
 1 2 mA
ICCS2 VCC = 5.0 V MB89F538
tinst = 6.4 µs
Sleep mode
MB89535A/7A/8A
 1 2 mA
MB89537AC/
538AC
(Continued)

36
 MB89530A Series

(Continued)
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
Sub mode
 3 7 mA MB89P538/
PV530
FCL =
Sub mode
32.768 kHz  400 800 µA
ICCL MB89F538
VCC = 5.0 V
TA = +25 °C Sub mode
MB89535A/7A/8A
 50 85 µA
MB89537AC/
538AC
Sub, sleep mode
 30 50 µA MB89P538/
VCC PV530
FCL = 32.768
Supply Sub, sleep mode
kHz  15 30 µA
current ICCLS MB89F538
VCC = 5.0 V
TA = +25 °C Sub, sleep mode
MB89535A/7A/8A
 15 30 µA
MB89537AC/
538AC
FCL =
32.768 kHz Watch mode,
ICCT  5 15 µA
VCC = 5.0 V main stop
TA = +25 °C
ICCH TA = +25 °C  3 10 µA Sub, stop modes
A/D conversion
IA FCH = 10.0 MHz  4 6 mA
AVCC running
IAH TA = +25 °C  1 5 µA A/D stopped
Input Except VCC, VSS, AVCC,
CIN f = 1 MHz  5 15 pF
capacitance AVSS
* : The MB89PV530/P538/537AC/538AC have a built-in I2C function, and a choice of input buffers by software setting.
MB89535A/537A/538A have no built-in I2C functions, and therefore this standard does not apply.

37
 MB89530A Series

(2) Supply Voltage at 3.0 (V) (except MB89F538)

(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VIH  0.7 VCC  VCC + 0.3 V
P40 to P47, P60 to P64,
SI1, SI2
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
VIHS  0.8 VCC  VCC + 0.3 V
“H” level SCK1, EC, PWCK,
input voltage PWC, SCK2, UCK2,
UI2, ADST
With SMB
VIHSMB  VSS + 1.4  VSS + 5.5 V input buffer
selected*
SCL, SDA
With I2C
VIHI2C  0.7 VCC  VSS + 5.5 V input buffer
selected*
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VIL  VSS − 0.3  0.3 VCC V
P40 to P47, P60 to P64,
SI1, SI2
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
VILS UI1, INT10 to INT13,  VSS − 0.3  0.2 VCC V
“L” level SCK1, EC, PWCK, PWC,
input voltage SCK2, UCK2, UI2, ADST
With SMB
VILSMB  VSS − 0.3  VSS + 0.6 V input buffer
selected*
SCL, SDA
With I2C
VILI2C  VSS − 0.3  0.3 VCC V input buffer
selected*
Open drain VD1 P50 to P57 VCC + 0.3 V
output
 VSS − 0.3 
applied VD2 P42, P43 VSS + 5.5 V
voltage
P00 to P07, P10 to P17,
“H” level P20 to P24, P30 to P37, IOH = −2.0 mA
output VOH P40, P41, P44 to P47 2.4   V
voltage
P25 to P27 IOH = −3.0 mA
P00 to P07, P10 to P17,
“L” level
P20 to P27, P30 to P37,
output VOL IOL = 4.0 mA   0.4 V
P40 to P47, P50 to P57,
voltage
RST
(Continued)

38
 MB89530A Series

(Continued) (AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)

Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
Input leak
P00 to P07, P10 to P17,
current With no pull-up
P20 to P27, P30 to P37, 0.0 V < VI <
(Hi-Z ILI −5  +5 µA resistance
P40 to P47, P50 to P57, VCC
output leak specified
P60 to P64
current)
Open drain
0.0 V < VI < VSS
output leak ILIOD P42, P43   +5 µA
+ 5.5 V
current
P00 to P07, P10 to P17, With pull-up
Pull-up P20 to P27, P30 to P37, resistance speci-
RPULL VI = 0.0 V 25 70 100 kΩ
resistance P40, P41, P44 to P47, fied. The RST sig-
P60 to P64, RST nal is excluded.
FCH = 10.0 MHz
ICC1  6 10 mA
tinst = 0.4 µs
FCH = 10.0 MHz
ICC2  1.5 3 mA
tinst = 6.4 µs
FCH = 10.0 MHz
ICCS1  2 4 mA Sleep mode
tinst = 0.4 µs
FCH = 10.0 MHz
ICCS2  1 2 mA Sleep mode
tinst = 6.4 µs
Sub modes
 1 3 mA MB89P538/
FCL = PV530
32.768 kHz Sub modes
ICCL VCC VCC = 3.0 V MB89535A/7A/
Supply TA = +25 °C  20 50 µA 8A
current MB89537AC/
538AC
FCL =
32.768 kHz Sub, sleep
ICCLS  15 30 µA
VCC = 3.0 V modes
TA = +25 °C
FCL =
32.768 kHz Watch mode,
ICCT  5 15 µA
VCC = 3.0 V main stop
TA = +25 °C
ICCH TA = +25 °C  1 5 µA Sub, stop modes
A/D conversion
IA FCH = 10.0 MHz  1 3 mA
AVCC running
IAH TA = +25 °C  1 5 µA A/D stopped
Input
Except VCC, VSS, AVCC,
capaci- CIN f = 1 MHz  5 15 pF
tance AVSS

* : The MB89PV530/P538/537AC/538AC have a built-in I2C function, and a choice of input buffers by software setting.
MB89535A/537A/538A have no built-in I2C functions, and therefore this standard does not apply.
39
 MB89530A Series

4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Condition Unit Remarks
Min Max
RST “L” pulse width tZLZH  48 tHCYL  ns
Notes: • tHCYL is the main clock oscillator period.
• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may
cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the
external reset pin (RST).

tZLZH

RST 0.2 VCC 0.2 VCC

(2) Power-on Reset

(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Condition Unit Remarks
Min Max
Power on time tR  0.5 50 ms
For repeated
Power shutoff time tOFF  1  ms
operation
Note : Be sure that the power supply will come on within the selected oscillator stabilization period. Also, when
varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually.

tR tOFF

2.2 V
VCC
0.2 V 0.2 V 0.2 V

40
 MB89530A Series

(3) Clock Timing Standards

(AVss = Vss = 0 V, TA = −40 °C to +85 °C)

Condi- Value
Parameter Symbol Pin name tion Unit Remarks
Min Typ Max
FCH X0, X1 1  12.5 MHz Main clock
Clock frequency
FCL X0A, X1A  32.768  kHz Sub clock
tHCYL X0, X1 80  1000 ns Main clock
Clock cycle time
tLCYL X0A, X1A  30.5  µs Sub clock
PWH 
X0 20   ns External clock
PWL
Input clock pulse width
PWHH
X0A  15.2  µs External clock
PWLL
Input clock rise, fall tCR
X0   10 ns External clock
time tCF

• X0, X1 timing and application conditions

tHCYL

PWH PWL
tCR tCF
0.8 VCC 0.8 VCC
X0

0.2 VCC 0.2 VCC 0.2 VCC

• Clock application conditions

Using a crystal oscillator

or Using an external clock
ceramic oscillator signal

X0 X1 X0 X1

Open
FCH
FCH
C1 C2

41
 MB89530A Series

• X0A, X1A timing and application conditions

tLCYL

PWLH PWLL
tCR tCF
0.8 VCC 0.8 VCC
X0A

0.2 VCC 0.2 VCC 0.2 VCC

• Clock application conditions

Using a crystal oscillator

Using an external clock
or
signal
ceramic oscillator

X0A X1A X0A X1A

Open
FCL
FCL
C1 C2

(4) Instruction Cycle

(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter Symbol Rated value Unit Remarks
Operating at FCH = 12.5 MHz
Instruction cycle 4/FCH, 8/FCH, 16/FCH, 64/FCH µs (4/FCH)
(minimum instruction tinst tinst = 0.32 µs
execution time) Operating at FCL = 32.768 kHz
2/FCL µs
tinst = 61.036 µs

42
 MB89530A Series

(5) Serial I/O Timing

(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Sym- Value
Parameter Pin name Condition Unit Remarks
bol Min Max
Serial clock cycle time tSCYC SCK, UCK 2 tinst  µs
SCK↓→SO tSLOV SCK, SO, UCK, UO Internal −200 +200 ns
clock
Valid SI→SCK↑ tIVSH SI, SCK, UI, UCK operation 200  ns
SCK↑→valid SI hold time tSHIX SCK, SI, UCK, UI 200  ns
Serial clock “H” pulse width tSHSL 1 tinst  µs
SCK, UCK
Serial clock “L” pulse width tSLSH 1 tinst  µs
External
SCK↓→SO time tSLOV SCK, SO, UCK, UO clock 0 200 ns
operation
Valid SI→SCK↑ tIVSH SI, SCK, UI, UCK 200  ns
SCK↑→ valid SI hold time tSHIX SCK, SI, UCK, UI 200  ns
Note : For tinst see “ (4) Instruction Cycle”.

Internal shift clock mode

tSCYC
SCK
UCK 2.4 V
0.8 V 0.8 V
tSLOV

SO 2.4 V
UO 0.8 V

tIVSH tSHIX

SI 0.8 VCC 0.8 VCC

UI 0.2 VCC 0.2 VCC

External shift clock mode

tSLSH tSHSL
SCK
UCK 0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV

SO 2.4 V
UO 0.8 V

tIVSH tSHIX

SI 0.8 VCC 0.8 VCC

UI 0.2 VCC 0.2 VCC

43
 MB89530A Series

(6) Peripheral Input Timing

(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Max
Peripheral input “H” level
tILIH1 INT10 to INT13,  2 tinst  µs
pulse width 1
INT20 to INT27,
Peripheral input “L” level
tIHIL1 EC, PWC, PWCK  2 tinst  µs
pulse width 1
Peripheral input “H” level
tILIH2  28 tinst  µs
pulse width 2
ADST
Peripheral input “L” level
tIHIL2  28 tinst  µs
pulse width 2
Note : For tinst see “ (4) Instruction Cycle”.

tIHIL1 tILIH1
EC, INT, PWC, PWCK

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tIHIL2 tILIH2
ADST

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

44
 MB89530A Series

(7) I2C Timing

(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Pin Value
Parameter Symbol Condition Unit Remarks
name Min Max
SCL 1 / 4 tinst × 1 / 4 tinst × Master
Start condition output tSTA  ns
SDA m × n − 20 m × n + 20 only
SCL 1 / 4 tinst × 1 / 4 tinst × Master
Stop condition output tSTO  ns
SDA (m × n + 8) − 20 (m × n + 8) + 20 only
SCL
Start condition detection tSTA  1 / 4 tinst × 6 + 40  ns
SDA
SCL
Stop condition detection tSTO  1 / 4 tinst × 6 + 40  ns
SDA
SCL 1 / 4 tinst × 1 / 4 tinst × Master
Restart condition output tSTASU  ns
SDA (m × n + 8) − 20 (m × n + 8) + 20 only
SCL
Restart condition detection tSTASU  1 / 4 tinst × 4 + 40  ns
SDA
1 / 4 tinst × 1 / 4 tinst × Master
SCL output “L” width tLOW SCL  ns
m × n − 20 m × n + 20 only
1 / 4 tinst × 1 / 4 tinst × Master
SCL output “H” width tHIGH SCL  ns
(m × n + 8) − 20 (m × n + 8) + 20 only
SDA output delay time tDO SDA  1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20 ns
Setup after SDA output
tDOSU SDA  1 / 4 tinst × 4 − 20  ns
interrupt interval
SCL input “L” width tLOW SCL  1 / 4 tinst × 6 + 40  ns
SCL input “H” width tHIGH SCL  1 / 4 tinst × 2 + 40  ns
SDA input setup tSU SDA  40  ns
SDA input hold tHO SDA  0  ns

Notes : • For tinst see “ (4) Instruction Cycle”.

• The value “m” in the above table is the value from the shift clock frequency setting bits (CS4-
CS3) in the clock control register “ICCR”. For details, refer to the register description in the hardware
manual.
• The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2-CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSU appears when the interrupt period is longer than the SCL “L” width.
• The rated values for SDA and SCL assume a start up time of 0 ns.

45
 MB89530A Series

• I2C interface [Data sending (master/slave) ]

tDO tDO tSU tSU tDOSU

SDA
ACK
tSTASU tSTA tLOW tHO

SCL 1 9

• I2C interface [Data receiving (master/slave) ]

tSU tHO tDO tDO tDOSU
SDA
ACK

tHIGH tLOW tSTO

SCL
6 7 8 9

46
 MB89530A Series

5. A/D Converter Electrical Characteristics

(1) MB89535A/537A/537AC/538A/538AC/P538/PV538
(VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
Resolution capability    10 bit
Total error   ±3.0 LSB

Linear error   ±2.5 LSB
Differential linear error   ±1.9 LSB
AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 AVCC = VCC
Zero transition voltage VOT AVR = AVCC mV
 LSB LSB LSB
Full scale transition AVR − 3.5 AVR − 1.5 AVR + 1.5
VFST mV
voltage LSB LSB LSB
Inter-channel variation   4.0 LSB
Conversion time   60 tinst  µs *
Sampling time  16 tinst  µs
Analog input current IAIN AN0 to    10 µA
Analog input voltage VAIN AN7 0  AVR V
Reference voltage  AVSS + 3.5  AVCC V
Reference voltage IR AVR A/D running  400  µA
supply current IRH A/D off   5 µA
* : Includes sampling time.
Note : For tinst see “ (4) Instruction Cycle”.

(2) MB89F538
(VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
Resolution capability    10 bit
Total error   ±5.0 LSB

Linear error   ±2.5 LSB
Differential linear error   ±1.9 LSB
AVSS − 1.5 AVSS + 0.5 AVSS + 4.5 AVCC = VCC
Zero transition voltage VOT AVR = AVCC mV
 LSB LSB LSB
Full scale transition AVR − 6.5 AVR − 1.5 AVR + 1.5
VFST mV
voltage LSB LSB LSB
Inter-channel variation   4.0 LSB
Conversion time   60 tinst  µs *
Sampling time  16 tinst  µs
Analog input current IAIN AN0 to    10 µA
Analog input voltage VAIN AN7 0  AVR V
Reference voltage  AVSS + 3.5  AVCC V
Reference voltage IR AVR A/D running  400  µA
supply current IRH A/D off   5 µA
* : Includes sampling time.
Note : For tinst see “ (4) Instruction Cycle”.
47
 MB89530A Series

(3) A/D Converter Terms and Definitions

• Resolution
The level of analog variation that can be distinguished by the A/D converter.
• Linear error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→“00
0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) , compared with
the actual conversion values obtained.
• Differential linear error (Unit : LSB)
The deviation from the theoretical input voltage required to produce a change of 1 LSB in output code.
• Total error (Unit : LSB)
The difference between theoretical conversion value and actual conversion value.
Theoretical input/output
characteristics Total error

3FF VFST 3FF

Actual conversion
3FE 3FE characteristics
3FD 1.5 LSB 3FD (1 LSB I N +
Digital output

Digital output

0.5 LSB)

004 004
VNT
003 003 Actual
VOT conversion
002 002 characteristics
1 LSB
Theoretical
001 001 characteristics
0.5 LSB
AVSS AVR AVSS AVR
Analog input Analog input

VFST − VOT VNT − {1 LSB × N + 0.5 LSB}

1 LSB = (V) Total error in digital output N =
1022 1 LSB

(Continued)

48
 MB89530A Series

(Continued)

Zero transition error Full-scale transition error

004 Actual Theoretical characteristics

conversion
characteristics 3FF Actual
conversion
003 characteristics
Digital output

Digital output
3FE

002
Actual VFST (actual
3FD measurement
conversion
value)
characteristics
001 Actual conversion
VOT (actual 3FC
characteristics
measurement value)
AVSS AVR
Analog input Analog input

Linear error Differential linear error

3FF Actual conversion

characteristics Theoretical characteristics
3FE N+1 Actual
(1 LSB × N + VOT) conversion
3FD characteristics V (N + 1) T
Digital output

Digital output

VFST N
(actual
VNT measure-
004
ment
value)
003 Actual conversion N−1
VNT
characteristics
002
Theoretical Actual conversion
001 characteristics N−2
characteristics
VOT (actual measurement value)
AVSS AVR AVSS AVR
Analog input Analog input

Analog input linear = VNT − {1 LSB × N + VOT} Differential linear = V (N + 1) T − VNT −1

error in digital output N 1 LSB error in digital output N 1 LSB

49
 MB89530A Series

(4) Precautionary Information

• Input Impedance of Analog Input Pins
The A/D converter of MB89530A has a sample & hold circuit as shown below, which uses a sample-and-hold
capacitor to obtain the voltage at the analog input pin for 8 instruction cycles following the start of A/D conversion.
For this reason if the external circuits providing the analog input signal have high output impedance, the analog
input voltage may not stabilize within the analog input sampling time. It is therefore recommended that the output
impedance of external circuits be reduced to 10 kΩ or less.
• MB89535A/537A/537AC/538A/538AC Analog Input Equivalent Circuit
Sample-and-hold circuit
C = 45 pF
Analog input pin
Compara-
tor
R = 2.2 kΩ
If analog input impedance is Closes 8 instruction cycles
10 kΩ or more, the use of a after the start of A/D conversion
capacitor of approximately
0.1 µF is recommended. Analog channel selector

• MB89P538 and MB89PV530 Analog Input Equivalent Circuit

Sample-and-hold circuit
C = 64 pF
Analog input pin
Compara-
tor
R = 3 kΩ
If analog input impedance is Closes 8 instruction cycles
10 kΩ or more, the use of a after the start of A/D conversion
capacitor of approximately
0.1 µF is recommended. Analog channel selector

• MB89F538 Analog Input Equivalent Circuit

Sample-and-hold circuit
C = 30 pF
Analog input pin Compara-
tor
R = 3.2 kΩ
If analog input impedance is Closes 8 instruction cycles
10 kΩ or more, the use of a after the start of A/D conversion
capacitor of approximately
0.1 µF is recommended. Analog channel selector

• About error
The smaller the absolute value |AVR - AVss| is, the greater the relative error becomes.

50
 MB89530A Series

■ EXAMPLE CHARACTERISTICS (MB89538A)

(1) Power Supply Current (External Clock)
ICC1 vs. VCC ICCS1 vs. VCC

14 5
(TA = + 25 ˚C) 12.5 MHz (TA = + 25 ˚C)
12 12.5 MHz
10 MHz
4
10 10 MHz

ICCS1 (mA)
ICC1 (mA)

8 8 MHz 3
8 MHz

6 2
5 MHz 5 MHz
4
2 MHz 1
2 2 MHz
1 MHz 1 MHz
0 0
2 3 4 5 6 7 2 3 4 5 6 7
VCC (V) VCC (V)

(2) “H” Level Input Voltage/ “L” Level Input Voltage (CMOS Input)

VIN vs. VCC

4
(TA = + 25 ˚C)
3
VIN (V)

0
2 3 4 5 6 7
VCC (V)

(3) “H” Level Input Voltage / ”L” Level Input Voltage (Hysteresis Input)

VIN vs. VCC

4
(TA = + 25 ˚C) VIH

3
VIN (V)

VIL
2

0
2 3 4 5 6 7
VCC (V)

51
 MB89530A Series

(4) Pull-up Resistor Value

RPULL vs. VCC
1000
(TA = + 25 ˚C)

Pull-up (kΩ)
100

10
0 1 2 3 4 5 6
VCC (V)

(5) ”H” Level Output Voltage

VCC - VOH1 vs. IOH VCC - VOH2 vs. IOH

1.6 0.9
(TA = + 25 ˚C, VCC = 5 V) (TA = + 25 ˚C, VCC = 5 V)
1.4 0.8

1.2 0.7

0.6
VCC - VOH1 (V)

VCC - VOH2 (V)

1.0
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2 0.1

0.0 0.0
0 2 4 6 8 10 0 2 4 6 8 10
IOH (mA) IOH (mA)

(6) ”L” Level Output Voltage

VCC - VOL vs. IOL

0.9
(TA = + 25 ˚C, VCC = 5 V)
0.8

0.7

0.6
VCC - VOL (V)

0.5

0.4

0.3

0.2

0.1

0.0
0 2 4 6 8 10
IOL (mA)

52
 MB89530A Series

(7) AD Converter Characteristic Example

Linearity Error
3.0
2.5
2.0 (VCC = AVR = 5 V, Fc = 10 MHz)
1.5
1.0
Error (LSB)

0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0 128 256 384 512 640 768 896 1024

Conversion characteristic

Differential linearity error

2.5

2.0
1.5

1.0
Error (LSB)

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5
0 128 256 384 512 640 768 896 1024

Conversion characteristic

Total Error
4.0

3.0
(VCC = AVR = 5 V, Fc = 10 MHz)
2.0
Error (LSB)

1.0

0.0

-1.0

-2.0

-3.0

-4.0
0 128 256 384 512 640 768 896 1024

Conversion characteristic

53
 MB89530A Series

■ MASK OPTIONS
MB89535A
MB89537A MB89PV530-101
MB89F538-101 MB89P538-101
Part number MB89537AC
MB89F538-201 MB89P538-201 MB89PV530-201
No MB89538A
MB89538AC
Method of Specify at time Setting Setting Setting
specification of mask order not possible not possible not possible
Main clock
Select oscillator
stabilization wait period
(FCH* = 10 MHz)
approx.214/FCH* Selection 218/FCH* 218/FCH* 218/FCH*
1
(approx.1.6 ms) available (approx. 26.2 ms) (approx. 26.2 ms) (approx. 26.2 ms)
approx.217/FCH*
(approx.13.1 ms)
approx.218/FCH*
(approx.26.2 ms)
Clock mode selection
Selection • 101 : 1-system clock mode
2 • 2-system clock mode
available • 201 : 2-system clock mode
• 1-system clock mode
* : FCH: Main clock frequency

54
 MB89530A Series

■ ORDERING INFORMATION
Part number Package Remarks
MB89535AP
MB89537AP
MB89537ACP
MB89538AP
MB89535AP, MB89537AP and MB89538AP
MB89538ACP DIP-64P-M01
do not have I2C functions.
MB89P538P-101
MB89P538P-201
MB89F538P-101
MB89F538P-201
MB89535APF
MB89537APF
MB89537ACPF
MB89538APF
MB89535APF, MB89537APF and
MB89538ACPF FPT-64P-M06
MB89538APF do not have I2C functions.
MB89P538PF-101
MB89P538PF-201
MB89F538PF-101
MB89F538PF-201
MB89535APFM
MB89537APFM
MB89537ACPFM
MB89538APFM
MB89535APFM, MB89537APFM and
MB89538ACPFM FPT-64P-M09
MB89538APFM do not have I2C functions.
MB89P538PFM-101
MB89P538PFM-201
MB89F538PFM-101
MB89F538PFM-201
MB89535APFV
MB89537APFV
MB89535APFV, MB89537APFV and
MB89537ACPFV FPT-64P-M03
MB89538APFV do not have I2C functions.
MB89538APFV
MB89538ACPFV
MB89PV530C-101
MDP-64C-P02
MB89PV530C-201
MB89PV530CF-101
MQP-64C-P01
MB89PV530CF-201

55
 MB89530A Series

■ PACKAGE DIMENSIONS
64-pin plastic SH-DIP
Note : Pins width and pins thickness include plating thickness.
(DIP-64P-M01)
+0.22 +.009
58.00 –0.55 2.283 –.022

INDEX-1

17.00±0.25
(.669±.010)
INDEX-2

+0.70
4.95 –0.20
+.028
.195 –.008
+0.50
0.70 –0.19
+.020
.028 –.007

+0.20
0.27±0.10
3.30 –0.30 (.011±.004) 19.05(.750)
+.008 +0.40 +0.50
.130 –.012 1.378 –0.20 1.778(.0700) 0.47±0.10 1.00 –0
+.016 0.25(.010) M
+.020
0~15°
.0543 –.008
(.019±.004) .039 –.0

C 2001 FUJITSU LIMITED D64001S-c-4-5

Dimensions in mm (inches).
Note: The values in parentheses are reference values

(Continued)

56
 MB89530A Series

Note 1)* : These dimensions do not include resin protrusion.

64-pin, Plastic LQFP
Note 2)Pins width and pins thickness include plating thickness.
(FPT-64P-M03) Note 3)Pins width do not include tie bar cutting remainder.

12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ 0.145±0.055
(.006±.002)
48 33

49 32

Details of "A" part

0.08(.003) +0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004

INDEX
0.10±0.10
0˚~8˚ (.004±.004)
64 17 (Stand off)

"A"

0.50±0.20 0.25(.010)
LEAD No. 1 16 (.020±.008)
0.60±0.15
0.50(.020) 0.20±0.05
0.08(.003) M (.024±.006)
(.008±.002)

C 2003 FUJITSU LIMITED F64009S-c-5-8

Dimensions in mm (inches).
Note: The values in parentheses are reference values

(Continued)

57
 MB89530A Series

Note 1)* : These dimensions do not include resin protrusion.

64-pin, Plastic QFP
Note 2)Pins width and pins thickness include plating thickness.
(FPT-64P-M06) Note 3)Pins width do not include tie bar cutting remainder.

24.70±0.40(.972±.016)

* 20.00±0.20(.787±.008) 0.17±0.06
(.007±.002)
51 33

52 32

18.70±0.40
(.736±.016)
Details of "A" part
*14.00±0.20
(.551±.008) +0.35
3.00 –0.20
INDEX +.014 (Mounting height)
.118 –.008

64 20

0~8˚
1 19

1.00(.039) 0.42±0.08 +0.15

0.20(.008) M
0.25 –0.20
(.017±.003)
1.20±0.20 +.006
.010 –.008
(.047±.008) (Stand off)

"A"
0.10(.004)

C 2003 FUJITSU LIMITED F64013S-c-5-5

Dimensions in mm (inches).
Note: The values in parentheses are reference values

(Continued)

58
 MB89530A Series

Note 1)* : These dimensions do not include resin protrusion.

64-pin, Plastic QFP
Note 2)Pins width and pins thickness include plating thickness.
(FPT-64P-M09) Note 3)Pins width do not include tie bar cutting remainder.

14.00±0.20(.551±.008)SQ

* 12.00±0.10(.472±.004)SQ 0.145±0.055
(.0057±.0022)
48 33

49 32

0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004

0.25(.010)
INDEX
0~8˚
64 17

0.50±0.20 0.10±0.10
"A" (.020±.008) (.004±.004)
1 16 (Stand off)
0.60±0.15
0.65(.026) (.024±.006)
0.32±0.05
0.13(.005) M
(.013±.002)

C 2003 FUJITSU LIMITED F64018S-c-3-5

Dimensions in mm (inches).
Note: The values in parentheses are reference values

(Continued)

59
 MB89530A Series

64-pin, Ceramic MDIP

(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)

15.24(.600) 18.75±0.30 19.05±0.30

TYP (.738±.012) (.750±.012)

INDEX AREA 2.54±0.25 0.25±0.05

(.100±.010) (.010±.002)
33.02(1.300)REF

1.27±0.25
10.16(.400)MAX (.050±.010)

+0.13
1.778±0.25 0.46 –0.08 0.90±0.13 3.43±0.38
(.070±.010) +.005
(.035±.005) (.135±.015)
.018 –.003
55.12(2.170)REF

C 1994 FUJITSU LIMITED M64002SC-1-4

Dimensions in mm (inches).
Note: The values in parentheses are reference values

(Continued)

60
 MB89530A Series

(Continued)
64-pin, Ceramic MQFP
(MQP-64C-P01)

18.70(.736)TYP

16.30±0.33 12.00(.472)TYP
(.642±.013)
INDEX AREA 15.58±0.20 +0.40
1.00±0.25
(.613±.008) 1.20 –0.20 (.039±.010)
+.016 1.00±0.25
.047 –.008
(.039±.010)
1.27±0.13
(.050±.005)

22.30±0.33 12.02(.473) 18.12±0.20

(.878±.013) TYP (.713±.008) 18.00(.709)
10.16(.400) 14.22(.560) TYP
24.70(.972) 0.30(.012) TYP
TYP TYP TYP

0.40±0.10
(.016±.004) +0.40
1.27±0.13 0.30(.012)TYP 0.40±0.10 1.20 –0.20
+.016
(.050±.005) (.016±.004) .047 –.008
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP

10.82(.426)
0.15±0.05 MAX
0.50(.020)TYP (.006±.002)

C 1994 FUJITSU LIMITED M64004SC-1-3

Dimensions in mm (inches).
Note: The values in parentheses are reference values

61
MB89530A Series

FUJITSU LIMITED
All Rights Reserved.

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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patent right or copyright, or any other right of Fujitsu or any third
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intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
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from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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Foreign Exchange and Foreign Trade Law of Japan, the prior
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of those products from Japan.

F0303
 FUJITSU LIMITED Printed in Japan