Cadence Analog Flow

João Vaz

INTRODUCTION TO CADENCE
ANALOG DESIGN FLOW
(for AMS CMOS PDK)

Prof. João Vaz

version 1.2021

Wireless Circuits - Lx
Instituto de Telecomunicações

Instituto Superior Técnico

Universidade de Lisboa
 Cadence Analog Flow
Introduction João Vaz

• Analog Design Flow

schematic

virtuoso
layout

DRC
assura,
LVS QRC,
calibre
extraction
 Cadence Analog Flow
Introduction João Vaz

• Cadence design tools servers

At IST cadence tools reside on two servers

a) Alameda server DNS – fatima2.vps.tecnico.ulisboa.pt

b) Taguspark server DNS – fatima.vps.tecnico.ulisboa.pt

IST student can log to the respective server using its Fenix authentication.

The easiest way to connect is by using ssh.

The most efficient way to connect is by using vnc.

The servers can be accessed by any client inside or outside IST.

 Cadence Analog Flow
Introduction João Vaz

• First time configuration for C35 CMOS AMS technology PDK

Technology libraries kit are usually called pdk (*) or, in the AMS case, hit-kit.

1) Create a directory for using cadence and move inside it.

2) Run initialization script “source /opt/ic_tools/init/init-amsC35-410”.

3) Start command for C35 CMOS AMS technology is “ams_cds -tech c35b4 &”.

4) The main cadence interface window appears, Command Interpreter Window (CIW).

5) The technology exact version (C35B4C3) should be selected in an additional

window.

CIW

(*) Process Design Kit

 Cadence Analog Flow
Introduction João Vaz

• Regular cadence start for C35 CMOS AMS technology

1) Run initialization script “source /opt/ic_tools/init/init-amsC35-410”.

2) Start command for cadence with C35 CMOS AMS technology is “ams_cds &”.

3) The CIW appears.

4) For closing cadence, use CIW menu “File/Exit”.

Please note that before finishing a work session it is very important to close
cadence. Otherwise, one or more licenses will be locked. Also, depending on how
the user made login to the server, some files inside the libraries can became
locked and additional procedures must be done to unlock them.
 Cadence Analog Flow
Introduction João Vaz

• Library manager

Library manager is where libraries, cells and views can be created, open and
deleted. It can be started in the CIW “Tools” menu.
AMS PDK opens it automatically.

By default, PRIMLIB library, which has low frequency AMS PDK components,
appears. Also cadence analogLib, which has ideal generic components, is included.
If “show categories” is selected, a group organization of the cells is shown.
 Cadence Analog Flow
Introduction João Vaz

If additional libraries with RF components are needed (PRIMLIBRF and

SPIRALS_4M), or PADS (IOLIB_ANA_4M), on CIW menus chose
“hitkit”→”add/remove hitkit libraries”. A window appears where it is possible to
add available libraries from right to left column.

new added
libraries
↓
pads libs
rf components
spiral inductors
 Cadence Analog Flow
Introduction João Vaz

• Library creation
When starting a new project, a new library should be created. This is done in
Library Manager using menu “File/New/Library”. This library should be
associated with the technology version in use.

fill
library
name

For AMS C35 4-metals version

choose TECH_C35B4
 Cadence Analog Flow
Schematic João Vaz

• Cell and view creation

First select the library in the library manager. Then with menu “File/New/Cell
View” fill the form.
For each cell type cadence
automatically choses the right tool
fill to open it. Then an empty window
cell appears.
name

schematic window
fill cell
type
 Cadence Analog Flow
Schematic João Vaz

• Adding instances (components) to the schematic

First open the schematic window. Then using the menu “Create/Instance”, the
window Add Instance appears. Press “Browse”, and library manager appears.
Chose the instance library, cell and view that should be symbol type. Place the
element inside the schematic.

At the same time cadence gives the option to configure the element properties
before placing by opening element properties window.

Anyway the same properties can always be changed after placement. For that:
1) Select the component
2) Open menu “Edit/Properties/Object”, the properties window appears.

Components from Cadence or AMS libraries are read-only but can be used in
user libraries. User own cells with symbol views can be reused by the same user.
 Cadence Analog Flow
Simulation João Vaz

• Configuring a simulation
step 1
For a certain schematic cell, the simulation is started with the
menu “Launch/ADE GXL. Then, cadence asks if the user wants
to create or open an adexl view (step1). This adexl view stores
all simulation configuration details for the cell.
After pressing ok, a new window appears (step2), press ok. step 2
A new ADE window appears (step3)
Expand “Tests” by clicking “+” in ADE window. Add a test
and chose the corresponding schematic to simulate (step4).
step 3 step 4

ADE window can be used to

simulate different schematics
from the same library.

A certain test can have several simulations

types configured for its schematic.
Variable are also configured in ADE window.
 Cadence Analog Flow
Simulation João Vaz

• Example: 500MHz AMP_LF

A simple inverter stage amplifier will

be considered.
The schematic is made considering
that a hierarchical design will be
used. This means that one cell has
the amplifier with PDK components
and cadence pins.

It is possible to create a symbol from schematic window

with menu “create/cell view/from cellview”. amp_LF
schematic

During symbol creation a form appears

where the user can edit the pins sides
placement.

amp_LF
symbol

Note: amp_LF components from PRIMLIB

 Cadence Analog Flow
Simulation João Vaz

Another cell, the testbench, has the schematic with the necessary off-chip
components to perform the AMP_LF simulation. These components are usually
sources, grounds and passives, from analogLib, and the symbol of the circuit under
test.

input voltage
parameters for
AC and TRANS
analysis
amp_LF testbench

A hierarchical design is required to allow LVS and layout parasitic extraction

phases which are mandatory for post-layout simulations.

Following slides will show how to configure typical low frequency circuits
simulations, like DC, AC and transient.
 Cadence Analog Flow
Simulation João Vaz

General view of a configured ADE window

simulation type tab

outputs tab schematic tab simulation options button

schematic run
simulations simulation
button

ade tab

results tab

Global variables are valid for all tests, each test has local design variables.
For each test outputs from all simulations can be configured.
 Cadence Analog Flow
Simulation João Vaz

• AC simulation
The AC small-signal simulation configuration form is shown for a simple
frequency sweep (step1). Other sweep options are possible.
step 1
step 2
After running the simulation, on
ADE results tab, click with the
mouse right button (RMB) over
one of the results line. A menu
opens and chose “direct
Plot\Main form”, which opens
step2 form.

Fill the form and obtain graphic

results.
Depending on “function” and
“select” fields, the form asks for
selecting a “Net” or a “Terminal”.

If ”Add To Outputs” is selected,

results equations are added to
ADE output setup tabs.
Net: selection quantity is the node voltage.
Terminal: selection quantity is the current entering
the component terminal.
 Cadence Analog Flow
Simulation João Vaz

Graphical result for output voltage in dB20 which, because input source AC
magnitude is 1, is numerical equal to gain voltage in decibel.
 Cadence Analog Flow
Simulation João Vaz

• TRAN simulation
The time domain simulation (tran) configuration form is shown for a simple case
with stop time (step1). Other options are possible.

step 1 step 2

After running the

simulation, on ADE chose
pressing RMB “direct
Plot\Main form”, which
opens step2 from.

Fill the form and obtain

graphic results.
 Cadence Analog Flow
Simulation João Vaz

Graphical result for output voltage in the time domain.

 Cadence Analog Flow
Simulation João Vaz

• DC simulation
The DC simulation configuration form is shown for a simple case of obtaining
the Quiescent Point (step1). Other options are possible.

step 1
After running the simulation, on
ADE results tab, click with the RMB
over one of the results line. A menu
opens and chose “Annotate\DC node
voltages” or “Annotate\DC operating
point”.
Voltage and current DC values will
be plotted in the schematic.

If a variable sweep is selected,

graphics are also possible to plot.
 Cadence Analog Flow
Simulation João Vaz

Annotation result for “dc operating point” and “dc node voltages”.

Please note that annotation results can also be seen directly in the schematic
by opening menu with right-mouse button.
 Cadence Analog Flow
Simulation João Vaz

• Fabrication dispersion simulation

Cadence is able to simulate circuits taking into account dispersion effects. For
that it uses device models included in the PDK that are obtained from wafers
with limit acceptable tolerance parameters (corners).

The corners conditions are:

TM – Typical mean condition (typical wafers).
WP – Worst power condition (fast NMOS and fast PMOS).
WS – Worst speed condition (slow NMOS and slow PMOS).
WO – Worst one condition (fast NMOS and slow PMOS).
WZ – Worst zero condition (slow NMOS and fast PMOS).

Although theses cases apply to MOS devices, the passive devices measured
in the wafers have also models for the same situations.
The Monte Carlo (MC) simulation makes random variation of the model,
instead of limit cases. It can also mix random corner with random variations
around them.
 Cadence Analog Flow
Simulation João Vaz

• Corners simulation
The AC simulation will be used for corners analysis simulation. Corners
analysis assumes that each type of components (for example MOS) suffer from
equal fabrication dispersion by using non typical models.
Start creating a corners file by using CIW menu “hitkit/simulation utilities/corner
analysis”. A form opens (step1).
Chose the components types to consider

Temperature and supply voltage variation

can also be considered by including new
values

The number of corners plus a typical

simulation can be seen here

Fill file name with extension (.sdb)

Finally save the file and close the form.

Now a configured corners file is available.

step 1
 Cadence Analog Flow
Simulation João Vaz

On ADE, expand “Corners” by clicking “+”. Add a corner. The corners setup
window appears. Import the created .sdb file, and the window will look like step2
where one corner has all variations. Select the corner and expand it (step3) which
is better for results interpretation.

step 3
step 2

Press ”ok” and run the AC simulation. Please note that by default typical corner is
not selected on ADE corners list.

Corner analysis can be very time consuming, depending on corners number and
simulation complexity.
 Cadence Analog Flow
Simulation João Vaz

Graphical result for gain voltage in decibel. Typical curve in red with circle
symbols.
 Cadence Analog Flow
Simulation João Vaz

• Monte Carlo simulation

The AC simulation will be used for show Monte Carlo (MC) simulation. As can be
seen on step1 process, mismatch or both can be chosen.
On ADE “simulation type tab” chose “Monte Carlo sampling”. Click ”simulation
options button” and the a for appears (step1). Fill as shown and press “ok”.
On ADE window, click with the mouse right button over the test name. A menu
opens and chose “Model librarys”, which opens step2 form.

To perform MC simulation
change all sections from
*tm to *mc (step3).

After finishing MC
step 2
simulations change back
again *mc to *tm.

step 1 step 3
 Cadence Analog Flow
Simulation João Vaz

Graphical result for gain voltage in decibel from MC simulations.

 Cadence Analog Flow
Simulation João Vaz

• Example: 4GHz AMP_RF

A simple single stage amplifier will be

considered. The schematic is made
considering that a hierarchical design.

amp_RF
schematic

amp_RF testbench

Source and load use “psin” analogLib element.

Amp_RF has no input decoupling capacitor, so
testbench includes an ideal one to avoid input
source bias influence. amp_RF symbol

Note: amp_RF components from PRIMLIBRF

 Cadence Analog Flow
Simulation João Vaz

• S-parameters simulation
The s-parameter simulation configuration form is shown for a simple frequency
sweep (step1).
step 1
Ports must be selected by order

A sweep must be selected, in this step 2

case a frequency sweep

If noise is selected, ports must

be selected

After running the simulation,

chose “direct Plot\Main form”,
which opens step2 form.

Several functions can be plotted,

in different formats.
 Cadence Analog Flow
Simulation João Vaz

S-parameters and noise simulation example.

 Cadence Analog Flow
Simulation João Vaz

• Periodic steady-state (PSS) simulation

A one-tone input source Psav power sweep will be configured.
input psin source parameters
The “psin” input for PSS analysis
source default
properties must
me edited

The Psav variable must

be added by using RMB
over ”Design varibles”
and menu ”copy from
cellview”. Give an initial
value.

Give a frequency name

Fill the available power with a parameter
Fill the fundamental frequency value
 Cadence Analog Flow
Simulation João Vaz

The PSS simulation configuration form is shown for a

simple Psav sweep (step1).

Select one of the 2 simulators engines

psin source is automatically recognized

Input or press auto calculate

fundamental frequency value

Input number of harmonics

Select only if the circuit is autonomous

(oscillator case)

Configure the variable sweep

Note: Harmonics number is only used for results

presentation if shooting method is selected. step 1
 Cadence Analog Flow
Simulation João Vaz

The PSS simulation direct plot form is shown (step2). step 2

Power, voltage, current and relations
between them can be chosen

psin source is automatically recognized

Input or press auto calculate

fundamental frequency value

Input number of harmonics

x-axis variable

Select only if the circuit is autonomous

(oscillator case)

Configure the variable sweep

Note: Harmonics number is only used for results

presentation if shooting method is selected.
 Cadence Analog Flow
Simulation João Vaz

Details about PSS simulation direct plot form

For single quantity For two quantities ratio

In this case the non-sweep variable

must be chosen for the quantity

In this case the non-sweep variable

must be chosen for each quantity

For one quantity power must

be defined in a single place.

For two quantity power must

be defined in two places.

Note: For each case power can be defined by several ways.

In this example “port” was used.
 Cadence Analog Flow
Simulation João Vaz

Graphical result for output power and power gain in terms of Psav.
 Cadence Analog Flow
Simulation João Vaz

Graphical result for output voltage can be obtained.

For time domain For frequency domain

 Cadence Analog Flow
Layout João Vaz

• Building a layout
Layout main characteristics

• Each schematic component must match a layout component in terms of type and
dimensions.

• The components electrical connections in the schematic must be exactly

replicated in the layout.

• Pins names in schematic and layout must match (the names are case sensitive).

• The schematic and layout have only PDK components.

The layout can be designed in two way

Placing all components and editing its dimensions, making all connections and
adding the pins by hand. In this case Layout L tool can be used.

Making an automatic placement of components and pins, using wirelines to guide

the connections design. The components have already the schematic dimensions.
In this case Layout XL must be used. Same cell schematic is automatically opened.
 Cadence Analog Flow
Layout João Vaz

• Layout creation
step2
Create a layout cellview
in the same amp_RF cell
step1

step2 window appears

The layers window list all

type of available layers
defined in the technology
file.
Each layer has a name, a
purpose, a color and a
pattern. Selection and
visibility is possible to
activate or not.

Layout L empty window

 Cadence Analog Flow
Layout João Vaz

For using layout XL, on layout L menu “Launch”, chose “Layout XL”. This way
layout L window transforms into layout XL window.
To place the components and pins, on menu “Connectivity/Generate/All from
source…” and step1 form appears. Unselect PR boundary.

Click IO pins tab, and step2

form appears. If necessary, it
is possible to change pins
size or layers. Although this
can be made after placement,
for a better reading width and
height for each pin can be
increase to 10.

step 1 step 2
 Cadence Analog Flow
Layout João Vaz

After placement layout XL

windows appears like this.
The components and the pins
are randomly placed, and
some lines show the terminals
required connections.

Following steps
Move, rotate and mirror the
components to simplify the
connections to be made.
Place the necessary pads and
move each pin into each one.
Start making the metallic
connections (routing) using
metal layers and vias. Important
Connect the guard-ring to the It is mandatory during layout design to perform
adequate VDD/GND pads. frequently design rules check (DRC) to see if any
geometrical error is made.

Additionally, these 3 buttons can be selected and during layout

design some size warnings will appear.
 Cadence Analog Flow
Layout João Vaz

Several aspects
Layers have a name and a purpose. Drawing shapes using layers with drawing
purpose (drw) can be used for defining, for example, metals, poly, diffusion,
wells, etc. These drw layers are also called tooling layers because they define
the process materials fabrication steps. Other purposes layers are usually used
by the CAD to identity special regions, pins, components, etc.
The PDK library has already the layouts for all the components. The designer
task is essential to route the components pins between then and with the pads
that are the accesses to the outside.
This task is accomplished by placing metal layers and vias. Guard-rings must
also be connected to PG pads.
Sometimes it is necessary to place wells (p or n type) around components and
connect these wells to PG. These can be made using guard-rings or simple
multiple contacts.
Any geometric shape can be placed using menu “Create/Shape”. Path can also
be used to make a more efficient routing using menu “Create/Wiring”.
Vias and all types of contacts can be placed using menu “Create/Vias”.
Many menus have shortcut info close to some of the items.
 Cadence Analog Flow
Layout João Vaz

• LNA layout

A final layout is
shown on the right
figure.
Although there are
many good design
practices for
obtaining a good
layout, each designer
has its own style.
This layout is a
simple one, only for
demonstration
purposes.
 Cadence Analog Flow
Layout João Vaz

• Cpolyrf details
All components have accesses in M1.
Because passive RF components have
individual GR with M1, the route to inner
connections should take that into
account. The foundry allows to use only 3
sides GR to simplify the routing.

The image shows a Cpolyrf capacitor

where bottom GR side was unselected,
allowing a direct M1 route to bottom plate.

The route to top M1 plate is made with M4, and a stack of vias 1,2 and 3 is used to
connect top plate.

Because Cpolyrf has a n-well below, its GR should be connected to VDD.

 Cadence Analog Flow
Layout João Vaz

• Rpolyrf details

The image shows a Rpolyrf resistance where all GR sides

are selected.

The route to Rpolyrf terminals is made with M2 and via 1.

This way M1 GR is isolated from M2 routing.

Because Rpolyrf has a n-well below, its GR should be

connected to VDD.
 Cadence Analog Flow
Layout João Vaz

• Nmosrf details

Active RF components have individual GR with M1.

Although the foundry allows to use only 3 sides
GR to simplify the routing, in the transistor case it
is better to maintain a 4 sides GR.

The image shows a nmosrf transistor where

bottom/top sides GR were selected, left/right sides
were unselected. This way space is created to
place the vias and contacts to gate and drain
terminals. Finally, new left/right GR were manually
added to complete the 4 sides GR.

Because this nmos has grounded source, the body and source are connected to
GND using M1.
The drain side is routed from M4 with stacked vias 1,2,3 to connect the M1 drain
terminal region.
The gate side is routed from M4 with stacked vias 1,2,3 and poly1 contact, to
connect the poly1 gate terminal region.
 Cadence Analog Flow
DRC João Vaz

• Design rule check (DRC) with Assura

step 1
DRC can be called with layout window menu
“Assura/Run DRC”.
The following form opens (step1).
Fill “grid” and “no_coverage” options

A successful design will present the following

results (step2).
Part of the results are INFO type, which are no
errors. The other error that are located inside
PDK components should be disregarded.

step 2

Selecting each error line with the mouse, and using the form arrows, a zoom of the
error location is shown.
 Cadence Analog Flow
LVS João Vaz

• Layout versus schematic (LVS) with Assura

With AMS technology to perform LVS labels must be

included in the layout. The labels, which in reality are
“pins”, are different from layout XL pins but have the
same name.

For placing the labels use layout window menu

“Create/Label” (step1). The figure example is for label
“GND”. The label layer must be of name “PIN”, and the
step 1
purpose is the metal layer the label connects, in this
case the pad top metal 4. A height of 10 improves label
visibility.
After placing all labels, call LVS using menu
“Assura/Run DRC”.
The step 2 form appears, press “OK”.

Because both DRC and LVS create a large quantity

of files, it is important to fill a “run directory” on
respective forms. Otherwise, the working
directory will become full of files.

step 2
 Cadence Analog Flow
LVS João Vaz

An LVS successful result will present a form like this, which means that layout
represents the same circuit as schematic, i.e., they match.

An unsuccessful LVS will present an errors list that the designer should solve.
The typical errors are mismatches in the electrical connections or in the
components parameters values.
 Cadence Analog Flow
QRC João Vaz

• Extraction with Assura (QRC)

QRC can be called with layout window menu “Assura/Run Quantus QRC”. The
following form opens (step1).

Fill “View” with

av_extracted_C

Choose “Extraction”
tab and form opens
(step2). Select C only,
and “Ref Node”
with GND.

Start QRC extraction

by pressing “OK”.

step 1 step 2

This slide example was done for C extraction. For RC extraction fill “View” with
av_extracted_RC” and choose “RC” extraction type.
 Cadence Analog Flow
QRC João Vaz

After a successful extraction QRC form open (step1).

step 1 step 2

Please note that QRC cannot run without a successful previous LVS.

If an RC extraction was also made, the cell now has both extracted views (step2).
Extracted views are a kind of layout with the extracted netlist included. For the C
case it includes parasitic capacitors, for the RC case it includes parasitic
capacitors and resistances.
 Cadence Analog Flow
Simulation João Vaz

To simulate the circuit with parasitic capacitances included, “av_extracted_C” view

should be found by the simulator before the “schematic” view. For that, on the
testbench schematic ADE window, with the mouse right bouton on top of the
configured test, select “Environment” item. The following window appears.
Fill the name of the view to use
before the schematic view.
Like this, next simulation will
include the C parasitics influence
that are included on av_extracted
view.

To simulated again without

parasitics influence, and to avoid
deleting the av_extracted_C, you
can change it, for example, to
Xav_extracted_C.
Because this view name does not exist, the simulator ignores it and uses
schematic view again.