UVM RAL Training

Prerequisites:

Before starting this course, students should have:

1. Basic UVM Knowledge (Testbench architecture, components, sequences).

2. SystemVerilog Basics (Classes, inheritance, polymorphism).

3. Functional Coverage Basics (Functional coverage, covergroups).

4. Simulation Tools (QuestaSim).

5. Text editor – Gvim/vim

6. Scripting language – Python (NOT Mandatory)

15-Day UVM RAL Training Plan:

Day 1: Introduction to UVM RAL

• Concepts Covered:

o What is UVM RAL and its importance in verification?

o UVM RAL Architecture and Benefits.

o Components of a Register Model: Registers, Fields, Blocks, and Memory.

o Benefits of abstraction and automation in verification.

• Exercise:

o Create a simple Register Block with one register, define its field, and add reset
values.

Day 2: Core UVM RAL Classes

• Concepts Covered:

o uvm_reg: The base class for registers.

o uvm_reg_field: Defines fields within a register.

o uvm_reg_block: Represents a block of registers.

o uvm_mem: Defines memory for UVM RAL.

o The relationship between these classes.

• Exercise:

o Define a uvm_reg_block with multiple registers and fields (RO, RW, WO attributes).
Day 3: Defining Registers and Fields

• Concepts Covered:

o Register Attributes: Read/Write access (RO, RW, WO).

o Field Attributes: Reset values, bit masks, width, and access control.

o Using reset() to initialize registers.

• Exercise:

o Create registers with fields of different types (e.g., control, status, and data
registers). Set reset values and define access types.

Day 4: Register Blocks and Address Mapping

• Concepts Covered:

o Creating Register Blocks (uvm_reg_block).

o Assigning physical address space to registers.

o Address map for multiple registers.

• Exercise:

o Define a block with multiple registers and map addresses to them using
address_map.

Day 5: Integrating RAL Model into Testbench

• Concepts Covered:

o Configuring the RAL model in a UVM testbench.

o Register model initialization and configuration.

o Integration of RAL model into the UVM environment (uvm_test).

• Exercise:

o Integrate a simple register block into a UVM testbench. Initialize registers and
configure reset behavior.

Day 6: Basic Register Operations (Read/Write)

• Concepts Covered:

o Basic RAL Methods: read(), write(), mirror(), update().

o Writing and reading register fields.

• Exercise:

o Perform basic read and write operations on registers. Validate the behavior of read
and write methods.

Day 7: Adapters and Predictors

• Concepts Covered:

o Adapters: uvm_reg_adapter for mapping register accesses between the testbench

o Predictors: uvm_reg_predictor for predicting register values and automating

o Adapter integration in UVM RAL.

• Exercise:

o Create a custom adapter and integrate it into a simple testbench. Verify correct
transactions.

Day 8: Connecting the Register Model to DUT

• Concepts Covered:

o Adapter integration for DUT transactions.

o Synchronizing register model with the DUT through adapter and predictor.

o Validating register accesses between testbench and DUT.

• Exercise:

o Connect the register model to the DUT via an adapter. Perform a simple register
read/write operation with the DUT.

Day 9: Advanced Register Operations

• Concepts Covered:

o Advanced register access methods: Blocking vs. non-blocking access.

o Using predict() to predict register values based on expected behavior.

o mirror() and update() for synchronizing DUT and register models.

• Exercise:

o Implement advanced register access methods and validate them with blocking/non-
blocking operations.
Day 10: Register Sequences

• Concepts Covered:

o Writing uvm_reg_sequence for register access operations.

o Using uvm_sequence to automate register accesses in tests.

o Register-level test sequences for verification.

• Exercise:

o Create a sequence to test multiple register operations (e.g., read-modify-write).

Day 11: Register Callbacks

• Concepts Covered:

o Using uvm_reg_cbs for implementing pre- and post-register access callbacks.

o Handling error injection, logging, and verification with callbacks.

• Exercise:

o Implement callbacks for error injection during register access and logging register
read/write activities.

Day 12: Debugging Register Access

• Concepts Covered:

o Debugging techniques for adapters, predictors, and register sequences.

o Using UVM logging functions and waveform viewers for debugging.

o Identifying issues in register reads/writes and fixing them.

• Exercise:

o Debug a faulty register access scenario using logging and waveform viewers.

Day 13: Register Coverage

• Concepts Covered:

o Functional coverage for registers and fields.

o Using covergroup, coverpoint, and bins for register-level coverage.

o Register coverage models to verify all possible register accesses.

• Exercise:
 o Create and analyze register coverage for a register block.

Day 14: Memory Verification

• Concepts Covered:

o Memory verification using the uvm_mem class.

o Performing memory read/write operations in a UVM RAL testbench.

o Validating memory access patterns and verifying memory integrity.

• Exercise:

o Define a memory model with registers, perform memory read/write operations, and
validate memory access.

Day 15: Final Project and Review

• Concepts Covered:

o Integrating all learned concepts in a complete UVM RAL testbench.

o Review of key UVM RAL concepts: Adapters, sequences, callbacks, debugging, and
coverage.

o Q&A and final discussion on the application of UVM RAL in real-world verification.

• Exercise:

o Implement a complete RAL-based verification project using registers, sequences,

Generating RAL Models using Python Script (Additional concepts – if time permits)

• Using Python Scripts to Generate RAL Models:

o Python scripting to automate the generation of UVM RAL model components.

o Scripts to define registers, blocks, and memory models.

o Creating configurations for address mapping and register field attributes using
Python.