Department of Computer Science

Faculty of Computing
Abubakar Tafawa Balewa University, Bauchi
CS 313 Introduction to Computer Systems (2 Units) – Prerequisite CS 223
Computer structure and machine language memory control processing and I/O Units; register’s
principle, machine instruction types and their format; character representation; programme
control; pitch execute cycle turning; I/O operations, assembly language mnemonic operations;
symbolic addresses, assembler concepts and instruction format; data-word definition; literals,
addressing techniques; macros; file I/O; assembler segmentation and linkage; assembler
construction; interpretative routines.

Introduction
Introduction to computer systems offers a foundational understanding of the fundamental
principles that control the operation of modern computer systems. In this course, we will explore
the main layers of hardware and software, study how they interact to execute instructions and
process information. From the concepts of digital logic and microprocessor architecture to the
organization of memory and the role of the operating systems. Thus, this study will furnish
students with an overview of the inner workings of computers. At the end of this course, student
will gain the understanding of the complexities involved in designing, building, and utilizing
computer systems effectively.
COMPUTER STRUCTURE
Computer Architecture in general covers three aspects of computer design namely: Computer
Hardware, Instruction set Architecture and Computer Organization. Computer hardware consists
of electronic circuits, displays, magnetic and optical storage media and communication facilities.
Instruction set Architecture is programmer visible machine interface such as instruction set,
registers, memory organization and exception handling. Two main approaches are mainly CISC
(Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) Computer
Organization includes the high level aspects of a design, such as memory system, the bus
structure and the design of the internal CPU.
Computer Architecture
In computer engineering, computer architecture is a set of rules and methods that describe the
functionality, organization, and implementation of computer systems.

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Functional unit
 A computer consists of five (5) functionally independent main parts input, memory,
arithmetic logic unit (ALU), output and control unit.
 Input device accepts the coded information as source program i.e., high level language.
 This is either stored in the memory or immediately used by the processor to perform the
desired operations.
 The program stored in the memory determines the processing steps.
 Basically, the computer converts one source program to an object program. i.e., into
machine language.
 Finally, the results are sent to the outside world through output device. All of these
actions are coordinated by the control unit.

Figure: Elementary Functional Units of Computer

Input unit
 The source program/high level languages program/coded information/simply data is fed
to a computer through input devices keyboard is a most common type.
 Whenever a key is pressed, one corresponding word or number is translated into its
equivalent binary code over a cable & fed either to memory or processor.
 Example –Keyboard, Joysticks, trackballs, mouse, scanners etc. are other input devices.
Memory unit:
Its function is to store programs and data. It is basically two types namely, primary memory and
secondary memory.
Primary memory:
 Is the one exclusively associated with the processor and operates at high speed.
 The memory contains a large number of semiconductors storage cells.
 These are processed in a group of fixed size called word.
 Programs must reside in the memory during execution. Instructions and data can be
written into the memory or read out under the control of processor.

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 Secondary memory:
 This type of memory is used where large amounts of data & programs have to be
stored, particularly information that is accessed infrequently.
 Examples: - Magnetic disks & tapes, optical disks (i.e., CD-ROM’s), floppies etc.
Arithmetic logic unit (ALU):
Most of the computer operations are executed in ALU of the processor like addition, subtraction,
division, multiplication, etc. The operands are brought into the ALU from memory and stored in
high-speed storage elements called register.
Control unit:
The operations of all the units are coordinated by the control unit i.e., it acts as a nerve centre
that sends signals to other units and senses their states. The actual timing signals that govern the
transfer of data between input unit, processor, memory and output unit are generated by the
control unit.
Output unit:
These are the counterparts of input unit. Its basic function is to send the processed results to the
outside world after processing. Examples: - Printer, speakers, monitor etc.
Bus Structure
A bus is a communication system that transfers information (in any form like data, address or
control information) between components, inside a computer, or between computers.
 It is the group of wires carrying a group of bits in parallel.
 There are three kinds of bus according to the type of information they carry like
1. Data Bus 2. Address Bus and 3. Control Bus
 A bus which carries a word from or to memory is called Data bus. It carries the data from
one system module to other. Data bus may consist of 32, 64, 128 or even more numbers
of separate lines. This number of lines decides the width of the data bus. Each line can
carry one bit at a time. So, a data bus with 32 lines can carry 32bit at a time.
 Address Bus is used to carry the address of source or destination of the data on the data
bus.
 Control Bus is used to control the access, processing and information transferring.

Figure: Depiction of Bus Structure

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 In this method bus architecture, the processor will completely supervise and participate in
the transformation.
 The information will be first taken to the processor register and then to the memory such
that transfer is known as program-controlled transfer.
 The interconnection between i/o unit, processor and memory accomplished by two
independent system bus is known as two-way bus interconnection structure.
 The system bus between i/o unit and processor consist of DAB (Device address bus), DB
(Data bus), CB (Control bus). Similarly, the system bus between memory processor
consists of MAB (Memory address bus), DB, and CB.
 The communication exists between
 Memory to processor
 Processor to memory
 I/O to processor
 Processor to I/O
 I/O to memory

Memory addressing

The maximum size of the memory that can be used in any computer is determined by the
addressing scheme. For instance a 16-bit computer that generates a 16-bit address is capable of
addressing up to 216k memory location. The number of location represents the size of the address
space of computer. Most modern computers are byte addressable computer.

A control memory is a part of the control unit. Any computer that involves microprogrammed
control consists of two memories. They are the main memory and the control memory. Programs
are usually stored in the main memory by the users. Whenever the programs change, the data is
also modified in the main memory. They consist of machine instructions and data.

The control memory consists of microprograms that are fixed and cannot be modified frequently.
They contain microinstructions that specify the internal control signals required to execute
register micro-operations.

The machine instructions generate a chain of microinstructions in the control memory. Their
function is to generate micro-operations that can fetch instructions from the main memory,
compute the effective address, execute the operation, and return control to fetch phase and
continue the cycle.

The figure below demonstrate the general configuration of a microprogrammed control

organization.

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 In this, the control is presumed to be a Read-Only Memory (ROM), where all the control
information is stored permanently. ROM provides the address of the microinstruction. The other
register, that is, the control data register stores the microinstruction that is read from the memory.
It consists of a control word that holds one or more micro-operations for the data processor.

The next address must be computed once this operation is completed. It is computed in the next
address generator. Then, it is sent to the control address register to be read. The next address
generator is also known as the microprogram sequencer. Based on the inputs to a sequencer, it
determines the address of the next microinstruction. The microinstructions can be specified in
several ways.

The main functions of a microprogram sequencer are as follows −

 It can increment the control register by one.

 It can load the address from the control memory to the control address register.
 It can transfer an external address or load an initial address to begin the start operation.

The data register is also known as the pipeline register. It allows two operations to be performed
at a time. It allows performing the micro-operation specified by the control word and also the
generation of the next microinstruction.

A dual-phase clock is required to be applied to the address register and the data register. It is
possible to apply a single-phase clock to the address register and work without the control data
register.

The main advantage of using a microprogrammed control is that, if the hardware configuration is
established once, no further changes can be done. However, if a different control sequence is to
be implemented, a new set of microinstructions for the system must be developed.

INSTRUCTIONS AND INSTRUCTION SEQUENCING

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The instruction set defines many of the function performed by the CPU and plays a
significant role in the implementation of the CPU.
The factors to be taken into account while designing an instruction set are namely, operation
set, data type, format of instruction, register and addressing mode.

1. Operation set: This gives an idea how many & what kind of operation need to be
provided and also the complexity of such operation.
2. Data type: Information needs to be provided on the various types of data & operation to
be performed on them.
3. Format of instruction: This includes the length of the instruction in bits, number of
addresses to be used with the instruction and the size of each field in the instruction.
4. Register: The number of CPU register that can be accessed by instruction for storage of
data & operands.
5. Addressing mode: The instruction set also specifies addressing methods for accessing
operands either in the memory or in the processor register.

Types of Operands
Machine operation depends on the types of data being processed. The different format of
data to be used with assembly and high-level language program are as follows
1. Address 2. Number 3. Character 4. Logical data

Address

 Address is a form of numbers that represent specific location in the memory.

 Address may be considered as unsigned integer.
Number
 Numeric data types are used by all machine language.
 Three types of numerical data are commonly used :
1. Integer or Fixed point
2. Floating point
3. Decimal
Character
Another common form of data is represented in a program are character string. As it
cannot be stored or processed so these form of data are coded by any of the conversion
method like American Standard Code for Information Interchange (ASCII) and
Extended Binary Coded Decimal Interchange Code (EBCDIC).
Logical data

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  This is the bit-oriented view of data.
 These types of data can be represented as an array of Boolean or binary data
items (1 for T and 0 for F).

Addressing Modes

 The operand field of an instruction specifies the address from where the data has
to be fetched.
 This may be a memory address, register or may be a direct value.
 The operand chosen is dependent on the addressing mode of the instruction.

The most common addressing techniques are as follows

1). Immediate. 2). Direct. 3). Indirect. 4). Register. 5). Register indirect. 6). Displacement. 7). Stack

1). Immediate Addressing:

The simplest form of addressing is immediate addressing, in which the operand

is actually present in the instruction:
OPERAND = A

The advantage of immediate addressing is that no memory reference other than the
instruction fetch is required to obtain the operand.

LOAD A, #10

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A: This is the destination register. The data will be loaded into register A.
 #10: This is the immediate operand. The value 10 is directly included within the
instruction itself.

This instruction loads the immediate value 10 into register A.

Characteristics:

i. Efficiency for Constants: Immediate addressing is efficient for loading small, constant
values.
ii. Simplicity: It's a straightforward way to load specific values into registers or memory
locations.
iii. Limited Range: The range of values that can be represented as immediate operands is
typically limited by the instruction format.

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Importance:

Immediate addressing provides a convenient way to incorporate constant values directly into
your assembly language code, making it a valuable addressing mode for various programming
tasks.

2). Direct Addressing:

 A very simple form of addressing is direct addressing, in which the address field
specifies the address of the memory location.

 It requires only one memory reference and no special calculation

LOAD A, [2000]
 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A: This is the destination register. The data will be loaded into register A.
 [2000]: This is the direct address operand. The square brackets indicate that the value
within the brackets is a memory address. In this case, the instruction loads the data stored
at memory location 2000 into register A.

Characteristics of Direct Addressing:

i. Data is located at a specific memory address: The instruction directly specifies the
memory address where the operand is located.
ii. Suitable for accessing fixed data locations: Useful for accessing data stored in specific
memory locations, such as global variables or constant tables.
iii. Limited flexibility: The address must be known at assembly time.

Importance:

Direct addressing provides a way to access data stored at a specific memory location. This
addressing mode is often used when the location of the data is known and fixed.

3). Indirect Addressing:

 The address field of the instruction uses the address of the operand stored in the
memory.

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  The effective address of the operand is given by the address part of the
instruction.

LOAD A1, [A2]

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 [A2]: This is the indirect address operand. The square brackets indicate that the value
within the brackets is a memory address. However, instead of a fixed address like in
direct addressing, the address is stored in another register (A2 in this case).

Procedure:

i. Read Register A2: The processor reads the value stored in register A2.
ii. Use A2 as an Address: The value read from A2 is treated as a memory address.
iii. Access Memory: The processor then accesses the memory location specified by the
value in A2.
iv. Load Data: The data stored at that memory location is loaded into register A1.

Characteristics of Indirect Addressing:

 Flexibility: Allows you to access data at memory locations whose addresses are stored in
registers.
 Dynamic Memory Access: Enables accessing data in different parts of memory by
simply changing the value in the register.
 Used in Array and Pointer Operations: Often used for accessing elements of arrays,
implementing pointers, and manipulating data structures.

4). Register Addressing:

 Register addressing is similar to direct addressing.
 The only difference is that the address field refers to a register rather than a
main memory address.

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LOAD A1, A2

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 A2: This is the source register. The data will be loaded from register A2.

Procedure:

i. Read Register A2: The processor reads the value currently stored in register A2.
ii. Load Data: The value read from register A2 is directly copied into register A1.

Characteristics of Register Addressing:

 Fast Access: Accessing data directly from registers is the fastest form of data access.
 Used for Intermediate Results: Often used to hold intermediate results during
calculations.
 Efficient for Frequently Used Data: If data is frequently used, keeping it in registers
can significantly improve performance.

5). Register Indirect Addressing:

Register indirect addressing is similar to indirect addressing, except that the address
field refers to a register instead of a memory location.

LOAD A1, (A2)

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 (A2): This is the register indirect address operand. The parentheses around A2 indicate
that the value in register A2 is used as an offset or index into memory.

Procedure:

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 i. Read Register A2: The processor reads the value stored in register R2.
ii. Calculate Memory Address: The value in A2 is added to a base address (which may be
implicit or specified separately) to determine the actual memory address.
iii. Access Memory: The processor accesses the memory location calculated in the previous
step.
iv. Load Data: The data stored at that memory location is loaded into register A1.

Characteristics of Register Indirect Addressing:

 Flexibility: Allows you to access elements within an array or a block of memory by

using an index stored in a register.
 Dynamic Memory Access: Enables efficient access to elements within data structures
like arrays and linked lists.
 Often used with Stack Pointer: Can be used to access data on the stack by using the
stack pointer (SP) as the index register.

Importance:

Register indirect addressing provides a flexible way to access data within a specific region of
memory by using a register to offset from a base address. This is crucial for efficient array and
data structure manipulation.

6). Displacement Addressing:

A very powerful mode of addressing combines the capabilities of direct addressing and
register indirect addressing, which is broadly categorized as displacement addressing:
EA = A + (R)
Three of the most common use of displacements addressing are as follows:

• Relative addressing
• Base-register addressing
• Indexing

LOAD A1, 100(A2)

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  LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 100(A2): This is the displacement address operand.
 A2: This register holds a base address.
 100: This is a constant displacement or offset value.

Procedure:

1. Read Register A2: The processor reads the value stored in register A2.
2. Calculate Effective Address: The displacement value (100) is added to the value in
register A2. This sum represents the effective memory address.
3. Access Memory: The processor accesses the memory location calculated in the previous
step.
4. Load Data: The data stored at that memory location is loaded into register A1.

Characteristics of Displacement Addressing:

 Flexibility: Allows you to access data at a fixed offset from a base address stored in a
register.
 Array Access: Commonly used to access elements within an array by using the array
base address in a register and the element index as the displacement.
 Data Structure Access: Useful for accessing fields within structures by using the
structure's base address and field offsets.

Importance:

Displacement addressing provides a way to access data at a specific offset from a base address
stored in a register. This is a versatile addressing mode for accessing elements within arrays,
structures, and other data structures.
A). Relative Addressing:
 In this mode, the instruction specifies the operand address as the relative
position of the current instruction address i.e., content of PC.
 The current instruction address is added to the address field to produce effective
address.
JUMP 1000

 JUMP: This is the instruction mnemonic, indicating that the program flow should jump
to a new location.
 1000: This is the relative address. It's a displacement value that specifies the number of
bytes to jump relative to the current instruction (the JUMP instruction itself).

Procedure:

 Calculate Target Address:

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 o The processor determines the address of the current instruction (the JUMP
instruction).
o It then adds the displacement value (1000) to the current instruction's address.
This sum represents the target address of the jump.
 Jump to Target Address: The program execution immediately transfers to the
instruction located at the calculated target address.

Key Characteristics of Relative Addressing:

 Position-Independent Code: Relative addressing can be used to create position-

independent code (PIC), which can be loaded and executed anywhere in memory without
modification.
 Compact Representation: Relative addresses are often shorter than absolute addresses,
saving space in the instruction stream.
 Used for Jumps and Calls: Commonly used for implementing jumps, subroutine calls,
and loop control within programs.

Importance:

Relative addressing provides a way to jump to a location relative to the current instruction,
making it useful for creating flexible and position-independent code.

B). Base-Register Addressing:

In this mode, the reference register contains a memory address, and the address field
contains a displacement from that address.
LOAD A1, 0(A2)

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 0(A2): This is the base-register addressing operand.
 A2: This register holds a base address.
 0: This is a displacement value (in this case, zero).

Procedure:

1. Read Register A2: The processor reads the value stored in register A2.
2. Calculate Effective Address: The base address in register A2 is used as the effective
memory address.
3. Access Memory: The processor accesses the memory location specified by the value in
A2.
4. Load Data: The data stored at that memory location is loaded into register A1.

Characteristics of Base-Register Addressing:

 Flexibility: Allows you to access data relative to a base address stored in a register.

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  Array Access: Often used to access elements within an array by using the array base
address in a register.
 Data Structure Access: Useful for accessing fields within structures by using the
structure's base address in a register.

Importance:

Base-register addressing is a special case of displacement addressing where the displacement

value is zero. It allows you to directly access data at a memory location specified by a base
address stored in a register

C). Index addressing:

 In this mode an index register contains the offset value.
 The instruction contains the address that should be added to the offset in the
index register to get the effective address.

LOAD R1, 10(R2, R3)

 LOAD: This is the instruction mnemonic, indicating that the operation is to load data
into a register.
 A1: This is the destination register. The data will be loaded into register A1.
 10(A2, A3): This is the index addressing operand.
 A2: This register holds a base address.
 A3: This register holds an index value.
 10: This is a displacement value (optional).

Procedure:

1. Read Registers A2 and A3: The processor reads the values stored in registers A2 and A3.
2. Calculate Effective Address:
o The value in register A3 (index) is multiplied by the size of the data element (e.g.,
4 bytes for 32-bit integers).
o The displacement value (10) is added to the product.
o The result is added to the base address in register A2.
3. Access Memory: The processor accesses the memory location calculated in the previous
step.
4. Load Data: The data stored at that memory location is loaded into register A1.

Characteristics of Index Addressing:

 Array Access: Primarily used for accessing elements within arrays.

o A2 holds the base address of the array.
o A3 holds the index of the desired element.
 Data Structure Access: Can be used to access elements within more complex data
structures.
 Flexibility: Provides a flexible way to access elements within arrays or data structures by
using an index value.

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Importance:

Index addressing combines base-register addressing with an index value to efficiently access
elements within arrays or data structures.

Instruction format

An instruction format defines the layout of the bits of an instruction in an

instruction set.
Usually there are several instruction formats in an instruction set.

1. An operation code:-This specifies the operation to be performed such as ADD,

SUB, LOAD, STORE, MOV, JUMP etc.
2. Source operand:- The operand specified by the opcode may involve one or
more sources for operand, these act as the input for the operation (It is the data
that is read from a specific location (register, memory) as input for the
instruction).
3. Resultant operand:-After processing the result must have to be stored in an operand
(It's the destination where the result of the operation is stored).
4. Next reference instruction:-This field tells the CPU from where the next
instruction is to be fetched after the execution is completed (E.g. JUMP, CALL
etc.).

Three address Instruction

Computer with three addresses instruction format can use each address field to specify
either processor register or memory operand.

ADD R1, A, B R1 ® M [A] + M [B]

ADD R2, C, D R2 ® M [C] + M [D]
MUL X, R1, R2 M [X] R1 * R2

 The advantage of the three address formats is that it results in short program
when evaluating arithmetic expression.
 The disadvantage is that the binary-coded instructions require too many bits to
specify three addresses.

Two Address Instruction

 Most common in commercial computers.
 Each address field can specify either processes register or a memory word.
MOV R1, A R1 ® M [A]
ADD R1, B R1 ® R1 + M [B]
MOV R2, C R2 ® M [C] X = (A + B) * (C + D)
ADD R2, D R2 ® R2 + M [D]

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 MUL R1, R2 R1 ® R1 * R2
MOV X, R1 M [X] ® R1

One Address instruction

It used an implied accumulator (AC) register for all data manipulation. For
multiplication/division, there is a need for a second register.

LOAD A AC ® M [A]
ADD B AC ® AC + M [B]
STORE T M [T] ® AC X = (A +B) × (C + A)

 All operations are done between the AC register and a memory operand.
 It’s the address of a temporary memory location required for storing the
intermediate result.

LOAD C AC ® M (C)
ADD D AC ® AC + M (D)
ML T AC ® AC * M (T)
STORE X M [X] ® AC

Zero Address Instruction

A stack organized computer does not use an address field for the instruction ADD and
MUL. The PUSH & POP instruction, however, need an address field to specify the
operand that communicates with the stack (TOS ® top of the stack)
PUSH A TOS ® A
PUSH B TOS ® B
ADD TOS ® (A + B)
PUSH C TOS ® C
PUSH D TOS ® D
ADD TOS ® (C + D)
MUL TOS ® (C + D) * (A + B)
POP X M [X] TOS

MEMORY SYSTEM
Memory characteristics
The memory unit is the essential component in any computer since it is needed for storing
the program and data. The memory system is classified according to their key characteristics
like: 1. Location, 2. Capacity, 3. Unit of Transfer 4. Access Method, 5. Performance, 6.
Physical type and 7. Physical characteristics.
1. Location: It deals with the location of the memory device in the computer system. There are
three possible locations:
 CPU: This is often in the form of CPU registers and small amount of cache
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 Internal or main: This is the main memory like RAM or ROM. The CPU can directly access
the main memory.
 External or secondary: It comprises of secondary storage devices like hard disks, magnetic
tapes. The CPU doesn’t access these devices directly. It uses device controllers to access
secondary storage devices.
2. Capacity:
The capacity of any memory device is expressed in terms of: i) Word size ii) Number of words
Word size: Words are expressed in bytes (8 bits). A word can however mean any number of
bytes. Commonly used word sizes are 1 byte (8 bits), 2bytes (16 bits), 4 bytes (32 bits) and 8
bytes (64 bits). It is the amount of data that can be processed in a single operation.
Number of words: This specifies the number of words available in the particular memory
device. For example, if a memory device is given as 4K x 16.This means the device has a word
size of 16 bits and a total of 4096(4K) words in memory. This is the total number of words that
can be stored in a computer’s memory. Hence, it determines the total amount of data that can be
stored in memory.
3. Unit of Transfer: It is the maximum number of bits that can be read or written into the
memory at a time. In case of main memory, it is mostly equal to word size. In case of external
memory, unit of transfer is not limited to the word size; it is often larger and is referred to as
blocks.
4. Access Methods: It is a fundamental characteristic of memory devices. It is the sequence or
order in which memory can be accessed. There are three (3) types of access methods:
 Random Access: If storage locations in a particular memory device can be accessed in
any order and access time is independent of the memory location being accessed. Such
memory devices are said to have a random-access mechanism. RAM (Random Access
Memory) integrated circuits (IC) use this access method.
 Serial Access: If memory locations can be accessed only in a certain predetermined
sequence, this access method is called serial access. Magnetic Tapes, CD-ROMs employ
serial access methods.
 Semi random Access: Memory devices such as Magnetic Hard disks use this access
method. Here each track has a read/write head thus each track can be accessed randomly
but access within each track is restricted to a serial access.
5. Performance:
The performance of the memory system is determined using three parameters.
 Access Time: In random access memories, it is the time taken by memory to complete
the read/write operation from the instant that an address is sent to the memory. For non-
random access memories, it is the time taken to position the read write head at the desired
location. Access time is widely used to measure performance of memory devices.
 Memory cycle time: It is defined only for Random Access Memories and is the sum of
the access time and the additional time required before the second access can commence.
 Transfer rate: It is defined as the rate at which data can be transferred into or out of a
memory unit.
 For a random-access memory, it is equals to 1.

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  For a non-random access memory, it can be calculated as TN = TA+(N/R) Where
TN is the Average time to read or write, TA is the Average access time, N is
Number of bits and R is the Transfer rate in bps.

6. Physical type:
Memory devices can be either semiconductor memory (like RAM) or magnetic surface memory
(like Hard disks).
7. Physical Characteristics:
 Volatile/Non- Volatile: If a memory device continues hold data even if power is turned
off. The memory device is non-volatile else it is volatile.
Memory –Processor Data transfer/ Basic Memory Operation
 The memory unit supports two basic operations: read and write. The read operation reads
previously stored data and the write operation stores a new value in memory.
 Both of these operations require a memory address. In addition, the write operation
requires specification of the data to be written.
 The address and data of the memory unit are connected to the address and data buses of
the system bus, respectively.
 The read and write signals come from the control bus.
 For controlling the movement of these words i.e., in and out two signals are used to
 Write
 Read respectively
 The words to be written or moved in, are first entered to the register, that is called
memory data register (MDR).
 The location in the memory unit that a word is stored is called as Address of the word. To
take out or retrieve a word from a memory unit one has to specify its address in another
special register which is called as memory address register (MAR).
 MAR of R bit especially the memory size is of 2K word. Similarly, MDR of n bit
determines the word size is of n bit (n number of cells present in a word).

2K addressable locations
n-bit words- Word length
Read operation
 For Read operation the address has to be sent to MAR which is being carried out by the
address bus then the READ signal is sent to the memory for read function.
 The memory transfers the corresponding word from the specified location to the MDR
through data bus.

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  Drop the memory read control signal to terminate the read cycle.
 After the completion of the Read Operation the memory transfer Memory function
completed signal (MFC).
Write operation
 For write operation the CPU specify the location to MAR and data to MBR then MDR.
 Then it transfers the Write control signal after which the data which is present in MDR is
transfer to the memory.
 After completion of the write operation memory transfer MFC signal.
Access time
The duration of time between the initiation of read signal and the availability of required word in
the MBR is called as the access time or read time.
Write time
The duration between the write signal and storing of the word in the specified location is called
as write time.
Memory cycle time: - It is necessary that the information should be written back from where it
was read. The duration of read and write operation is called as memory cycle time (is the total
time taken for a computer memory to complete one read or write operation. It is also called
memory access time).
SEMICONDUCTOR RAM: -
Semiconductor memories are available in a wide range of speed and their cycle time ranges from
100 ns to less than 10ns.
ORGANISATION OF MEMORY CHIP: -
Memory cells are organized in the form of an array of cells, each cell capable of storing one bit
of information.
 Each row of cells constitutes a memory word of 8bits b0-b7 and cells of a row are
connected to a common signal line called “word line”, which is driven by the address
decoder.
 Two ‘bit lines ' connect the cells in each column to a sense /write circuit.
 The sense / write circuit are connected to the data I/O lines.
 During a 'Read' operation, these circuits read the information stored and transmits this
information to the output data line.
 During a 'Write' operation, the sense/write circuit receives input information and store it
in the selected cell.
 An organization of a very small memory chip consisting of 8bits of 16 words i.e., 16×8
organization.
 The data I/O of each sense/write circuit are connected to a single bidirectional data lines
that are connected to the data bus of the computer.
 In addition, there are also two control lines R/W and chip select (CS).

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  The R/W signal line specifies, the required operations and CS selects a given chip in
multi-chip memory system.
 This memory circuit stores 128 bits and it requires 14 external connections for address
data and control line. It also needs two lines for power supply and ground connection.
 For a larger memory circuit let 1k (1024) memory cell can be organized as 128×8
memory requires 17 or 19 (with other optional control lines output enabler (OE) and
write enabler (WE)) external connections.
To determine the external connections required for a 128 bits memory, we need to look
into the following factors.
Since we have 128 bits and each word is 8 bits, then 128/8= 16 = 2^4. Thus, we have 4
address line.
i. Number of address lines: since we have 16 words (128 bits), we will need 4 address
lines (A0-A3) to select one of the 16 words.
ii. Number of data lines: since each word is 8 bits (1 byte), we will need 8 data lines (D0-
D7) to transfer data.
iii. Control lines: We will also need the two control lines i.e. R/W and CS.
The external connections required for a 128 bits memory are:
 4 address lines (A0-A3)
 8 data lines (D0-D7)
 2 control lines (R/W and CS)
Hence, we will need 14 external connections.
Cache memory: -
 The speed of main memory is very slow in compare to the speed of processor. Hence, for
better performance a high-speed memory is used in between main memory and CPU.
That is known as cache memory.
 The cache memory comes from the word cache meaning to hide.
 The basic idea behind a cache is simple i.e., the most heavily used memory words are
kept in the cache, when the CPU needs a word, it will first look in the cache, only if the
word is not there, it goes to main memory.
 Analysis of a program shows the maximum program execution time spent in those
portions in which many instructions were executed repeatedly as in loops, hence for the
execution of the programs forms a localize area. Thus, for the execution of the programs
forms a localize area, where the programs or instruction executed repeatedly and the
remainder of the programs are executed relatively less frequently that is called locality of
reference.

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Read operation: -
 When the CPU needs to access memory, the cache is first searched, if the word is found,
it read, this is known as “cache hit”.
 If the word is not found, then the main memory is referred as “cache miss”.
 When a “cache miss” occurs, it initiates to access main memory to transfer the required
byte or word from main memory to cache.
 The performance of the cache memory is known as hit ratio.

Computation Example:
Cache Access Time (CAT) = 100ns
Main memory access time (MAT) is 1000ns
Hit Ratio (h) = 0.9.

Question: Find out the average memory access time.

Solution:
Average memory access time = cache access + main memory time
= h*CAT + (1-h) * MAT
Average Memory Access Time (AVMAT)
= 0.9*100+ (1-0.9) *1000
AVMAT = 90 + 100
AVMAT = 190ns
Write operation: -
During read operation, when the CPU finds a word in cache memory, then the main memory is
not involved in the transfer. But in case of write operation there are two ways of writing.
(1) Write through policy.
(2) Write back policy.
Write through policy: -
The simplest and most commonly used procedure is to update main memory with every memory
write operation with cache memory being update in parallel. This is called as write through
policy.

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 Write-through cache. With a write-through caching policy, the processor writes to the cache
first and then waits until the data is updated in memory or disk. This ensures data is always
consistent between cache and other storage assets. However, it takes longer to write to
memory and much longer to write to disk than it does to write to cache, so the processor
must wait and often suffer reduced performance as a result.
Advantages:-
This method is the most important characteristics of direct memory access transfer.
Write back policy
With write-back caching, the processor writes data to its local cache first before writing that
cached data to memory or disk. The cached data is then only written to memory or disk later in
intervals as a background task or as applications attempt to access the data.
Advantages
Whenever the word is updated several times, it is better to use write back policy.
Mapping
The transformation of information from main memory to cache memory is known as Mapping.
There are three types of mapping function
 Direct Mapping
 Associative Mapping
 Set-associative Mapping
To explain the mapping procedures, Let consider 2K cache consisting of 128 blocks of 16 words
each, and a 64K main memory addressable by a 16-bit address, 4096 blocks of 16 words each.
Direct Mapping
 Block m of the main memory maps onto block c of cache memory according to formula c
=m mod no of block of cache memory c = m mod 128.
 By this formula the block o,128,256…. Of main memory will be loaded to 0 block of
cache memory. Similarly block 1,129,257 …. of main memory will be loaded to 1 of CM
and likewise.
 For this mapping the CPU generates address for cache memory is 16 bits.
 The address is divided into 3 parts.
 Word
 Block
 Tag
The bit pattern will be as follows;
Tag Block Word
Direct Mapping

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  One block contains 16 words , so 4 bits are required to indicate word field, cache contain
128 blocks so 7 bits are required to indicate block field and the rest 16- (7+4)=5 bits are
required to indicate tag bit.
 When CPU wants to read or write then the higher order 5 bits of the address are being
compared with the tag bit of cache memory,
 If it matches then the desired word is present and a cache hit occurs.
 If not, there will be a cache miss which leads to a write operation.
Advantage
It is the simplest method of implementation.
Disadvantage
The contention problem may occur even though the cache is not full.
Associative mapping
 A main memory block can be placed into any cache block position.
 The 12 tag bits identify a memory block residing in the cache.
 The lower-order 4 bits select one of 16 words in a block.
 The cost of an associative cache is relatively high because of the need to search all 128
tags to determine whether a given block is in the cache or not.
Advantage:
An MM block can be mapped anywhere in CM.
Disadvantage:
It is slow and expensive; a search through all the 128 CM blocks is needed to check whether the
12 MSBs of the 16-bit address can be matched to any of the tags.

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Set-Associative Mapping:
 Blocks of the cache are grouped into sets, and the mapping allows a block of the main
memory to reside in any block of a specific set.
 A cache that has k no of blocks per set is referred to as a k-way set-associative cache.
 The contention problem of the direct method is eased.
 The hardware cost of the associative method is reduced.

Interleaved Memory
 The two key factors in the success of computer are performance and cost.
 This can be achieved through parallelism.
 In parallel processing or pipeline environment, the main memory is the prime system
resources, which is normally shared by all processor or stages of the pipeline.
 In such cases there may be memory interference, which as a result degrades the
performance. So, to avoid this problem, a new method is adopted which is known as
“Memory interleaving”.
 The Memory interleaving means the main memory of the computer into a no of modules
and distributing the address among those modules.
 Each memory module has its own Address Buffer Register (ABR)or Memory Address
Register (MAR) and Data Buffer Register (DBR) or Memory Buffer Register (MBR).
 There are two memory address layouts:
1. High order interleaving (Consecutive words in a module)
2. Low order interleaving (consecutive words in consecutive module)
 The address consists of :(1) (2) low-order m-bits point to a particular word in that module
HIGH ORDER INTERLEAVING: -
In this type of memory INTERLEAVING the memory is divided into M no. of modules where
the consecutive address lies in a single module.
 In this method the higher order bit of the address used for indicating the module no. and
the lower order bits are used for indicating the address in module.
 Let for example we have a memory having 16 words.

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  In the above case the higher order bits used for indicating the module no. and the lower
order bits are used for the words in the module.
 In this case each memory address is of n bit out of which the higher order m bits are
used for interleaving and n-m bits are used for the words in particular module.
 The m bits are being decided by the decider which will specify the particular module
no. and n-m bit specify the words in the module.
 Every memory module has its own MAR and MBR.
Advantage: -
 It permits easy expansion of memory by addition of one or more memory module as
needed to a maximum of m-1.
 Better system reliability in case of a failed module as it affects only a localized area f
address space.
Disadvantage: -
 When consecutive location is to be accessed then only one module is involved.
LOW ORDER INTERLEAVING: -
In this memory interleaving the consecutive words are distributed in consecutive modules.
 Here the higher order n-m bits are used for address of words in a module while m lower
bits are used for module number.
 This method is efficient way to address the module.
 Here any request for accessing consecutive words can keep several modules busy at the
same time; this is faster than the previous one and so used frequently.
 Ex:-all have 16 words.

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 PROCESSOR SYSTEM
INTRODUCTION
The part of the computer that performs the bulk of data processing operation is called the central
processing unit, CPU.
The CPU is made up of three (3) major parts
i. ALU: - Arithmetic Logic Unit performs the required microoperation for executing the
instruction.
ii. Register Set: - Stores the intermediate data used during the execution of instruction. 3.
Control Unit: - Supervises the transfer of information among register and ALU by sending
suitable control signal.

Control unit
The Control Unit (CU) is the heart of the CPU. Every instruction that the CPU supports has
to be decoded by the CU and executed appropriately. Every instruction has a sequence of
microinstructions behind it that carries out the operation of that instruction.
 Any digital system consists of 2 units
 Data processor
 Control logic
 Data processor consists of individual register and all functional unit.
 Control logic initiates all micro-operation in the data processor.
 Control unit generates control signal which initiates sequence of micro-operation.
 By issuing control signal which micro-operation are activated are represented as
sequence of 1s and which are not activated represented as 0s.
 Traditionally there are two general approaches to implement a control and decode unit for
a CPU :
 Hardwired control Unit
 Micro programmed control Unit
Hardwired control unit
 In the hardwired organization, the control logic is implemented with gates, flipflop,
decoder and other digital circuits.
 It has the advantage that it can be optimized to produce a fast mode of operation.
 A hardwired control for all the basic computer is shown in the above figure.
 The hardwired control unit consists of 2 decoders, a sequence counter and a number of
control logic gates.

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  The instruction fetched from memory is placed in IR (instruction register).The IR is
divided into 3 parts. The I bit, the operation code and bits 0-11.
 The opcode 12-14 are decoded with a 3×8 decoder. the eight o\p of the decoder are
designated by the symbol D0-D7.
 The subscripted decimal is equivalent to the binary value of the corresponding operation
code. • Bits 0-11 are applied to the control logic gates.
 The 4-bit SC (sequence counter) is decoded into 16 timing signals through T0-T15.
 The SC can be incremented/cleared synchronously.
 All these inputs like 0-11 of IR, decoded opcode from D0-D7, the o/p of I flipflop, the
timing signal T0-T15 and other input are given to control logic gates.
 These control logic gates decide the states of I/p and provide the appropriate control
signal and timing signal.
 Depending on this control signal, the ALU takes the appropriate action.
Micro programmed control unit
 Every instruction in a CPU is implemented by a sequence of one or more sets of
concurrent micro-operation. Each micro-operation is associated with a specific set of
control lines which when activated cause the micro-operation to take place.
 Here to generate the control signal, the CU execute a series of sequential steps of
microoperation.
 The control variable at any given time can be represented by a string of 1s or 0s called
control word.
 In micro programmed the binary control words are stored in memory called control
memory.
 The computer which employs micro programmed control possess 2 separate memories
namely 1). Main memory and 2). Control memory
 Main memory is available for storing program. content of main memory may alter by
changing the program.
 Each machine instruction in main memory initiates a series of micro instruction in control
memory.
 Microinstruction generates micro-operation such as fetch instruction from main memory,
calculate effective address, fetch operand, execute the operation etc.
 Each control word in control memory contains within it a microinstruction.

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  A sequence of microinstruction constitutes a micro program.
 For a particular control signal a particular micro program is written, since there is no need
to change the micro program stored in control memory, the control memory can be stored
in ROM.

Figure: Micro-programmed control organization

 Therefore, to execute a micro program stored in control memory to get the appropriate
control word for generation of control signal, the following operation is to be done.
 The control memory address specifies the address of micro instruction & the control data
register holds the microinstruction read from memory.
 The microinstruction contains a control word that specifies one or more micro-operation
for the data processor, once these operations are executed , the control must determine the
next address.
 The next address may also be a function of external input condition.
 The next address generator is a circuit that generates the next address which is then
transferred into the control address register to read the micro instruction.
 The next address generator sometimes called as micro program sequencer.

REGISTER FILES
 Most modern CPUs have a set of general purpose (GPRs) register R 0 to Rn-1 called
register files.
 Each register Rm in RF is individually addressable with address subscript m. Example: -
R2=f (R1, R2).
 This way the processor is able to retain intermediate results in fast and accessible
registers rather than external memory M.
 For accessing RF needs several ports for simultaneous reading and writing purposes, so it
is often realized as a ‘multiport RAM’.
 A multiport RF is built using a set of registers of proper size and multiplexer
demultiplexer.
 The read operation can take place through several devices reading from the same register
using different ports though the writing is normally done through one port only.
 The above RF shows a three port, where simultaneous read can occur from port A and
port B and writing takes place using port C.

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 Complete instruction Execution
The CPU executes each instruction in a series of small steps:
1. Fetch the next instruction from memory the instruction register (IR).
2. Change the program counter (PC) to point to the following instruction.
3. Decode the instruction just fetched.
4. If the instruction uses data in memory determine where they are.
5. Fetch the data if any, into internal CPU register.
6. Execute the instruction.
7. Store the result in the appropriate place.
8. Go to step 1 to begin executing the following instruction.
This above sequence of steps (micro-operation) is frequently referred to as the fetch-decode-
execute cycle or instruction cycle. During an instruction cycle, the action of the CPU is defined
by the sequence of microoperation it executes.
The time required by the CPU to execute a microoperation is the CPU cycle time or clock period.
DESIGN OF ALU
 The circuits which carry out the data processing instructions, is the ALU.
 The complexity of the ALU depend upon how the instruction are realized.
 The ALU using combinational circuits can perform fixed point arithmetic as well as word
based logical operation.
 Some extra control logic and some extensive data processing circuits called as coprocessor
are employed to perform floating point operation.
COMBINATIONAL ALU
 The simple ALU combines the both features of 2’s complement added subtractor and word-
based logic unit.
 The combinational ALU is nothing but a combination of combinational circuits and
multiplexer.

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 Figure: Combinational ALU Basic n-bit ALU
The above figure shows that:
 Mode control line attached to the two-way n bit multiplexer determines the type of operation
i.e., logical or arithmetic.
 The select line S determines the specific operation to be performed by the desired sub unit.
 As the select line is of 4 bits, we can get 16 different logical and also 16 different arithmetic
operation.
 Example: - by taking the values of M, the four combinations are as follows.
M 3=x i yi M 2=x i y i M 1=x i y i M 0=x i y i

F ( x , y )=M 3 S3 + M 2 S 2+ M 1 S 1 + M 0 S 0

¿ x i y i S 3 + x i y i S 2+ xi y i S 1+ x i y i S 0

 So, for every combination of S3, S2, S1 and S0 we will get a different operation.
ADVANTAGE
 This type of ALU is much simpler.
DISADVANTAGE
 It is more expensive.
 It is much slower.

INPUT OUTPUT SYSTEM

Introduction
 I/O is an essential & integral part of computer system. Variety of I/O devices on a
computer system - keyboard, mouse, display, magnetic disk, network adaptor, etc.
 I/O devices differ widely in terms of function,size, mode ofoperation, transferspeed, power
consumption, etc.
 All devices must be connected to the processor and memory using the same basic
architecture.
 Over the years, different mechanisms have been developed to connect I/O devices to
systems, and to program I/O data transfers over the resulting connections.
I/O controllers
 An I/O device is connected to the computer system by using a device controller.
 I/O devices vary in of some or all of the following characteristics:
 Representation of data: voltage, current, magnetic field, etc.
 Speed of operation and data transfer.
 Timing and control requirements.
 Need to detect physical events – e.g., mouse clicks or keypresses
 Need for error detection and correction.
 To resolve these problems the computer system, include special hardware circuits between
CPU & peripherals. These are called as interface unit. Each device has its own interfacing
unit.
 The purpose of communicational link is to solve the following problems:

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 Peripherals are electromechanical devices but CPU & memory are pure electronic
devices.
 Data transfer rate is slower than that of CPU, so synchronization mechanism is
required.
 Data codes and formats of peripheral devices different from the word format of CPU
and memory.
 Operating mode of peripheral is different from each other. Each other must be
controlled, so that it will not disturb the operation of others.

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