MDULE: III

INTERRUPTS, TIMERS, SERIAL COMMUNICATION.

Interrupt is a mechanism to put on hold, the normal program flow, execute a subroutine and then
resume normal program flow. This sub routine called Interrupt Sub Routine (ISR) or interrupt handler is
executed only when a certain event (interrupt) occurs. This event may be generated by internal chip
operation or provided by external sources

8051 supports five vectored interrupt sources. Three of these are generated automatically
by internal operations. They are
(1) Timer 0 interrupt
(2) Timer 1 interrupt and
(3) Serial COM interrupt

Two interrupts are triggered by external signals provided by circuitry connected to the
corresponding interrupt pins and are

(1) External hardware interrupt 0 and

(2) External hardware interrupt 1

Table below lists the name, flag, vector address and pin number of all interrupts in 8051

Interrupt Flag Vector address Pin

Reset 0000H 9
External interrupt 0 IE0 0003H 12
Timer 0 interrupt TF0 000BH
External interrupt 1 IE1 0013H 13
Timer 1 interrupt TF1 001B
Serial COM interrupt RI/TI 0023

LEVEL VS EDGE TRIGGERED INTERRUPTS

There are two interrupt triggering methods supported for external interrupts in 8051.
1.Level-triggered interrupts and
2.Edge –triggered interrupts
The Edge/ Level-triggered method can be activated by setting / clearing the interrupt type
control bit of the concerned interrupts in the TCON register

Level-triggered interrupts
In the level triggered mode, the external interrupt pins (INT0 and INT1) are normally high
and the processor merely samples the input signal at every instruction cycle and if it sees low
(logic 0) it triggers the interrupt. The 8051 will hold the interrupt signal until the routine can be
vectored to and completed as signaled by the execution of RETI instruction.
The level- triggered interrupt method is desired in situations in which the input signal is not
freed by the hardware device requesting the interrupt until sometime after service the interrupt
 Edge- triggered interrupts
An edge triggered interrupt is caused by a high to low transition in the input signal. As in
the case of level triggered interrupts, the signal is sampled once every instruction cycle. This
method of interrupt triggering is useful for devices that will not pull the signal back to logic
level one immediately upon being serviced. Here the input signal at INT pin must return to a
logic level one to cause another interrupt in the system

INTERRUPT ENABLE (IE) REGISTER

Upon reset all interrupts in microcontroller are disabled. The SFR called Interrupt Enable
(IE) register allows the programmer to enable interrupts as needed. The lower 7 bits (D0-D6) of
this register are used to enable /disable the specific interrupt, whereas the 7th bit (EA) is used to
enable or disable all interrupts. This bit acts as a master control bit for any of the interrupts. To
enable any particular interrupt bit EA and the corresponding interrupt bit art to set
Fig shows the IE register and its bit assignments

Bit Symbol Function

IE.7 EA Enable interrupts bit. Cleared to 0 to disable all interrupts. Set to 1 to permit individual
interrupts to be enabled
IE.6 - Not implemented
IE.5 ET2 Enable timer 2 overflow interrupt. Set to 1 to enable. Clear to 0 to disable (for 8052)
IE.4 ES Enable serial port interrupt. Set to 1 to enable. Clear to 0 to disable
IE.3 ET1 Enable timer 1 overflow interrupt. Set to 1 to enable. Clear to 0 to disable

IE.2 EX1 Enable external interrupt 1. Set to 1 to enable. Clear to 0 to disable

IE.1 ET0 Enable timer 0 overflow interrupt. Set to 1 to enable. Clear to 0 to disable

IE.0 EX0 Enable external interrupt 0. Set to 1 to enable. Clear to 0 to disable

INTERRUPT PRIORITY
When more than one interrupts are enabled. User can program the interrupt priority levels by
setting or clearing the bits in the SFR called Interrupt Priority (IP) register. Each interrupt sources can
individually set to one of two priority levels. If the pin corresponding to an interrupt source is set, it will
have high priority. Similarly, if the bit is cleared the interrupt will be of low priority and subject to being
interrupted by any high priority interrupts. Fig shows the IP register and its bit assignments
 Bit Symbol Function

IP.7 - Reserved for future use

IP.6 - Reserved for future use

IP.5 PT2 Timer2 overflow interrupt priority level (for 8052)

IP.4 PS Serial port interrupt. Set to 1 to enable. Clear to 0 to disable

IP.3 PT1 Timer1 overflow interrupt priority level

IP.2 PX1 External interrupt1 priority level

IP.1 PT0 Timer0 overflow interrupt priority level

IP.0 PX0 External interrupt0 priority level

STEPS IN INTERRUPT PROCESSING

When an interrupt event occurs, the microcontroller executes the following sequence of steps
1. The CPU completes execution of the instruction in progress
2. The address of the next instruction present in the
program counter is stored in to stack memory
3. The current status of the interrupts are internally saved by the CPU
4. The CPU suspends normal code execution and the program branches to preset memory location
called interrupt vector address
5. The interrupt flag corresponding to the interrupt source is cleared by the hardware
6. The CPU executes the interrupt service subroutine that is located at the interrupt vector address
7. Upon executing a RETI instruction that usually signifies the end of the interrupt subroutine, the CPU
restores the contents of the program counter from the stack
8. The CPU thus branches back to the program address location from where it branched off when
interrupt event occurred and continue execution from the next instruction onwards

TIMERS IN 8051
There are many microcontroller applications which require real time operations such as pulse
counting, frequency measurement, pulse width measurement, baud rate generation etc. All these tasks can
be done through software techniques. But software loops for these tasks will keep the processor encaged,
so that other important functions during this time will not be carried out. To relieve the processor of this
burden, two 16-bit up counters called Timer0(T0) and Timer1 (T1) are provided in 8051 microcontrollers.
Both of these counters can be configured as timer or counters independently.
A timer counts the internal clock pulses by incrementing the counter register (T0/T1) on every
machine cycle and provides a reference time delay or a clock. Since a machine cycle consists
of 12 oscillator periods, the counting rate is 1/12 of the oscillator frequency. ie at oscillator frequency of
12MHz, the clocking period will be equal to 1us.
A counter counts external pulses and increments the register in response to a transition from ‘1’
to ‘0’ at its corresponding external input pin (T0/T1). Thus, the counter output will be a count or number
representing the occurrence of such ‘1’ to ‘0’ transitions at the external input pin. For counting function
,8051 takes two machine cycles (24 oscillator periods) to detect a ‘1’ to ‘0’ transition at pin T 0 (P3.4) or
T1(P3.5)
When a timer or counter overflows from FFFF H to 0000 H, it sets a flag and generates an interrupt.
The 16-bit registers of timers are divided in to two 8-bit registers and are referred to as higher
byte (TH0/TH1) and the lower byte (TL0/TL1). The action of counter is controlled by the bit status in the
special function registers TMOD (Timer Mode control) and TCON (Timer/Counter Control) registers and
some program instructions.

Timer Mode control (TMOD) register

TMOD register is a special function register used to control the mode of operation of both timers. This
register is an 8 bit register with two similar nibbles. The upper nibble (bits 4 through7) contains the
configuration bits for Timer1 and the lower nibble (bits 0 through 3) has the configuration bits for Timer0.
The detailed description on TMOD register is given below

Bit Symbol Function

TMOD.7 GATE OR gate enable bit: When set to1timer/counter is enabled only
TMOD.3 while
INT0/1 pin is high and TR0/1 in TCON register is set. When
cleared to 0 timer is enabled whenever TR0/1 control bit is
set.
TMOD.6 T/C
C/T: Timer/Counter selector: Cleared for Timer operation (input
TMOD.2 from internals system clock), Set for Counter operation (input
fromT0/T1 input pins)
TMOD.5&TMOD.4 M1& M0 Timer/Counter mode selection bits1/0: Set/ cleared to select the
TMOD.1&TMOD.0 mode as given below
M1 M0 MODE
0 0 0
0 1 1
1 0 2
1 1 3
Timer Control (TCON) register
Timer Control (TCON) register is also an 8-bit special function register used to control and
monitor the two timers. The upper nibble of TCON has control bits and flags for the timers. The lower
nibble represents control bits and flags for the external interrupt. The bit position and their functions of
TCON register is shown in fig below

Bit Symbol Function

TCON.7 TF1 Timer1 overflow flag: Set when timer/counter overflows, cleared to halt timer1
TCON.6 TR1 Timer1 run control bit: Set to enable timer1 to count, cleared to halt timer1
TCON.5 TF0 Timer0 overflow flag: Set when timer/counter overflows, cleared when processor
execute interrupt service routine
TCON.4 TR0 Timer0 run control bit: Set to enable timer0 to count, cleared to halt timer0
TCON.3 IE1 External interrupt1 edge flag: Set when a high to low edge signal is received
on PinINT1(P3.3). cleared when processor vectors to interrupt service routine
TCON.2 IT1 External interrupt1 signal type control bit: Set to enable External interrupt 1 to
be edge triggered, cleared to enable External interrupt 1 to be level triggered
TCON.1 IE0 External interrupt 0edge flag: Set when a high to low edge signal is received on
Pin INT0(P3.2). cleared when processor vectors to interrupt service routine
TCON.0 ITO External interrupt0 signal type control bit: Set to enable External interrupt 0 to
be edge triggered, Cleared to enable External interrupt 0 to be level triggered

Timer/Counter control Logic

Timer/Counter in 8051 are controlled by TR1/0 bits in TCON, GATE bits in TMOD and INT1/0
input pins of 8051. The C/T pin in the TMOD register selects between the external pinT0/1 and the internal
clock frequency divided by 12. This input signal is then gated by a combination of TR0/1, GATE and the
INT0/1 pin.
The counter counts the selected input signal if TR0/1 is high along with GATE being low or
INT0/1 pin being high. This is illustrated in fig above
TIMER/COUNTER MODES
Timers can be operated in four different modes determined by the mode bits M1 andM0 in the
TMOD register

MODE0:

In this mode timer operates as a 13 bit up-counter in a way, the lower 5bits are in the TL0/1 and
the upper 8bits in TH0/1 register. Here TL0/1 will count from 0 to 31. When it is incremented from 31, it
will reset to 0 and increment TH0/1. Thus, effectively only 13 bits (bits 0-4 of TL0/1 and bits 0-7 of TH0/1)
of the timer bytes are being used. The timer interrupt flag TF0/1 bit is set, when the counter rolls over from
FF H to 00h. This bit can then be used to interrupt the 8051. Fig.above illustrates the timer operation in
mode0

MODE1:
This mode is exactly similar to mode0, but the counter is16 bits with lower byte in TL0/1 and the upper
byte in TH0/1. All other functions are similar to mode 0

MODE2:

Mode2 is the auto reload mode. In this mode the counter work as an 8bit counter in TL0/1.Here
TH0/1is used to hold a value that is loaded in to TL0/1. When the counter rolls over from FF H to 00H the
interrupt flag TF0/1 is set and the counter TL0/1 is reloaded automatically with the value in TH0/1. This
mode is useful to divide the input clock frequency to the counter by a preset value
MODE3:

Timer mode3 is a split-timer mode. In this mode the timer0 and timer1 don’t operate independently,
if mode3 is chosen for timer0. Timer1in mode3 just hold its current count. The control bit TR1 and the
timer flag TF1 are then be used by timer 0. Timer0 in mode3 functions as two independent counters .TL0
as an 8bit counter that counts the internal clock/12 or external events as represented in fig. The roll over of
TL0 from FFH to 00h sets the TF0 flag. This flag can then be used to interrupt the processor if required.
TH0 is an independent 8bit counter that counts 1./12 the clock frequency and is gated by TR1. Roll over
of this counter sets theTF1 flag which can also be used to interrupt the processor.

Time delay Calculation

A timer counts the internal clock pulses by incrementing the counter register (T0/T1) on every
machine cycle. In 8051 one machine cycle consists of 6 states or 12 clock cycles. Therefore, time to
increment the timer count by one (timer tick) can be determined as below.

Tick = (1/(Fosc/12)
= 12/Fosc
If the clock frequency (crystal frequency) is 12MHz
Tick = 12/12x10-6
= 1us

Now the Timer value for the required delay can be calculated using following steps
1.Calculate the tick value as 12/Fosc
2.Ddevide the desired time delay by tick value to get the count (n) required for the delay
3.Perform 65536-count(n) to get the timer value in decimal
4.Convert the result of step3 to Hex
5.Load the lower byte of the Hex value obtained in step 4 into lower byte of Timer (TL) and higher byte of
the Hex value into higher byte of timer (TH)

Here the time delay calculation using mode1(16-bit) can be done using the formula
T= (65536-NNNN)x Tick
Where NNNN is the decimal value obtained in step 3
Example: The value to be loaded into timer registers operating in mode1 to get a time delay of 5ms using
12Mhz crystal can be calculated as follows

Tick = 12/Fosc = 12/12x10-6 = 1us

Count value n = 5ms/1us = 5x10-3 /1x10 = 5000
Timer value in decimal = 65536-5000 = 60536
Timer value in Hex = EC78H
ie TL= 78H TH= ECH

SERIAL COMMUNICATION IN 8051

Communication with the outer devices through parallel port is possible through an 8-bit data bus.
This can work only if the cable is not too long since long cable diminish and distort signals. Arranging 8-
bit data cable to long distances is also expensive. For these reasons serial communication is used for
transferring data between two devices located far apart since this method requires only a single data line
instead of the 8-bit data cable
The basic mechanism of serial transmission is that data byte in parallel form is converted into serial
data stream using a parallel- in- serial out shift register. Then it is transmitted over a single data line. At the
receiving end the received data bits are packed to the byte form by using serial-in-parallel out shift registers.

Baud rate
Baud rate is a term to represent the rate of data transfer in serial communication. It is the number
of signal changes per second and is the reciprocal of the time to send one bit. Baud rate need not be equal
to the number of bits per second. This is because each data byte may consist few additional bits like start
and stop etc

SYNCHRONOUS AND ASYNCHRONOUS COMMUNICATION

Serial data communication uses two methods of communication
1.Synchronous communication and
2.Asynchrounous communication

In synchronous method a clock signal ( a pulse stream of logic low and high level at a fixed high
frequency) is transmitted as the control signal . The data bits are transmitted/received with reference to
the edges of the clock signal. All data transfer is thus synchronized to this clock. High speed of
communication is possible through this method. Synchronous serial data communication method is used
for block-oriented data transmission
In asynchronous communication no clock pulses are transmitted to synchronize the data transfer.
Here the data transfer takes place based on internal clock pulses. Thus, the interface lines between
communicating devices carry only data signals. The sender and receiver should be synchronized to the same
clock frequency. Asynchronous serial data communication method is used for character -oriented data
transmission

SIMPLEX AND DUPLEX-TRANSMISSION

Simplex transmission is the system in which only data transmission is possible. In duplex
transmission data can be transmitted and received. Duplex transmission can be half duplex or full duplex.
If data is transmitted one way at a time it is referred to as half duplex. If data is transmitted and received at
the same time the system is called full duplex. Full duplex system requires two wire conductors for the data
lines (one for transmission and other for reception) in order to transmit and receive data simultaneously
SERIAL COMMUNICATION IN 8051
The 8051 features an on-board full duplex Universal Asynchronous Receiver Transmitter (UART).
It is also receive buffered, meaning that it can commence reception of second byte before a previously
received byte has been read from the receive register. The 8051 serial communication is supported by
RS232 (Recommended Standard). The serial port can send and receive data simultaneously using two data
lines TXD and RXD. TXD is the serial transmit pin and RXD is the serial receive pin.

SBUF Register
It is an 8-bit register used solely for serial communication in 8051. For a byte of data to be
transferred via TxD line, it must be placed in SBUF register (Transmit). Similarly, SBUF
register(receive) holds the serially inputted data received by RxD line of 8051. All though the
name is SBUF for both transmit and receive register; they are two independent registers with the
same name. The receive buffer SBUF is read only and cannot be written into. The transmit buffer
SBUF is write only and cannot be read. All read instruction to SBUF will access the receive register
and all write instruction to SBUF will access the transmit register
The moment the byte is written in SBUF, it is framed with start and stop bits and
transferred serially through TxD line.
Similarly, when bits are received serially via RxD it is de-framed by eliminating stop and start
bits and a byte of data is received and placed in SBUF

SERIAL PORT CONTROL (SCON)REGISTER

The operation of the serial communications module is controlled by the Serial port Control
Register (SCON). Fig below shows the SCON register and its bit assignments

Bit Symbol Function

SCON.7 SM0 Serial port mode bit 0:
SCON.6 SM1 Serial port mode bit 1:
Serial port mode can be set using of SM0 and SM1as follows
SM 0 SM 1 Mode
0 0 0
0 1 1
1 0 2
1 1 3
SCON.5 SM2 Mul processor communica on bit: Set/Cleared to enable mul processor
communica on in mode 2
SCON.4 REN Receive enable bit:. set to one to enable recep on, cleared to 0 to disable recep on
SCON.3 TB8 Transmi ed bit 8: Set/cleared by program in mode2&3
SCON.2 RB8 Received bit 8:. Bit8 of received data in mode 2&3, stop bit in mode 1; not
used in mode 0
SCON.1 TI Transmit interrupt flag: Set to one by hardware at the end of the 8th bit me in mode
0, or at the beginning of the stop bit me in other modes. Must be cleared by
so ware.
SCON.0 RI Receive interrupt flag: Set to one by hardware at the end of the 8 th bit time in
mode 0, or halfway through the stop bit time in other modes. Must be cleared
by the software

POWER CONTROL REGISTER (PCON)

The PCON register is an 8-bit register. Of the 8-bits only 5 bits are used.. Fig. below shows the
PCON register and its bit assignments

Bit Symbol Function

PCON.7 SMOD Serial baud rate modify bit: Set to 1 by the program to double the baud rate
using Timer 1 for Modes 1,2&3 Cleared to 0 to use Timer1 baud rate
PCON.6 - Reserved
PCON.5 - Reserved
PCON.4 - Reserved
PCON.3 GF1 General purpose user Flag1: Set/Cleared by the program
PCON.2 GF0 General purpose user Flag0: Set/Cleared by the program
PCON.1 PD Power Down bit: Set to 1 by the program to enter Power Down mode
configuration
PCON.0 IDL Idle mode bit: Set to 1 by the program to enter Idle mode configuration

SERIAL COMMUNICATION MODES

The serial port provides both synchronous and asynchronous communication modes. The 8051
provides four programmable modes for serial communication. A particular mode can be selected by setting
the SM0 and SM1 bits in SCON register. The mode selection also decides the baud rate. It operates as a
UART in three full-duplex modes (Modes 1,2 and 3). Asynchronous transmission and reception can occur
simultaneously at different baud rate

MODE 0

In mode 0 it acts as an 8bit shift register clocking data in and out at a baud rate of
1/12 of the oscillator frequency. Here eight data bits are transmitter in LSB first fashion. In this mode of
operation pin RXD is used for transmission as well as reception of the data. Whereas pin TXD is used to
provide the shift clock. Therefore mode 0 doesn’t support full duplex operation
This mode is useful for situations in which the microcontroller is used to interface to a serial device
such as an EEPROM that has a serial eight-bit interface format
MODE1

In mode 1 eight data bits are transmitted in a ten-bit frame: one start bit, eight data bits and one
stop bit as shown in fig. Here bits are transmitted through TXD pin and received through RXD pin. The
baud rate in this mode is variable and is controlled by the overflow rate of timer 1 in the auto reload mode.
This mode is suitable for communication with most serial devices including personal computers.

MODE2

Mode 2 operation causes data bits to transmit in an 11 bit frame as a low start bit, 8 data bits, a 9th
bit and a stop bit as shown in fig . user can define 9th bit with TB8 bit of SCON register for transmission
and RB8 bit of the SCON register for reception. The 9th bit is typically used for inter processor
communications. In mode 2, the baud rate is defined by the bit SMOD in PCON and the oscillator
frequency. the baud rate is 1/64 of the oscillator frequency when SMOD bit is cleared and is 1/32 of the
oscillator frequency when SMOD bit is set

MODE3
As in the case of mode 2, mode 3 also causes data transmission or reception in 11-bit frame through
pin TXD /RXD. In fact mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in
mode 3 is variable and is controlled by the overflow rate of timer 1 in the auto reload mode

Table: Serial communication in 8051

Mode Transmission format Baud rate

0 8-data bits 1/12 of oscillator frequency
1 10-bit (Start bit +8databits +Stop bit) Variable
2 11-bit (Start bit+8 data bit + Programmable 9th bit +Stop bit) Programmable to either1/32 or
1/64 of oscillator frequency
3 11-bit (Start bit +8databits +Programmable 9th bit +Stop bit) Variable

RS232 STANDARDS
To allow the compatibility among data communication equipment made by various manufactures,
an interfacing standard called RS232 was set by Electronics Industries Association (EIA). This standard is
used in PCs and numerous types of equipment. Since this standard is set long before the advent of TTL
logic family its input and output voltage levels are not TTL compatible. In RS232 a 1 (HIGH)is represented
by -3 Vto -25V, while a 0 bit is represented by +3V-+25V, making -3 V- +3V undefined. For this reason,
to connect any RS232 to a microcontroller system we must use a voltage converter to convert the TTL logic
level to RS232 voltage level and vice versa. MAX232 IC chips are commonly used IC chips for this
purpose.
RS232 Pins

The original RS232 cable DB-25 has 25 pins. But all these pins were not used in PC cables. due to
this reason IBM introduced the DB-9 version of the serial I/O standard, which uses only 9 pins as shown in
fig above. The pin description of DB-9 is given in table

RXD and TXD pins of the 8051

8051 has two port pins for serial communication as one for transmission and other for receiving
data serially. These pins are designated as TxD (Transmitter)and RxD (Receiver) and are part of the port 3
group (P3.0 and P3.1). Here pin 11of the 8051 (P3.1) is assigned to TxD and pin 10(P3.0) is designated as
RxD. These pins are TTL compatible; therefore, they require a line driver to make themRS232 compatible.
Max232 chip is one such driver

MAX232

The MAX232 has two sets of line drivers for transferring and receiving data as shown in fig above.
The line drivers used for TxD are called T1 and T2(, while the line drivers used for RxD are called R1 and
R2.Both RxD and TxD driver have input and output pins designated as T1 IN, T2IN, T1OUT, T2OUT for TxD
driver and R1IN , R2IN, R1OUT, R2OUT for RXD ddriver In many applications only one of each is used.
MAX232 requires four capacitors ranging from 0.1 to 22 uf to to provide more stable voltage. The most
widely used value for these capacitors is 22uf
8051 CONNECTION TO RS232

In connection of 8051 to RS232 T1 and R1 are used together for TxD and RxD and second is left
un used as shown in fig (b). Here the T1IN (pin11) of Max232 is connected to the TxD pin of the
microcontroller, while T1OUT (p in14) is connected to RxD pin of the RS232 DB connector. The R1IN (pin13)
of Max232 is connected to the TxD pin of the RS232 DB connector., while R1 OUT (pin12) is connected to
RxD pin of the micro controller