AN5373

Application note

Getting started with STM32U5 MCU hardware development

Introduction
This application note is intended for system designers who require a hardware implementation overview of the development
board features: power supply, clock management, reset control, boot mode settings, and debug management.
It details how to use the STM32U5 series microcontrollers (named STM32U5) and describes the minimum hardware resources
required to develop an application using these MCUs.
This document also includes detailed reference design schematics with the description of the main components, interfaces, and
modes.

AN5373 - Rev 6 - September 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 AN5373
General information

1 General information

This document applies to the STM32U5 series Arm® Cortex®‑M33‑based microcontrollers.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Reference documents

[1] Reference manual STM32U5 series Arm®-based 32-bit MCUs (RM0456)

[2] Application note STM32 microcontroller system memory boot mode (AN2606)
[3] Application note Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs (AN2867)
[4] Application note STM32 MCUs secure firmware install (SFI) overview (AN4992)

AN5373 - Rev 6 page 2/47

 AN5373
Power supply management

2 Power supply management

2.1 Power supplies

The STM32U5 devices require a 1.71 to 3.6 V operating voltage supply (VDD).
The independent supplies listed below, can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator, and the system analog such as reset,
power management, and internal clocks. VDD is provided externally through the VDD pins.
• VDDA = 1.62 V (ADCs/COMPs/DACs/OPAMPs) / 1.8 V (VREFBUF) to 3.6 V
VDDA is the external-analog power supply for A/D converters, D/A converters, voltage reference buffer,
operational amplifiers, and comparators. The VDDA voltage level is independent from the VDD voltage. The
VDDA pin must preferably be connected to the VDD voltage supply when these peripherals are not used.
Note: In case the VDDA pin is left at high impedance or is tied to VSS, the maximum input voltage that can be
applied on the I/Os with "_a" I/O structure, is reduced (refer to device datasheet for more details).
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step-down converter. It is provided externally through
the VDDSMPS pin, and must be connected to the same supply as VDD pin when the SMPS is used in the
application. When the SMPS is not used, it is recommended to connect both VDDSMPS and VLXSMPS to
ground.
• VLXSMPS
The VLXSMPS pin is the switched SMPS step-down converter output.
Note: The SMPS output can not be used to power external components.
• VDD11
VDD11 is a digital core supply provided through the internal SMPS step-down converter VLXSMPS pin.
VDD11 pins (two or three) are present only on packages with internal SMPS, connected to a total of 4.7 µF
(typical) external capacitors.
• VCAP
VCAP is the digital core supply, from the internal LDO regulator. VCAP pins (one or two) are present only on
packages with LDO only (without SMPS), connected to a total of 4.7 µF (typical) external capacitor.
Note: – In case there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF
capacitor, for a total around 4.4 µF.
– The SMPS power supply pins (VLXSMPS, VDD11, VDDSMPS, VSSSMPS) are available only on
packages with SMPS. In such packages, the STM32U5 devices embed two regulators, one LDO
and one SMPS in parallel, to provide the VCORE supply to digital peripherals. A 4.7 μF total external
capacitor and a 2.2 µH coil are required on VDD11 pins.
– The flash memory is supplied by VCORE and VDD.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external-independent power supply for USB transceivers. The VDDUSB voltage level is
independent from the VDD voltage. The VDDUSB pin must preferably be connected to the VDD voltage
supply when the USB is not used.
Note: In case the VDDUSB pin is left at high impedance or is tied to VSS, the maximum input voltage that can
be applied on the I/Os with "_u" I/O structure, is reduced (refer to device datasheet for more details).
• VDD11USB = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDD11USB is the external power supply for the USB transceiver. This supply is only available on specific
packages and must be connected to VDD11.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level is independent
from the VDD voltage, and must preferably be connected to VDD when PG[15:2] is not used.
Note: On small packages, VDDA, VDDIO2, or VDDUSB independent power supplies may not be present as a
dedicated pin, and are internally bonded to a VDD pin. They are neither present when the related features
are not supported on the product.

AN5373 - Rev 6 page 3/47

 AN5373
Power supplies

• VBAT = 1.55 V to 3.6 V

VBAT is the power supply when VDD is not present (through power switch) for RTC, TAMP, external clock
32 kHz oscillator, backup registers, and optionally backup SRAM.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage
reference buffer (VREFBUF) when enabled. The VREF+ pin can be grounded when ADC and DAC are not
active.
The internal voltage reference buffer supports four output voltages that are configured with the VRS[2:0]
field in VREFBUF_CSR register:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
– VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.
– VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.
– VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA
and VDDA pins, respectively.
When the VREF+ pin is double-bonded to VDDA in a package, the internal VREFBUF is not available, and
must be kept disabled.
VREF- must always be equal to VSSA.
• VDDDSI = 1.71 V to 3.6 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDDDSI is the external power supply for the DSI controller. It is provided externally through the VDDDSI
supply pin, and must be connected to the same supply as VDD pin.
• VDD11DSI = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDD11DSI is the external power supply for the DSI transceiver and must be connected to VDD11.
The following figures present an overview of the STM32U5 devices power supply, depending on the SMPS
presence.

AN5373 - Rev 6 page 4/47

 AN5373
Power supplies

Figure 1. STM32U535xxxxQ and STM32U545xxxxQ power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL
VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wake-up logic, IWDG)
SRAM1
VDD SRAM2
Voltage regulator SRAM4
LDO regulator VCORE Digital
2x VDD11 peripherals
VLXSMPS SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
VBAT VSW LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers

DT70511V2
RTC
TAMP
BKPSRAM

AN5373 - Rev 6 page 5/47

 AN5373
Power supplies

Figure 2. STM32U535xx and STM32U545xx power supply overview (without SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temperature sensor
3 x PLL Core
VSS Internal RC oscillators
SRAM1
SRAM2
Standby circuitry
SRAM4
VDD (Wake-up logic, IWDG)
VCORE Digital
peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
LSE crystal 32 kHz oscillator
VSW
VBAT LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP

DT70512V2
BKPSRAM

AN5373 - Rev 6 page 6/47

 AN5373
Power supplies

Figure 3. STM32U575xQ and STM32U585xQ power supply overview (with SMPS)

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wake-up logic, IWDG) SRAM1
VDD SRAM2
Voltage regulator SRAM3
SRAM4
LDO regulator VCORE
2x VDD11 Digital
VLXSMPS peripherals
SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
VBAT VSW LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register

DT63604V2
RTC
TAMP
BKPSRAM

AN5373 - Rev 6 page 7/47

 AN5373
Power supplies

Figure 4. STM32U575xx and STM32U585xx power supply overview (without SMPS)

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
(Wake-up logic, IWDG) SRAM4
VDD
VCORE
VCAP Digital
peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
VSW LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register

DT64350V2
RTC
TAMP
BKPSRAM

AN5373 - Rev 6 page 8/47

 AN5373
Power supplies

Figure 5. STM32U5F/5G/59/5AxxxxxQ power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
VDD11USB(1) USB transceiver
VSS
VDDDSI
VDD11DSI DSI transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators Core

Standby circuitry SRAM1

VSS
(Wake-up logic, IWDG) SRAM2
VDD SRAM3
Voltage regulator SRAM4
SRAM5
LDO regulator (2)
VCORE SRAM6
2x or 3x VDD11
VLXSMPS SMPS regulator
Digital
VDDSMPS peripherals
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
VBAT VSW LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
DT70551V2

RTC
(1) Only available on specific packages. TAMP
(2) Only for STM32U5Fx/5Gx devices. BKPSRAM

AN5373 - Rev 6 page 9/47

 AN5373
Power supplies

Figure 6. STM32U5F/5G/59/5Axxx power supply overview (without SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
VDD11USB(1) USB transceiver
VSS

VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators
SRAM1
SRAM2
SRAM3
Standby circuitry SRAM4
VDD (Wake-up logic, IWDG) SRAM5
(2)
VCORE SRAM6
VCAP
Digital
LDO regulator
peripherals

Flash memory
Low-voltage detector

Backup domain
VSW LSE crystal 32kHz oscillator
VBAT LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC

DT66058V2
(1) Only available on specific packages. TAMP
(2) Only for STM32U5Fx/5Gx devices. BKPSRAM

In devices without SMPS, the VDD supply source feeds the I/Os and system analog peripherals (such as PLLs
and reset block). The VCORE power supply for digital peripherals and memories is generated from the LDO.
Note: If the selected package has the SMPS step-down converter option but the SMPS is not used by the application
(and the embedded LDO is used instead), the SMPS power supply pins must be set as follows:
• VDDSMPS and VLXSMPS connected to VSS
• VDD11 pins connected to VSS through two 2.2 µF capacitors as in normal mode

2.1.1 Independent analog peripherals supply

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have
an independent power supply that can be separately filtered and shielded from noise on the PCB.
The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply
ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. After reset, the analog peripherals supplied by VDDA are
logically and electrically isolated and therefore are not available. The isolation must be removed before using
these peripherals, by setting the ASV bit in PWR_SVMCR, once the VDDA supply is present.
The VDDA supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds
(1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section Peripheral voltage
monitoring (PVM) of document [1].
When a single supply is used, the VDDA pin can be externally connected to the same VDD supply, through an
external filtering circuit, to ensure a noise-free VDD reference voltage.

AN5373 - Rev 6 page 10/47

 AN5373
Power supplies

ADC and DAC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate
reference voltage lower than VDDA.
VREF+ is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC)
signal. VREF+ can be provided either by an external reference or by the VREFBUF that can output a configurable
voltage: 1.5, 1.8, 2.048 or 2.5 V. The VREFBUF can also provide the voltage to external components through the
VREF+ pin.
For further information, refer to the device datasheet and section Voltage reference buffer (VREFBUF) of
document [1].

2.1.2 Independent I/O supply rail

Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can
range from 1.08 V to 3.6 V, and is provided externally through the VDDIO2 pin. The VDDIO2 voltage level is
completely independent from VDD or VDDA.
The VDDIO2 pin is available only for some packages (refer to the pinout details in the datasheet for the I/O list).
After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and are therefore not available.
The isolation must be removed before using any I/O from PG[15:2], by setting the IO2SV bit in PWR_SVMR, once
the VDDIO2 supply is present.
The VDDIO2 supply is monitored by the VDDIO2 voltage monitoring (IO2VM) and compared with the internal
reference voltage (3/4 VREFINT, around 0.9 V).
For more details, refer to the device datasheet and section Peripheral voltage monitoring (PVM) of document [1].

2.1.3 Independent USB transceiver supply

The USB transceivers are supplied from a separate VDDUSB power supply. VDDUSB range is from 3.0 V to 3.6 V
and is completely independent from VDD or VDDA.
After reset, the USB features supplied by VDDUSB are logically and electrically isolated, and are therefore not
available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the
PWR_SVMR register, once the VDDUSB supply is present.
The VDDUSB supply is monitored by the USB voltage monitoring (UVM) and compared with the internal reference
voltage (VREFINT, around 1.2 V). For more details, refer to the device datasheet and section Peripheral voltage
monitoring (PVM) of document [1].
For STM32U59x/5Ax/5Fx/5Gx devices only, the USB high-speed transceiver can be supplied from an optional
power supply VDD11USB. VDD11USB range is from 1.0 V to 1.26 V and must be connected to VDD11.

2.1.4 Battery backup domain

To retain the content of the backup registers and supply the RTC when VDD is turned off, the VBAT pin can be
connected to an optional backup voltage, supplied by a battery or by another source.
The VBAT pin powers RTC, TAMP, LSE oscillator, and PC13 to PC15 I/Os. That allows the RTC to operate even
when the main power supply is turned off.
The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in PWR_BDCR1.
The switch to the VBAT supply is controlled by the power-down reset embedded in the reset block.
Caution: • During tRSTTEMPO (at VDD startup) or after a PDR (power-down reset) detection, the power switch
between VBAT and VDD remains connected to the VBAT pin.
• During the startup phase, if VDD is established in less than tRSTTEMPO (refer to the datasheet for
tRSTTEMPO value), and VDD > VBAT + 0.6 V, a current may be injected into the VBAT pin through an
internal diode connected between the VDD pin and the power switch (VBAT). If the power supply/battery
connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an
external low-drop diode between this power supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin externally to VDD with
a 100 nF external ceramic decoupling capacitor.

AN5373 - Rev 6 page 11/47

 AN5373
Power supplies

When the backup domain is supplied by VDD (analog switch connected to the VDD pin), the following pins are
available:
• PC13, PC14, and PC15 that can be used as GPIO pins
• PC13, PC14, and PC15 that can be configured by RTC or LSE (refer to the RTC section of document [1])
• Pins listed below, that are configured by TAMP as tamper pins:
– PE3 (TAMP_IN6/TAMP_OUT3)
– PE4 (TAMP_IN7/TAMP_OUT8)
– PE5 (TAMP_IN8/TAMP_OUT7)
– PE6 (TAMP_IN3/TAMP_OUT6)
– PC13 (TAMP_IN1/TAMP_OUT2)
– PA0 (TAMP_IN2/TAMP_OUT1)
– PA1 (TAMP_IN5/TAMP_OUT4)
– PC5 (TAMP_IN4/TAMP_OUT5)
Note: • Because the power switch can transfer only a limited amount of current (3 mA), the use of PC13 to PC15
I/Os in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF.
These I/Os must not be used as current source (for example to drive an LED).
• Under VDD, TAMP_OUTx pins (PE3, PE4, PE5, PE6, PA0, PA1, PC5) keep the same speed features as
the GPIOs to which they are connected. However, under VBAT, the speed of TAMP_OUTx pins must be
limited to 500 kHz.
• The speed of the PC13 pin is always limited to 2 MHz, under VDD or under VBAT.

Backup domain access

After a system reset, the backup domain (RCC_BDCR, PWR_BDCR1, RTC, TAMP and backup registers, plus
backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bit RCC_AHB3ENR.
2. Set the DBP bit in PWR_DBPR to enable access to the backup domain.

VBAT battery charging

When VDD is present, the external battery can be charged on VBAT through an internal resistance, 5 kΩ, or
1.5 kΩ, depending on the VBRS bit in PWR_BDCR2.
The battery charging is enabled by setting VBE bit in PWR_BDCR2. It is automatically disabled in VBAT mode.

2.1.5 Voltage regulator

The STM32U5 devices embed the following internal regulators in parallel to provide the VCORE supply for digital
peripherals, SRAMs, and the embedded flash memory:
• SMPS step-down converter
• LDO (linear voltage regulator)
They can be selected when the application runs, depending on the application requirements. The SMPS allows
the power consumption to be reduced. However, the noise generated by the SMPS may impact some peripheral
behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best
performances.
Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges
(range 1/2/3/4), in all Stop modes (Stop 0/1/2/3), and in Standby mode with SRAM2. Refer to the low-power mode
summary table in document [1].
On some packages, the SMPS supply pins are not available, consequently only the LDO might be used to supply
VCORE domain.

AN5373 - Rev 6 page 12/47

 AN5373
Power supply schemes

Dynamic Voltage scaling management

Both LDO and SMPS regulators can provide four different voltages (voltage scaling) and can operate in all Stop
modes. Both regulators also can operate in the following ranges:
• Range 1 (1.2 V, 160 MHz), high performance: provides a typical output voltage at 1.2 V. It is used when the
system clock frequency is up to 160 MHz.
• Range 2 (1.1 V, 110 MHz), medium-high performance: provides a typical output voltage at 1.1 V. It is used
when the system clock frequency is up to 110 MHz.
• Range 3 (1.0 V, 55 MHz), medium-low power: provides a typical output voltage at 1.0 V. It is used when the
system clock frequency is up to 55 MHz.
• Range 4 (0.9 V, 24 MHz), low power: provides a typical output voltage at 0.9 V. It is is used when the
system clock frequency is up to 24 MHz.
Voltage scaling is selected through the VOS[1:0] field in PWR_VOSR.
Caution: The EPOD (embedded power distribution) booster must be enabled and ready before increasing the system
clock frequency above 50 MHz in Range 1 and Range 2 (refer to document [1] for sequences to switch between
voltage scaling ranges).

2.1.6 Power supply for I/O analog switches

Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch sensing
controller) functions. These switches are by default supplied by VDDA. However, they can be supplied by a VDDA
voltage booster or by VDD, depending on the configuration of ANASWVDD and BOOSTEN bits in
SYSCFG_CFGR1.
It is recommended to supply the I/O switches with the highest voltage value between VDDA, VDDA booster,
and VDD.
Note: If possible, select VDDA or VDDA booster rather than VDD, as they are often less noisy.
The analog switches for TSC function are supplied by VDD.

2.2 Power supply schemes

The device is powered by a stabilized VDD power supply as described below:
• VDD pins must be connected to VDD with external decoupling capacitors: a 10 μF (typical value, 4.7 µF
minimum) single tantalum or ceramic capacitor for the package, and a 100 nF ceramic capacitor for each
VDD pin.
• VDD11 pins are present only on packages with SMPS. The SMPS step-down converter requires a 2.2 μH
(typical) external ceramic coil connected between VLXSMPS and VDD11 pins. In addition, two 2.2 μF
capacitors on VDD11 pins are connected to the VSSSMPS pin.
• The VCAP pin is present only on standard packages (without SMPS). It requires a 4.7 µF (typical) external
decoupling capacitor connected to VSS. If there are two VCAP pins (UFBGA169 package), each VCAP pin
must be connected to a 2.2 µF (typical) capacitor (for a total around 4.4 µF).
• The VDDA pin must be connected to two external decoupling capacitors: 100 nF ceramic and 1 μF
tantalum or ceramic.
Additional precautions can be taken to filter digital noise: VDDA can be connected to VDD through a ferrite
bead.
• The VREF+ pin can be provided by an external voltage reference. In this case, an external 100 nF + 1 μF
tantalum or ceramic capacitor must be connected on this pin.
It can also be provided internally by the VREFBUF. In this case, an external 1 μF (typical) capacitor must
be connected on this pin.
• The VBAT pin can be connected to an external battery to preserve the content of the Backup domain:
– When VDD is present, the external battery can be charged on VBAT through a 5 kΩ or 1.5 kΩ
internal resistor. In this case, the user can insert a capacitor according to the expected discharging
time (1 µF is recommended).
– If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD
with a 100 nF external ceramic decoupling capacitor.

AN5373 - Rev 6 page 13/47

 AN5373
Power supply schemes

Figure 7. Power supply scheme for U535/545/575/585xxxxQ (with SMPS)

VBAT Backup circuitry

1.65 – 3.6 V
(LSE, RTC, TAMP,
backup registers,
3.3 V backup SRAM)
Power switch
VDDUSB
100 nF
VDD
VDDSMPS
Voltage regulator
10 µF
SMPS VCORE
VLXSMPS SMPS ON

2.2 µH
2 x VDD11
2 x 2.2 µF Kernel logic
VSSSMPS
SMPS OFF (CPU, digital
and memories)
VDD LDO
n x VDD

VDDIO1
OUT

Level shifter
IO
n x 100 nF GPIOs
IN
logic
+ 10 µF

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x100 nF OUT
Level shifter

+ 4.7 µF IO
GPIOs logic
IN
m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+ 1 µF OPAMPs/
100 nF+ 1 µF VREF- COMPs/
VREFBUF
DT64359V1

VSSA

AN5373 - Rev 6 page 14/47

 AN5373
Power supply schemes

Figure 8. Power supply scheme for STM32U535/545/575/585xx (without SMPS)

VBAT
Backup circuitry
1.65 – 3.6 V (LSE, RTC, TAMP
backup registers,
3.3 V backup SRAM)
VDDUSB
100 nF
VCAP Power switch

4.7 µF

VDD VCORE
n x VDD LDO
VCORE
regulator
VDDIO1
OUT Kernel logic

Level shifter
n x 100 nF I/O (CPU, digital
+ 1 x 10 µF GPIOs logic and
IN
memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x 100 nF OUT
Level shifter

+ 4.7 µF I/O
GPIOs logic
IN

m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+1 µF OPAMPs/
100 nF+ 1 µF VREF- COMPs/
VREFBUF DT64358V1

VSSA

Caution: If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF (typical) capacitor
(for a total around 4.4 µF).

AN5373 - Rev 6 page 15/47

 AN5373
Power supply schemes

Figure 9. Power supply scheme for STM32U5F/5G/59/5Axxx (with SMPS)

1.55 – 3.6 V VBAT Backup circuitry

(LSE, RTC, TAMP,
backup registers,
3.3 V
backup SRAM)
VDDUSB Power switch
100 nF
VDD
VDDDSI(2)
100 nF
VDDSMPS
Voltage regulator
10 µF
SMPS VCORE
VLXSMPS SMPS ON

2.2 µH
2 x VDD11
2 x 2.2 µF Kernel logic
VSSSMPS
SMPS OFF (CPU, digital
VDD11(1) and memories)
VDD11USB(1)
VDD11DSI(2)
VDD LDO
n x VDD

VDDIO1
OUT
Level shifter

n x 100 nF GPIOs IO
IN logic
+ 10 µF

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
Level shifter

m x100 nF OUT
IO
+ 4.7 µF GPIOs
IN
logic
m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/ (1) Only available on specific packages.
+ 1 µF OPAMPs/
VREF- COMPs/
(2) Only available on STM32U5x9 devices.
100 nF+ 1 µF
VREFBUF
DT69108V1

VSSA

AN5373 - Rev 6 page 16/47

 AN5373
Power supply schemes

Figure 10. Power supply scheme for STM32U5F/5G/59/5Axxx (without SMPS)

1.65 – 3.6 V VBAT

Backup circuitry
(LSE, RTC, TAMP,
VDDUSB backup registers,
VDDUSB backup SRAM)
Power switch
100 nF

VCAP
4.7 µF
VCORE
VDD
n x VDD LDO VCORE
regulator

VDDIO1
OUT

Level shifter
GPIOs I/O
IN logic Kernel logic
(CPU, digital
and memories)
n x VSS

VDDIO2
m x VDDIO2
VDDIO2
Level shifter

m x100 nF OUT
I/O
+ 4.7 µF GPIOs
IN
logic
m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+ 1 µF OPAMPs/
VREF-
DT71165V1

100 nF+ 1 µF COMPs/

VREFBUF

VSSA

Note: • SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on application
requirements. However, only one of them is active at the same time. When SMPS is active, it feeds the
VCORE on the two VDD11 pins provided through the SMPS VLXSMPS output pin. A 2.2 µH coil and a
2.2 μF capacitor on each VDD11 pin are then required. When LDO is active, it provides the VCORE and
regulates it using the same decoupling capacitors on VDD11 pins.
• It is recommended to add a decoupling capacitor of 100 nF near each VDD11 pin/ball, but it is not
mandatory.

AN5373 - Rev 6 page 17/47

 AN5373
Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD

2.3 Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD

2.3.1 Power supply isolation

The devices feature a powerful reset system that ensures the main power supply (VDD) has reached a valid
operating range before releasing the MCU reset.
This reset system is also in charge of isolating the independent power domains: VDDA, VDDUSB, VDDIO2, and VDD.
This reset system is supplied by VDD and is not functional before VDD reaches a minimal voltage (1 V in
worse‑case conditions).
To avoid leakage currents between the available supplies and VDD (or ground), VDD must be provided first to the
MCU, and then released with tolerance during power down (see Section 2.3.3).

2.3.2 General requirements

During power-up and power-down phases, the following power sequence requirements must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, and VDDUSB) must remain below
VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.

Figure 11. Power-up/power-down sequence

3.6
VDDX(1)

VDD

VPOR
VPDR

0.3
DT47490V2

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD

(1) VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
Note: VBAT is an independent supply and has no constraint versus VDD. All power supply rails can be tied together.

2.3.3 Particular conditions during the power-down phase

During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided
to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time
constants during the power-down transient phase (see Figure 11).
VDDX (VDDA, VDDIO2, or VDDUSB) power rails must be switched off before VDD.
Note: During the power-down transient phase, VDDX can remain temporarily above VDD (see Figure 11).

AN5373 - Rev 6 page 18/47

 AN5373
Reset and power-supply supervisor

Example of computation of the energy provided to the MCU during the power-down phase
If the sum of decoupling capacitors on VDDX is 10 μF and VDD drops below 1 V while VDDX is still at 3.3 V,
the energy remaining in the decoupling capacitors is:

E = 1 C × V2 = 1 × 10−5 × 3.32 = 0.05 mJ

2 2
The energy remaining in the decoupling capacitors is below 1 mJ, so it is acceptable for the MCU to absorb it.

2.4 Reset and power-supply supervisor

2.4.1 Brownout reset (BOR)

The devices have a brownout reset (BOR) circuitry. The BOR is active in all power modes except Shutdown
mode, and cannot be disabled. The BOR monitors the backup domain supply voltage that is VDD when present,
VBAT otherwise.
Five BOR thresholds can be selected through option bytes.
During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified VBORx
threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the
VBORx upper limit, the device reset is released, and the system can start.
For more details on the brownout reset thresholds, refer to the electrical characteristics section in the datasheet.

Figure 12. Brownout reset waveform

VDD
VBOR0 (rising edge)

hysteresis
VBOR0 (falling edge)

Temporization
tRSTTEMPO

DT31444V1
Reset

Note: The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).

2.4.2 System reset

A system reset sets all registers to their reset values except the reset flags in RCC_CSR and the registers in the
backup domain.
A system reset is generated when one of the following events occurs (refer to document [1] for more details):
• a low level on the NRST pin (external reset)
• a window watchdog event (WWDG reset)
• an independent watchdog event (IWDG reset)
• a software reset
• a low-power mode security reset
• an option-byte loader reset
• a brownout reset
These sources act on the NRST pin that is always kept low during the delay phase. The reset service routine
vector is selected via the boot option bytes.

AN5373 - Rev 6 page 19/47

 AN5373
Reset and power-supply supervisor

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a
minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse
is generated while the NRST pin is asserted low.
In case of an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption
through the pull-up resistor.

Figure 13. Simplified diagram of the reset circuit

VDD

RPU
System reset

External
reset Filter
NRST WWDG reset
IWDG reset
Pulse Software reset
generator
(min 20 μs) Low-power manager reset

DT40966V1
Option byte loader reset
BOR

2.4.3 Backup domain reset

A backup domain reset is generated when one of the following events occurs:
• a software reset, triggered by setting the BDRST bit in RCC_BDCR
• a VDD or VBAT power-on, if both supplies have previously been powered off
A backup domain reset only affects the LSE oscillator, RTC and TAMP, backup registers, the backup SRAM, and
RCC_BDCR and PWR_BDCR1.

AN5373 - Rev 6 page 20/47

 AN5373
Packages

3 Packages

3.1 Package summary

The package selection must consider the constraints that are strongly dependent upon the application.
The list below summarizes the most frequent ones:
• Number of interfaces required: Some interfaces may not be available on some packages. Some interfaces
combinations may not be possible on some packages.
• PCB technology constrains: Small pitch and high-ball density may require more PCB layers and
higher‑class PCB.
• Package height
• PCB available area
• Noise emission or signal integrity of high-speed interfaces
• Smaller packages usually provide better signal integrity. This is further enhanced as small-pitch and high-
ball density requires multilayer PCBs that allow better supply/ground distribution.
• Compatibility with other devices

AN5373 - Rev 6 page 21/47

 AN5373
Conversion from UFBGA169 to TFBGA169 boards

Table 1. Package summary for STM32U5 devices

Pitch STM32U535/ STM32U575/ STM32U59/ STM32U5F/

Package Size (mm) Height (mm)
(mm) 545xx 585xx 5Axxx 5Gxxx

LQFP48 7×7 0.5 1.6 X X - -

UFQFPN48 7×7 0.5 0.6 X X - -
LQFP64 10 × 10 0.5 1.6 X X X -
UFBGA64 5×5 0.5 0.6 X - - -
LQFP100 14 × 14 0.5 1.6 X X X X
UFBGA100 7×7 0.5 0.6 X - - -
UFBGA132 7×7 0.5 0.6 - X X -
LQFP144 20 × 20 0.5 1.6 - X X -

UFBGA169(1) 7×7 0.5 0.6 - X - -

TFBGA169(1) 7×7 0.5 1.1 - - X -

LQFP48 SMPS 7×7 0.5 1.6 X X - -

UFQFPN48 SMPS 7×7 0.5 0.6 X X - -
WLCSP56 SMPS 3.38 × 3.38 0.4 0.59 X - - -
LQFP64 SMPS 10 × 10 0.5 1.6 X X X -
UFBGA64 SMPS 5×5 0.5 0.6 X - - -
WLCSP72 SMPS 3.38 × 3.38 0.35 0.58 X - - -
WLCSP90 SMPS 4.20 × 3.95 0.40 0.59 - X - -
LQFP100 SMPS 14 × 14 0.5 1.6 X X X X
LQFP100 DSI SMPS 14 × 14 0.5 1.6 - - - X
UFBGA100 SMPS 7×7 0.5 0.6 X - - -
UFBGA132 SMPS 7×7 0.5 0.6 - X X -
LQFP144 SMPS 20 × 20 0.5 1.6 - X X -
LQFP144 DSI SMPS 20 × 20 0.5 1.6 - - - X
UFBGA144 DSI SMPS 10 × 10 0.8 0.850 - - - X
WLCSP150 SMPS 5.38 × 5.47 0.4 0.58 - - X -
WLCSP150 DSI SMPS 5.38 × 5.47 0.4 0.58 - - X -

UFBGA169 SMPS(1) 7×7 0.5 0.6 - X - -

TFBGA169 SMPS(1) 7×7 0.5 1.1 - - X -

WLCSP208 DSI SMPS -(2) 0.35 0.58 - - X X

TFBGA216 DSI SMPS 13 × 13 0.8 1.1 - - X X

1. For more information about the compatibility between UFBGA169 and TFBGA169, refer to Section 3.2.
2. Size in mm for STM32U59/5Axxx: 5.38 × 5.47
Size in mm for STM32U5F/5Gxxx: 5.8 × 5.6

3.2 Conversion from UFBGA169 to TFBGA169 boards

The UFBGA169 and TFBGA169 packages are compatible. However, it is important to note that the TFBGA169
balls have a larger diameter than the UFBGA169 balls, while the pitch of both packages is the same. To ensure
compatibility between the two packages, STMicroelectronics recommends maintaining a 280 µm solder mask
opening on the PCB. Additionally, customers must consider the height difference between the TFBGA169 and
UFBGA169 packages when designing their application.

AN5373 - Rev 6 page 22/47

 3.3 Pinout summary
AN5373 - Rev 6

Table 2. Pinout summary for STM32U5 devices

WLCSP150 DSI SMPS

WLCSP208 DSI SMPS

UFBGA144 DSI SMPS

TFBGA216 DSI SMPS

LQFP100 DSI SMPS

LQFP144 DSI SMPS

WLCSP150 SMPS
UFQFPN48 SMPS

UFBGA100 SMPS
UFBGA132 SMPS

UFBGA169 SMPS

TFBGA169 SMPS
WLCSP56 SMPS

WLCSP72 SMPS
WLCSP90 SMPS
UFBGA64 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS
UFQFPN48

UFBGA100

UFBGA132

UFBGA169

TFBGA169
UFBGA64
LQFP100

LQFP144
LQFP48

LQFP64
Pin name

Specific I/Os

PC14-OSC32_IN X(1) X X X X X X X X X X X X X X X X X X X X X X X X X X X

PC15-
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
OSC32_OUT
PH0-OSC_IN X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PH1-OSC_OUT X X X X X X X X X X X X X X X X X X X X X X X X X X X X
System pins
NRST X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PH3-BOOT0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Power pins
VBAT X X X X X X X X X X X X X X X X X X X X X X X X X X X X

VDDUSB(2) o X X X X X X X X o X X X X X X X X X X X X X X X X X X

VSSA(3) o o o X X o X o o o o o o o o o o o o o o o o o o o X X

VREF- o o o X X o X o o o o o o o o o o o o o o o o o o o X X

VREF+(4) o o o X X o X X X o o o o o X X o X X X X X X X X X X X

VDDA o o X X X o X X X o o o o o X X X X X X X X X X X X X X

Pinout summary
VDDIO2 -(5) - - - - X X X X - - - - X X - - - X X - - X X X X X X

AN5373
page 23/47

VDD11 - - - - - - - - - X X X X X X X X X X X X - X X X X X X
VDDSMPS - - - - - - - - - X X X X X X X X X X X X X X X X X X X
 AN5373 - Rev 6

WLCSP150 DSI SMPS

WLCSP208 DSI SMPS

UFBGA144 DSI SMPS

TFBGA216 DSI SMPS

LQFP100 DSI SMPS

LQFP144 DSI SMPS

WLCSP150 SMPS
UFQFPN48 SMPS

UFBGA100 SMPS
UFBGA132 SMPS

UFBGA169 SMPS

TFBGA169 SMPS
WLCSP56 SMPS

WLCSP72 SMPS
WLCSP90 SMPS
UFBGA64 SMPS

LQFP100 SMPS

LQFP144 SMPS
LQFP48 SMPS

LQFP64 SMPS
UFQFPN48

UFBGA100

UFBGA132

UFBGA169

TFBGA169
UFBGA64
LQFP100

LQFP144
LQFP48

LQFP64
Pin name

VSSSMPS - - - - - - - - - X X X X X X X X X X X X X X X X X X X
VLXSMPS - - - - - - - - - X X X X X X X X X X X X X X X X X X X
VCAP X X X X X X X X X - - - - - - - - - - - - - - - - - - -
VDDDSI - - - - - - - - - - - - - - - - X - - - X X - X - - X X
VDD11DSI - - - - - - - - - - - - - - - - X - - - X X - X - - X X
VSSDSI - - - - - - - - - - - - - - - - X - - - X X - X - - X X
VDD11USB - - - - - - - - - - - - - - - - - - - - - - - X - - X X
Number of VDD 3 3 3 5 5 6 9 10 10 3 3 3 4 4 4 5 9 5 6 9 10 8 9 9 10 10 17 10
Number of VSS 3 4 4 5 5 6 11 11 11 3 4 3 3 6 4 5 7 6 6 11 10 12 12 10 11 11 19 20

1. 'X' means that the pin is present.

2. 'o' means that VDD and VDDUSB are internally connected and available on a single pin.
3. 'o' means that VSSA and VREF- are internally connected and available on a single pin.
4. 'o' means that VDDA and VREF+ are internally connected and available on a single pin.
5. '-' means that the pin is absent.

Caution: Packages with and without SMPS are not compatible, in almost all power supply pins of Table 2.
Example: VDDIO2 is the pin number 130 on SMPS package. Pin 130 on the package without SMPS is mapped to a VSS pin. It means that the system
is short‑circuited when a legacy package is mounted on an SMPS socket.

Pinout summary
AN5373
page 24/47
 AN5373
Clocks

4 Clocks

The following clock sources can be used to drive the system clock (SYSCLK):
• HSI16: high-speed internal 16 MHz RC oscillator clock
• MSIS: multi-speed internal RC oscillator clock
• HSE: high-speed external crystal or clock, from 4 to 50 MHz
• PLL1 clock
The MSIS is used as system clock source after startup from reset, configured at 4 MHz.
The devices have the following additional clock sources:
• MSIK: multi-speed internal RC oscillator clock used for peripherals kernel clocks
• LSI: 32 kHz low-speed internal RC that drives the independent watchdog and optionally the RTC used for
auto-wakeup from Stop and Standby modes
• LSE: 32.768 kHz low-speed external crystal or clock that optionally drives the real-time clock (rtc_ck)
• HSI48: internal 48 MHz RC that potentially drives the OTG FS, the SDMMC and the RNG
• SHSI: secure high-speed internal RC that drives the secure AES (SAES).
• PLL2 and PLL3 clocks
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
Several pre-scalers can be used to configure the AHB and the APB frequencies domains with a maximum
frequency of 160 MHz.

4.1 HSE clock

The high-speed external clock signal (HSE) can be generated from the following clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock that feeds OSC_IN pin
The resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to
minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted
according to the selected oscillator.

Table 3. HSE/LSE clock sources

Clock source Hardware configuration

OSC_IN OSC_OUT
External clock
DT46306V1

GPIO

External souce

OSC_IN OSC_OUT

Crystal/ceramic resonators
DT46308V1

CL1 CL2
Load
capacitors

CL1 and CL2 values depend on the quartz. Refer to document [3] for more details.

AN5373 - Rev 6 page 25/47

 AN5373
HSI16 clock

4.1.1 External crystal/ceramic resonator (HSE crystal)

The 4 to 50 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The
associated hardware configuration is shown in Table 3. Refer to the electrical characteristics section of the
datasheet for more details.

4.1.2 External source (HSE bypass)

In this mode, an external clock source must be provided, with a frequency up to 50 MHz. The external clock signal
(square, sinus or triangle) with ~40 to 60 % duty cycle depending on the frequency (refer to the datasheet), must
drive the OSC_IN pin while the OSC_OUT pin can be used as a GPIO (see Table 3).
Note: For details on pin availability, refer to the pinout section of the datasheet. To minimize the consumption, the
square signal is recommended.

4.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. The HSI16 RC oscillator provides a
clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator.
However, even with calibration, the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
The HSI16 clock can be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails.
For more details, refer to section Clock security system (CSS) in document [1].

4.3 MSI (MSIS and MSIK) clocks

The MSI is made of four internal RC oscillators: MSIRC0 (48 MHz), MSIRC1 (4 MHz), MSIRC2 (3.072 MHz), and
MSIRC3 (400 kHz). Each oscillator feeds a prescaler providing a division by 1, 2, 3 or 4.
Two output clocks are generated from these divided oscillators:
• MSIS that can be selected as system clock
• MSIK that can be selected by some peripherals as kernel clock
MSIS and MSIK frequency range can be adjusted by software, by using respectively the MSISRANGE [3:0] and
MSIKRANGE [3:0] fields in RCC_ICSCR1, with MSIRGSEL = 1. Sixteen frequency ranges are available,
generated from the four internal RCs (refer to document [1] for more details).
The MSI clock can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails (refer
to section Clock security system (CSS) in document [1]).
The MSI oscillator provides a low-cost (no external components) low-power clock source. In addition, when the
MSI is used in PLL‑mode with the LSE, it provides a very accurate clock source that can be used by the USB
OTG_FS peripheral, and feeds the PLL to run the system at the maximum speed 160 MHz.

Hardware auto calibration with LSE (PLL-mode)

When a 32.768 kHz external oscillator is present in the application, either MSIS or MSIK can be configured in a
PLL‑mode. This mode is enabled as follows:
• for MSIS: by setting the MSIPLLEN bit to 1 in RCC_CR
• for MSIK: by setting the MSIPLLEN bit to 0 in RCC_CR
In case MSIS and MSIK ranges are generated from the same MSIRC source, the PLL‑mode is applied on both
MSIS and MSIK. When configured in PLL‑mode, the MSIS or MSIK automatically calibrates itself thanks to the
LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSIK in PLL‑mode can be used for the
USB OTG_FS peripheral, avoiding the need of an external high‑speed crystal.
For more details on how to measure the MSI frequency variation, refer to section Internal/external clock
measurement with TIM15/TIM16/TIM17 in document [1].
Note: On STM32U5Ax/59x/5Fx/5Gx, the OTG_HS peripheral cannot be clocked by the MSI in PLL‑mode. The HSE
crystal must be used.

4.4 LSE clock

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator (see Table 3). It provides a
low‑power but highly accurate clock source to the RTC (real-time clock) peripheral for clock/calendar or other
timing functions.

AN5373 - Rev 6 page 26/47

 AN5373
LSE clock

The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in RCC_BDCR, to
obtain the best compromise between robustness and short startup time on one side, and low-power-consumption
on the other side.

External source (LSE bypass)

In this mode, an external clock source must be provided, with a frequency up to 1 MHz. The external clock signal
(square, sinus, or triangle) with ~50 % duty cycle, must drive the OSC32_IN pin while the OSC32_OUT pin can
be used as GPIO (see Table 3).

AN5373 - Rev 6 page 27/47

 AN5373
Boot configuration

5 Boot configuration

5.1 Boot mode selection

At startup, a BOOT0 pin, nBOOT0, and NSBOOTADDx[24:0]/SECBOOTADD0[24:0] option bytes are used to
select the boot memory address that includes:
• Boot from any address in user flash memory
• Boot from system memory (bootloader)
• Boot from any address in embedded SRAM
• Boot from root security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user
option bit to free the GPIO pad if needed.
When TrustZone® is disabled by resetting TZEN option bit (TZEN = 0), the boot space is as detailed in the table
below.

Table 4. Boot modes when TrustZone® is disabled (TZEN = 0)

nBOOT0 nSWBOOT0
BOOT0 Boot address ST programmed
FLASH_ FLASH_ Boot area
pin PH3 option‑byte selection default value
OPTR[27] OPTR[26]

Boot address defined by user option

- 0 1 NSBOOTADD0[24:0] Flash: 0x0800 0000
bytes NSBOOTADD0[24:0]
Boot address defined by user option Bootloader:
- 1 1 NSBOOTADD1[24:0]
bytes NSBOOTADD1[24:0] 0x0BF9 0000
Boot address defined by user option
1 - 0 NSBOOTADD0[24:0] Flash: 0x0800 0000
bytes NSBOOTADD0[24:0]
Boot address defined by user option Bootloader:
0 - 0 NSBOOTADD1[24:0]
bytes NSBOOTADD1[24:0] 0x0BF9 0000

When TrustZone® is enabled by setting the TZEN option bit (TZEN = 1), the boot space must be in a secure area.
The SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address. A unique boot entry
option can be selected by setting the BOOT_LOCK option bit. All other boot options are ignored.

AN5373 - Rev 6 page 28/47

 AN5373
Embedded bootloader and RSS

The table below details the boot modes when the TrustZone® is enabled.

Table 5. Boot modes when TrustZone® is enabled (TZEN = 1)

nBOOT0 BOOT0 nSWBOOT0

BOOT_ ST
RSS Boot address
FLASH_ pin FLASH_ Boot area programmed
LOCK command option‑byte selection
default value
OPTR[27] PH3 OPTR[26]

Secure boot address

defined by user option Flash:
- 0 1 0 SECBOOTADD0[24:0]
bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS
0x0FF8 0000
Secure boot address
0
defined by user option Flash:
1 - 0 0 SECBOOTADD0[24:0]
bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
0 - 0 0 N/A RSS
0x0FF8 0000
RSS:
- - - ≠0 N/A RSS
0x0FF8 0000
Secure boot address
defined by user option Flash:
1 - - - - SECBOOTADD0[24:0]
bytes 0x0C00 0000
SECBOOTADD0[24:0]

5.2 Embedded bootloader and RSS

The embedded bootloader is located in the system memory and programmed by ST during production. It is used
to reprogram the flash memory by using the following serial interfaces:
• USART: USART1 on pins PA9/PA10, USART2 on pins PA2/PA3, USART3 on pins PC10/PC11
• I2C: I2C1 on pins PB6/PB7, I2C2 on pins PB10/PB11, I2C3 on pins PC0/PC1
• SPI: SPI1 on pins PA4/PA5/PA6/PA7, SPI2 on pins PB12/PB13/PB14/PB15, SPI3 on pins PB5/PG9/PG10/
PG12
• FDCAN: FDCAN1 on pins PB8/PB9
• USB in device mode through the DFU (device firmware upgrade) interface, on pins PA11/PA12
For further details on the STM32 bootloader, refer to document [2].
The RSS (root secure services) are embedded in a flash memory area named secure information block,
programmed during ST production.
The RSS enable, for example, the SFI (secure firmware installation) using the RSS extension firmware
(RSSe SFI). This feature allows the customers to protect the confidentiality of the firmware to be provisioned into
the STM32 device when the production is subcontracted to a third party. Refer to document [4].
The RSS are available on all devices, after enabling the TrustZone® through the TZEN option bit.

AN5373 - Rev 6 page 29/47

 AN5373
Debug management

6 Debug management

The serial wire/JTAG debug port (SWJ-DP) is an Arm® standard CoreSight™ debug port.
The host/target interface is the hardware equipment that connects the host to the application board. This interface
is made of three components: a hardware debug tool, a serial-wire connector, and a cable connecting the host to
the debug tool.
The figure below shows the connection of the host to a development board.

Figure 14. Host-to-board connection

JTAG/serial-wire connector
Debug tool

DT67885V1
Host PC
Power supply
STM32 board

The Nucleo demonstration board embeds the debug tools (STLINK), so it can be directly connected to the PC
through a USB cable.

6.1 SWJ-DP (serial-wire and JTAG debug port)

The SWJ-DP combines:
• a JTAG‑DP that provides a 5-pin standard JTAG interface to the AHP-AP port
• an SW-DP that provides a 2-pin (clock + data) interface to the AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.
Note: The software can configure all SWJ-DP port I/Os to other functions, but debugging is no longer possible.

6.2 Pinout and debug port pins

The devices are offered in various packages with different numbers of available pins. As a result, some
functionality related to the pin availability may differ from one package to another.

6.2.1 SWJ-DP pins

Five pins are used as outputs for the SWJ-DP, as alternate functions of the GPIOs (general-purpose I/Os). These
pins, detailed in the table below, are available on all packages.

Table 6. Debug port pin assignment

JTAG debug port SW debug port

SWJ-DP pin Pin assignment
Type Description Type Debug assignment

JTMS/SWDIO Input JTAG test mode selection Input/Output Serial‑wire data input/output PA13
JTCK/SWCLK Input JTAG test clock Input Serial‑wire clock PA14
JTDI Input JTAG test data input - - PA15
TRACESWO if asynchronous trace
JTDO/TRACESWO Output JTAG test data output - PB3
is enabled
JNTRST Input JTAG test nReset - - PB4

AN5373 - Rev 6 page 30/47

 AN5373
Pinout and debug port pins

6.2.2 Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins that
are immediately usable by the debugger host.
Note: The trace outputs are not assigned except if explicitly programmed by the debugger host.
The table below shows the different possibilities for releasing some pins (refer to document [1] for more details).

Table 7. SWJ-DP I/O pin availability

SWJ-DP I/O pin assigned

PA13 / PA14 /
Available debug ports PA15 / PB3 / PB4/
JTMS/ JTCK/
JTDI JTDO JNTRST
SWDIO SWCLK

Full SWJ‑DP (JTAG‑DP + SW‑DP)

X X X X X
Reset state
Full SWJ‑DP (JTAG‑DP + SW‑DP) but without JNTRST X X X X
JTAG-DP disabled and SW-DP enabled X X - -
JTAG-DP disabled and SW-DP disabled Released

6.2.3 Internal pull-up and pull-down resistors on JTAG pins

The JTAG input pins must not be floating since they are directly connected to flip-flops that control the debug
mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of
some of these flip-flops.
To avoid any uncontrolled I/O levels, the devices embed the following internal resistors on the JTAG input pins:
• JNTRST: internal pull-up
• JTDI: internal pull-up
• JTMS/SWDIO: internal pull-up
• TCK/SWCLK: internal pull-down
Once the user software releases the JTAG I/O, the GPIO controller takes the control again, and the software can
then use these I/Os as standard GPIOs. The reset states of the GPIO control registers put the I/Os in the
following equivalent states:
• JNTRST: input pull-up
• JTDI: input pull-up
• JTMS/SWDIO: input pull-up
• JTCK/SWCLK: input pull-down
• JTDO: input floating
Note: The JTAG IEEE standard recommends adding pull-up resistors on TDI, TMS, and nTRST, but there is no special
recommendation for TCK. However, for the devices, an integrated pull-down resistor is used for JTCK. Having
embedded pull-up and pull-down resistors removes the need to add external resistors.

AN5373 - Rev 6 page 31/47

 AN5373
Serial-wire debug (SWD) pin assignment

6.2.4 SWJ-DP connection with standard JTAG connector

The figure below shows the connection between the device and a standard JTAG connector.

Figure 15. JTAG connector implementation

JTAG connector
VDD VDD
Connector 2 x 10
STM32U5 MCU

(1) VTREF (2)

nJTRST (3) nTRST (4)
JTDI (5) TDI (6)
JTMS/SWDIO (7) TMS (8)
JTCK/SWCLK (9) TCK (10)
(11) RTCK (12)
JTDO (13) TDO (14)
nRST (15) nSRST (16)
(17) DBGRQ (18)
10 kΩ (19) DBGACK (20)
10 kΩ
10 kΩ

DT64362V1
VSS

6.3 Serial-wire debug (SWD) pin assignment

The same SWD pin assignment, detailed in the table below, is available on all packages.

Table 8. SWD port pins

SWD port
SWD pin Pin assignment
Type Debug assignment

SWDIO Input/Output Serial-wire data input/output PA13

SWCLK Input Serial-wire clock PA14

After reset, the pins used for the SWD are assigned as dedicated pins that can be immediately used by the
debugger host.
However, the MCU offers the possibility to disable the SWD, therefore releasing the associated pins for GPIO
use.
For more details on how to disable SWD port, refer to section I/O pin alternate function multiplexer and mapping
of document [1].

6.3.1 Internal pull-up and pull-down on SWD pins

Once the user software releases the SWD I/O, the GPIO controller takes control of it. The reset states of the
GPIO control registers put the I/Os in the equivalent states:
• SWDIO: alternate function pull-up
• SWCLK: alternate function pull-down
Having embedded pull-up and pull-down resistors removes the need to add external resistors.

AN5373 - Rev 6 page 32/47

 AN5373
Serial-wire debug (SWD) pin assignment

6.3.2 SWD port connection with standard SWD connector

The figure below shows the connection between the device and a standard SWD connector.

Figure 16. SWD connector implementation

CN1 10 NRST
9
8
7
6
5
4 SWCLK/PA14
3

DT64363V1
2 SWDIO/PA13
1 VDD
SWD connector STM32U5 device

AN5373 - Rev 6 page 33/47

 AN5373
Recommendations

7 Recommendations

7.1 PCB (printed circuit board)

For technical reasons, it is best to use a multilayer PCB, with a separate layer dedicated to ground (VSS) and
another dedicated to the VDD supply.
This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit
the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and
power supply.

7.2 Component position

A preliminary layout of the PCB must separate circuits into different blocks:
• high-current circuits
• low-voltage circuits
• digital component circuits
• circuits separated according to their EMI contribution, in order to reduce noise due to cross-coupling
on the PCB

7.3 Ground and power supply

The following rules related to grounding must be respected:
• Ground every block (noisy, low-level sensitive, digital, or others) individually.
• Return all grounds to a single point.
• Avoid loops (or ensure they have a minimum area).
In order to improve analog performance, the user must use separate supply sources for VDD and VDDA, and place
the decoupling capacitors as close as possible to the device.
The power supplies (VSS, VDD, VSSA, VDDA, VDDUSB, VDDIO2, VDDDSI, or VDDSMPS) must be implemented close to
the ground line to minimize the area of the supplies loop. This is because the supply loop acts as an antenna, and
acts as the main transmitter and receiver of EMI. All component‑free PCB areas must be filled with additional
grounding to create a kind of shielding (especially when using single‑layer PCBs).

7.4 Decoupling
All power-supply and ground pins must be properly connected to the power supplies. These connections
(including pads, tracks, and vias) must have the lowest possible impedance. This is typically achieved with thick
track widths and, preferably, the use of dedicated power-supply planes in multilayer PCBs.
In addition, each power supply pair must be decoupled with filtering ceramic capacitors (100 nF) and a tantalum
or ceramic capacitor of about 10 μF, connected in parallel on the device.
Some packages use a common VSS pin for several VDD pins, instead of a pair of power pins (one VSS for each
VDD). In that case, the capacitors must be between each VDD pin and the common VSS pin. These capacitors
must be placed as close as possible to, or below the appropriate pins on the underside of the PCB. Typical values
are 10 to 100 nF, but exact values depend on the application needs.

AN5373 - Rev 6 page 34/47

 AN5373
Other signals

The figure below shows the typical layout of such a VDD/VSS pin pair.

Figure 17. Typical layout for VDD/VSS pin pair

Via to VDD Via to VSS

VDD VSS

STM32

DT63912V1
7.5 Other signals
When designing an application, the EMC performance can be improved by closely studying the following:
• Signals for which a temporary disturbance affects the running process permanently (it is the case for
interrupts and handshaking strobe signals but not the case for LED commands)
For these signals, a surrounding ground trace, shorter lengths, and the absence of noisy and sensitive
traces nearby (crosstalk effect) improve EMC performance.
For digital signals, the best possible electrical margin must be reached for the two logical states. Slow
Schmitt triggers are recommended to eliminate parasitic states.
• Noisy signals (example: clock)
• Sensitive signals (example: high impedance)

7.6 Unused I/Os and features

All microcontrollers are designed for a variety of applications and often a particular application does not use
100 % of the MCU resources.
To increase the EMC performance and avoid extra power consumption, the unused features of the device must
be disabled and disconnected from the clock tree, as follows:
• The unused clock source must be disabled.
• The unused I/Os must not be left floating.
• The unused I/O pins must be configured as analog input by software, and must be connected to a fixed
logic level 0 or 1 by an external or internal pull-up or pull-down, or configured as output mode using
software.

AN5373 - Rev 6 page 35/47

 AN5373
Reference design

8 Reference design

8.1 Description
The reference designs shown in the next sections are based on STM32U5 devices in LQFP144 and TFBGA216
packages. This reference design can be tailored to any STM32U5 device with a different package, using the pin
correspondence given in Section 8.2 and Design reference for a STM32U599/5A9/5F9/5G9 device (with SMPS).

Clock
Two clock sources are used for the MCU (see Section 4 for more details):
• LSE: X1 – 32.768 kHz crystal for the embedded RTC
• HSE: X2 – 16 MHz crystal for the MCU
See Section 4 for more details.

Reset
The reset signal is active low in the reference design figures shown in Section 8.2.
The reset sources include:
• the reset button (B1)
• debugging tools via the connector CN1
See Section 2.4 for more details.

Boot mode
The user can add a switch on the board to change the boot option.
See Section 5 for more details.
Note: When waking up from Standby mode, the BOOT pin is sampled and the user must pay attention to its value.

SWD interface
The reference design shows the connection between the STM32U575/585 device and a standard SWD
connector.
See Section 6 for more details.
Note: To allow tools to reset the applications, the RESET pins must be connected.

Power supply
See Section 2 for more details.

AN5373 - Rev 6 page 36/47

 AN5373
Design reference for a STM32U5 device (with and without SMPS)

8.2 Design reference for a STM32U5 device (with and without SMPS)
Table 9 lists the components used for a STM32U5 design reference :
• based on STM32U535/545/575/585xxxxQ device, with SMPS (see Figure 18)
• based on a STM32U5xxx device, without SMPS (see Figure 19)

Table 9. Components of STM32U5 device design reference

Reference Type Value Quantity Comments

B1 Push-button - 1 -

Ceramic Decoupling capacitors

C1, C4, C6 1 µF 3
capacitor C6 used for the internal VREFBUF
Tantalum or
C2, C16 ceramic 10 µF 2 Decoupling capacitors required for the package
capacitor
C3 (x5), C5, C7, Ceramic
100 nF 10 For each external power pin
C8, C13, C17 capacitor
C15 4.7 µF 1 Decoupling capacitor

Tantalum or Required on each VDD11 pin of packages with

C18, C19 2.2 µF
ceramic SMPS
capacitor 2
C11, C12 3.9 µF Used for LSE: the value depends on the crystal
C9, C10 6.8 pF characteristics (refer to document [3])

L1 Coil 2.2 µH 1 Required for SMPS packages on VLXSMPS pin

X1 32.768 kHz 1 Used for LSE
Quartz
X2 16 MHz 1 Used for HSE
R1 1 Used to limit the current on VBAT pin
Resistor 10 KΩ
R2, R3, R4 3 Used for the ST‑LINK interface
SW1 Switch - 1 Used to select the right boot mode
ESD protection
U1, U2, U3 - 3
6V1
Used for ESD protection
R5, R6, R7, R8,
- 47 Ω 5
R9
ST LINK V2
P1 - 1 Used to connect an external ST‑LINK
connector

AN5373 - Rev 6 page 37/47

 AN5373
Design reference for a STM32U5 device (with and without SMPS)

Figure 18. STM32U535/545/575/585xxxxQ reference design (with SMPS)

DT71534V1

AN5373 - Rev 6 page 38/47

 AN5373
Design reference for a STM32U5 device (with and without SMPS)

Figure 19. STM32U5xxx reference design (without SMPS)

DT71533V1

AN5373 - Rev 6 page 39/47

 AN5373
Design reference for a STM32U5 device (with and without SMPS)

Table 10 lists the components in the STM32U599 discovery kit STM32U599J-DK (reference design MB1662)
based on STM32U599xxxxQ device, with SMPS (see Figure 20).

Table 10. Components of STM32U599 discovery kit

Reference Type Value Quantity Comments

B1 Push-button - 1 -

Ceramic Decoupling capacitors

C4, C6 1 µF 2
capacitor C6 used for the internal VREFBUF
Tantalum or
C2, C16 ceramic 10 µF 2 Decoupling capacitors required for the package
capacitor
C1, C3 (x10),
C5, C7, C8, Ceramic
100 nF 19 For each external power pin
C13, C17, C21, capacitor
C22, C23
C20 4.7 µF 1 Decoupling capacitor

Tantalum or Required on each VDD11 pin of packages with

C18, C19 2.2 µF 2
ceramic SMPS
C11, C12 capacitor 3.9 pF 2 Used for LSE: the value depends on the crystal
C9, C10 6.8 pF 2 characteristics (refer to document [3])

L1 Coil 2.2 µH 1 Required for SMPS packages on VLXSMPS pin

X1 32.768 kHz 1 Used for LSE
Quartz
X2 16 MHz 1 Used for HSE
R1 1 Used to limit the current on VBAT pin
Resistor 10 KΩ
R2, R3, R4 3 Used for the ST‑LINK interface
SW1 Switch - 1 Used to select the right boot mode
ESD protection
U1, U2, U3 - 3
6V1
Used for ESD protection
R5, R6, R7, R8,
- 47 Ω 5
R9
ST LINK V2
P1 - 1 Used to connect an external ST‑LINK
connector

AN5373 - Rev 6 page 40/47

 AN5373
Design reference for a STM32U5 device (with and without SMPS)

Figure 20. STM32U59/5A/5F/5GxxxxxQ reference design (with SMPS)

DT71535V1

AN5373 - Rev 6 page 41/47

 AN5373

Revision history
Table 11. Document revision history

Date Version Changes

21-Jun-2021 1 Initial release.

Updated:
3-Jan-2022 2 • Section 2 Power supply management
• Section 8.2 Component references
14-Nov-2022 3 Updated various typos and Section 8.2 Component references
16-Feb-2023 4 Document updated to cover entire STM32U5 series microcontrollers
Updated:
• Voltage range values for VDDDSI and VDD11DSI in Section 2.1 Power
supplies
• Figure 1. STM32U535xxxxQ and STM32U545xxxxQ power supply
overview (with SMPS)
• Figure 2. STM32U535xx and STM32U545xx power supply overview
(without SMPS)
12-Apr-2023 5 • Figure 3. STM32U575xQ and STM32U585xQ power supply overview
(with SMPS)
• Figure 4. STM32U575xx and STM32U585xx power supply overview
(without SMPS)
• Figure 5. STM32U5F/5G/59/5AxxxxxQ power supply overview (with
SMPS)
• Figure 6. STM32U5F/5G/59/5Axxx power supply overview (without
SMPS)
Updated:
• Note added for VLXSMPS in Section 2.1 Power supplies
• Table 1. Package summary for STM32U5 devices
01-Sept-2023 6 • Section 8.1 Description
• Table 9. Components of STM32U5 device design reference
• Table 10. Components of STM32U599 discovery kit
Added Section 3.2 Conversion from UFBGA169 to TFBGA169 boards

AN5373 - Rev 6 page 42/47

 AN5373
Contents

Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Independent analog peripherals supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Independent I/O supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Independent USB transceiver supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.4 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.5 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.6 Power supply for I/O analog switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Power supply schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Power supply isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 General requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.3 Particular conditions during the power-down phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Reset and power-supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 Brownout reset (BOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Package summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Conversion from UFBGA169 to TFBGA169 boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1 HSE clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 MSI (MSIS and MSIK) clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 Boot configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 Embedded bootloader and RSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1 SWJ-DP (serial-wire and JTAG debug port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AN5373 - Rev 6 page 43/47

 AN5373
Contents

6.2.1 SWJ-DP pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.3 Internal pull-up and pull-down resistors on JTAG pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.4 SWJ-DP connection with standard JTAG connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 Serial-wire debug (SWD) pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2 SWD port connection with standard SWD connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7.1 PCB (printed circuit board). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 Ground and power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 Design reference for a STM32U5 device (with and without SMPS) . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

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 AN5373
List of tables

List of tables
Table 1. Package summary for STM32U5 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2. Pinout summary for STM32U5 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. HSE/LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. Boot modes when TrustZone® is disabled (TZEN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5. Boot modes when TrustZone® is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. SWJ-DP I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Components of STM32U5 device design reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Components of STM32U599 discovery kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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 AN5373
List of figures

List of figures
Figure 1. STM32U535xxxxQ and STM32U545xxxxQ power supply overview (with SMPS). . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. STM32U535xx and STM32U545xx power supply overview (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. STM32U575xQ and STM32U585xQ power supply overview (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. STM32U575xx and STM32U585xx power supply overview (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. STM32U5F/5G/59/5AxxxxxQ power supply overview (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. STM32U5F/5G/59/5Axxx power supply overview (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Power supply scheme for U535/545/575/585xxxxQ (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Power supply scheme for STM32U535/545/575/585xx (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Power supply scheme for STM32U5F/5G/59/5Axxx (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Power supply scheme for STM32U5F/5G/59/5Axxx (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Brownout reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. SWD connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Typical layout for VDD/VSS pin pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. STM32U535/545/575/585xxxxQ reference design (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. STM32U5xxx reference design (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. STM32U59/5A/5F/5GxxxxxQ reference design (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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 AN5373

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