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Digital System Design Using VHDL (VIVA Questions)

This document contains 46 questions related to digital system design using VHDL. Some of the key topics covered include simulation vs synthesis, HDLs like VHDL, uses of FPGAs and CPLDs, the process of converting VHDL code to a bitstream file, modeling styles in VHDL, differences between signals and variables, data types, libraries, modeling concurrent and sequential processes, and schematics related to the logic design of an FPGA.

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Shashank Khobragade
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474 views3 pages

Digital System Design Using VHDL (VIVA Questions)

This document contains 46 questions related to digital system design using VHDL. Some of the key topics covered include simulation vs synthesis, HDLs like VHDL, uses of FPGAs and CPLDs, the process of converting VHDL code to a bitstream file, modeling styles in VHDL, differences between signals and variables, data types, libraries, modeling concurrent and sequential processes, and schematics related to the logic design of an FPGA.

Uploaded by

Shashank Khobragade
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System design using VHDL (VIVA Questions)

1. what is simulation? 2. what is synthesize? 3. what is HDL? 4. expand VHDL, FPGA, CPLD. 5. use of HDL? 6. steps taken by the processor to convert .vhd to .bit.? 7. can you download .vhd directly to your kit? 8. use of FPGA/CPLD/ASICs? 9. difference between C and VHDL ? 10. Name three styles of Modeling 11.difference between the three styles of modeling 12.what is the use of Process? 13. what is the use of sensitivity list? 14. diff b/n for loop and for generate? 15. diff b/n with/select and case select? 16.diff b/n bit and std_logic? 17. what is the use of High Impedance state? 18. dataflow is sequential or concurrent? 19. diff b/n sequential and concurrent? 20. behavioral is sequential or concurrent? 21. name different data types? 22. name few library functions?

23. what is the use of library function? 24. whether you need library functions if you use bit as a data type? 25. diff b/n Signal and Variable? 26. symbols used in case of signals and variables? 27. is it possible to use IF inside data flow style of modeling? 28. is it possible to use FOR inside data flow style of modeling? 29. True or false: everything is simulatable but not synthesizable. 30. diff b/n FOR loop and While loop? 31. use of entity? 32. use of architecture? 33. library required if you want to use temp:=temp+1; 34. in temp:= temp + 1 what is the importance of single quote? 35. when double quotes or no quotes can be used in the above case? 36. if signal a is std_logic_vector(7 downto 0) type and if signal b is std_logic_vector(7 downto 0) type: then which one of the following statement is true/corret? 1. b<=a 2. a<=b 3. b<=a(2 downto 0) 4. b<=a(3 downto 0) 5. b<=a(7 downto 3)] 6.a(7 downto 3)<=b(3 downto 0); 37. what is the importance of RTL schematic? 38. what is the importance of Technology schematic? 39. Ultimately FPGA is combination of .. and .. and etc. 40.True or False: whatever code we write finally the software (depending upon

the destination chip) is going to optimize the code. 41.what is the diff b/n RTL schematic and Technology schematic? 42.what is meant by speed grade? 43.speed of XC2S100 and XC3S400? 44. what is the use of clock divider programme.? 45. expand FRC, JTAG. 46. How many number of gates are there in XC2S100 and XC3S400?

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