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Yield Analysis - Unit 1

A chip with no manufacturing defect is called a good chip. Defect Level is the ratio of faulty chips among the chips that pass tests. A DL greater than 500 ppm is considered unacceptable.

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27 views15 pages

Yield Analysis - Unit 1

A chip with no manufacturing defect is called a good chip. Defect Level is the ratio of faulty chips among the chips that pass tests. A DL greater than 500 ppm is considered unacceptable.

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api-78343547
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© Attribution Non-Commercial (BY-NC)
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Lecture 4 Yield Analysis & Product Quality

Yield and manufacturing cost Clustered defect yield formula Yield improvement

Defect level
Test data analysis Example: SEMATECH chip Summary
VLSI Test: Bushnell-Agrawal/Lecture 4 1

Jan. 26, 2001

VLSI Chip Yield

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip:

Cost of fabricating and testing a wafer -------------------------------------------------------------------Yield x Number of chip sites on the wafer
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 2

Clustered VLSI Defects


Good chips

Faulty chips

Defects Wafer
Unclustered defects Wafer yield = 12/22 = 0.55
Jan. 26, 2001

Clustered defects (VLSI) Wafer yield = 17/22 = 0.77


3

VLSI Test: Bushnell-Agrawal/Lecture 4

Yield Parameters

Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter (a) Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x )

(Ad /a) x = ------------- . ---------------------x ! G (a) (1+Ad /a) a+x where G is the gamma function a =0, p (x ) is a delta function (max. clustering) a = , p (x ) is Poisson distr. (no clustering)

G (a+x )

Jan. 26, 2001

VLSI Test: Bushnell-Agrawal/Lecture 4

Yield Equation
Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / a ) - a
Example: Ad = 1.0, a = 0.5, Y = 0.58 Unclustered defects: a = Example: Ad = 1.0, a =

, Y = e - Ad
, Y = 0.37

too pessimistic !
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 5

Defect Level or Reject Ratio


Defect level (DL) is the ratio of faulty

chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

Jan. 26, 2001

VLSI Test: Bushnell-Agrawal/Lecture 4

Determination of DL

From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

Jan. 26, 2001

VLSI Test: Bushnell-Agrawal/Lecture 4

Modified Yield Equation

Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, b Stuck-at fault coverage, T The modified yield equation:

Y (T ) = (1 + TAf / b) - b
Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / b) - b
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 8

Defect Level
DL (T ) = -------------------Y (T )
( b + TAf ) = 1 - -------------------b

Y (T ) - Y (1)

( b + Af ) Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, b is the fault clustering parameter. Af and b are determined by test data analysis.
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 9

Example: SEMATECH Chip


Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM)
VLSI Test: Bushnell-Agrawal/Lecture 4 10

Jan. 26, 2001

Test Coverage from Fault Simulator


Stuck-at fault coverage

Vector number
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 11

Measured Chip Fallout


Measured chip fallout

Vector number
Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 12

Model Fitting
Chip fallout and computed 1-Y (T )

Chip fallout vs. fault coverage


Y (1) = 0.7623

Measured chip fallout

Y (T ) for Af = 2.1 and b = 0.083

Stuck-at fault coverage, T


Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 13

Computed DL
237,700 ppm (Y = 76.23%)

Defect level in ppm

Stuck-at fault coverage (%)


Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 4 14

Summary

VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (a) Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99%
VLSI Test: Bushnell-Agrawal/Lecture 4 15

Jan. 26, 2001

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