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8086 Signals

The document discusses the minimum and maximum mode signals of the 8086 microprocessor. In minimum mode, the 8086 provides address/data bus signals, status control signals, interrupt signals, and DMA signals to implement the memory and I/O interface with 1MB address space. Maximum mode adds signals for implementing multiprocessor/coprocessor systems with global resources shared between processors and passing of bus control. These include status signals, bus request/grant signals, and a LOCK signal to prevent other masters from gaining bus control during locked cycles.

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344 views11 pages

8086 Signals

The document discusses the minimum and maximum mode signals of the 8086 microprocessor. In minimum mode, the 8086 provides address/data bus signals, status control signals, interrupt signals, and DMA signals to implement the memory and I/O interface with 1MB address space. Maximum mode adds signals for implementing multiprocessor/coprocessor systems with global resources shared between processors and passing of bus control. These include status signals, bus request/grant signals, and a LOCK signal to prevent other masters from gaining bus control during locked cycles.

Uploaded by

sushalwork
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Minimum mode signals:

When the Minimum mode operation is selected, the

8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups : address/data bus, status control,interrupt and DMA.

Address/Data Bus : these lines serve two

functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data busduring next machine cycles. D15 is the MSB and D0 LSB.

DT/R: (Data transmit / Receive): It is an o/p signal

from the processor to control the direction of data flow DEN : It is an o/p signal used to enable the data during DTR. ALE :It is used to differentiate between HOB an LOB M/IO: It is used to differentiate between Memory access and I/O access. WR:It is a write control signal and it is asserted low whenever the processor writes data to memory or IO port.

INTA : INTA is a line to acknowledge when the

interrupt request is accepted by the processor. HOLd : It is an input signal to the processor from other bus .It is used by DMA Controller to get control of the bus. HLDA :It is an ACK signal by the processor to the BUS requesting the control of the bus through HOLD .

Maximum mode Signals


When the 8086 is set for the maximum-mode

configuration, it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources.

Coprocessor also means that there is a second

processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.

S0,S1,S2 , : These are status signals required to generate

bus timing and control signals. RQ/GT : Bus Request /Bus Grant to force the processor to release the local bus at the end of current bus cycle. LOCK: It is an o/p signal activated by the LOCK prefix instruction to prevent other bus masters from gaining control of the system bus. QS1,QS0 : The processor provides the status of the queue on these lines.

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