Fundamental of SDH Technology
Fundamental of SDH Technology
By
Saurabh Srivastava
Chapter-1 PDH and SDH Technologies
Chapter-2 SDH Synchronization
Chapter-3 New Generation SDH
Chapter-4 SDH Products
Chapter-5 Transmission Network Architecture
Chapter-6 Network Management System
Chapter-7 Transmission Testing Concepts
Sub-Modules
Chapter-1 PDH and SDH Technologies
1.01 Plesiochronous Digital Hierarchy
1.02 Jitter & Wander
1.03 Disadvantages of PDH
1.04 Advantages of SDH
1.05 SDH bit rates and Multiplexing
1.06 SDH Frame Structure
1.07 Frame Alignment
1.08 Mapping
1.09 Aligning of VC-12 with TU-12
1.10 Pointer
1.11 Multiplexing, Pointer & Frame Structure
1.12 Over head and Mapping
1.13 Contiguous & Virtual concatenation
1.14 Over head byte functionality
1.15 SDH Layer model
1.16 Elements of SDH Network
1.17 Automatic Protection Switching
1.18 SDH Management
Chapter-1 PDH and SDH Technologies
1.01 Plesiochronous Digital
Hierarchy
Plesio means = similar
Chronous means= Timing
Plesiochronous - "almost synchronous, because bits are
stuffed into the frames as padding and the
calls (signal) location varies slightly - jitters - from frame to
frame".
PDH (Plesiochronous Digital Hierarchy)
Pulse Code Modulation
.
The basis of analog to digital conversion is Shannons theory.The theory
states that after transmission the original signal can be reproduced within
certain limits from digital signal obtained by Sampling an analog at regular
intervals and at a rate at least twice the highest significant message
frequency.
The PCM Consists of 3 steps.
Sampling
Quantization
Coding
Sampling
T1 T2 T3
T4 T5 T6 T7
time
time
T1 T2 T3
T4 T5 T6 T7
Audio Signal
Sampler Output
Pulse Amplitude
Modulated
(PAM) signal
1. Voice Frequency 4 KHz
2. Sampling 4 KHz * 2 = 8 KHz
Quantization & Encoding
For Quantization CEPT countries use A- Law,other countries use -law is used.In -law the
decoder output value number is 0 to 127 for positive and 0 to 127 for Negative.While in A- Law ,the
decoder output value number is 1 to128 for positive and 1 to 128 for negative.
Quantizing = Amplitude is given a certain value.
Encoding = 8 KHz * 8 = 64 KHz
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32channels/Tim
e slots
0
Each channel is of 64Kb/s
FAS (Frame Alignment signal)
NFAS(Non frame Alignment signal)
32 * 64 KHz = 2.048 Mb/s
Capacity = 30 Base Channels
Signaling
2Mb Frame Structure
Submultiframe 1 Submultiframe 2
2ms ( 500Hz )
125ms ( 8 kHz )
Multi frame
F0 to F15
3.9 ms
frame alignment
CH . 1 CH . 16
CH . 15
CH . 30
Encoded telephone signals
Encoded telephone signals
488 ns ( 2048 KHz )
a to h = PCM 8 bit encoded telephone
signal of the assigned channel
Multiframe
alignment
Spare bit
FO
F 1
F 15
X : Bit reserved for future international use (No use =1) Can be
used for CRC-4 check bit
A : bit used to indicate MUX alarm (Normal1:0,Alarm=1)
Y: bit reserved for domestic use.One bit of 5 can be assigned for 2
Mb/s remote loop back command signal(OFF:1,ON: 0)
a to d = Signaling of the associated channel (CAS) or the
common signaling channel(CCS)
Multi Frame Structure
1. PCM 30 Mux (D1 Level )
2. PDH (D2 Level )
4 * 2.048 +stuffing bits = 8.448 Mbps
Capacity = 120 Base Channels
3. PDH (D3 Level )
4 * 8.448 + stuffing bits = 34.368
Mbps
Capacity = 480 Base Channels
4. PDH (D4 Level )
4 * 34.368 +stuffing bits = 139.264
Mbps
Capacity = 1920 Base Channels
5. PDH (D5 Level )
4 * 139 + stuffing bits = 565 Mbps
Capacity = 7680 Base Channels
PDH Bit rates
64kbit/s
Sampling x Coding
8kHz x 8bits
E1
2Mbit/s
32 Channels
(PCM30 or 31, CRC
C12 Container
8Mbit/s
4 Channels
E3
34Mbit/s
4 Channels
C4 Container
E4
140Mbit/s
4 Channels
C4 Container
Bit Stuffing
Pleisochronous Multiplexing
Bit Stuffing and Justification (Contd..)
The justification process is employed in all the PDH Multiplexers
At the far end of the transmission system, the justification bits are
removed and the original digital signal is recovered
The removal of these justification bits causes a small variation in the
phase of the clock.This variation is called Jitter
The number of stuffing bits added depends not only on the speed
of the tributaries to the multiplexer, but also on the speed of the
higher order bit stream
1.02 What are jitter and wander?
Jitter:
jitter is the term used to designate periodic or stochastic
deviations of the significant instants of a digital signal from the
ideal, equidistant values.
Otherwise stated, the transitions of a digital signal invariably
occur either too early or too late when compared to a perfect
square wave (reference clock).
Wander:
very slow jitter is known as wander. ITU-T G.810 puts the limit
between jitter and wander at 10 Hz.
Long-term
measurement (hours,
days)
Minutes Test times
Ns UI(Unit interval) Unit for amplitude
Absolutely necessary Not required Reference clock source
for measurement
Synchronization
problem
Causes bit errors Primary disruption
0-10Hz >10Hz Frequency range of phase
variations
Wander Jitter
Parameter
Jitter vs Wander
Jitter and Wander Definitions
Ideal Signal (NRZ)
Jittered Signal
Jitter
Sources of Jitter and Wander
Interference signals
Pattern dependent jitter
Phase noise
Delay variation
Stuffing and wait time jitter
Mapping jitter
Pointer jitter
Definition of Jitter Peak-to-Peak
Amplitude
Jitter
Amplitude
(PP)
Measurement Period
Jitter / UIpp
Time
WANDER Definitions
Wander Long-term timing variation (below 10 Hz)
TIE "Time Interval Error"
MTIE "Max. Time Interval Error"
TDEV "Time Deviation", timing variation as a function of
integration time. Provides information about the
spectral content.
TVAR "Time Variation", square of TDEV
ADEV "Allen Deviation"
MADEV "Modified Allen Deviation"
Plesiochronous Hierarchy based on 2Mbps primary rates permits
multiplexing up to 140Mbps respectively.
Changing from one hierarchical level to another requires additional
equipment.
Transmitting a multiplexed signal (34/140 Mb, etc) requires
specialized equipment.
Redirection (cross-connection) of channels must be done by hand on
DDFs.
Administrative connections require separate equipment to support
Supervision, EOW and protection switching.
Compatibility of transmission and administrative signals between
different vendor may give trouble.
1.03 Disadvantages of PDH
Need for extensive network management capability
within the hierarchy.
Standard interfaces between equipment.
Need for inter-working between north American and
European systems.
Facilities to add or drop tributaries directly from a
high speed signal.
Standardization of equipment management process.
1.04 Advantages of SDH
1.05 SDH Bit Rates and Multiplexing
USA, HongKong, Taiwan
STS1
OC1
51Mbit/s
STM-0
E4
140Mbit/s
4 Channels
C4 Container
DS3
44.36Mbit/s
P
D
H
(
a
s
y
n
-
c
h
r
o
n
o
u
s
)
S
D
H
(
s
y
n
c
h
r
o
n
o
u
s
)
OC48
2.5Gbit/s
STM-16
OC12
622Mbit/s
STM-4
OC192
10Gbit/s
STM-64
OC768
40Gbit/s
STM-256
STS3
OC3
155Mbit/s
STM-1
A frame with a bit rate of 155.52Mbps is defined in ITU-T
recommendation G.707.This frame is called Synchronous
Transport Module(STM),since it is the first level in hierarchy
it is called STM-1
It is made up from a byte matrix of 9 rows and 270 columns
Transmission is row by row, starting with the byte in the
upper left corner and ending with the byte in the lower right
corner
The frame repetition rate is 125ms.Each byte in payload
represents a 64kbps channel
1.06 SDH Frame Structure
The STM-n frame structure is best represented as a rectangle of 9 x 270 x n.
The 9 x n first columns are the frame header and the rest of the frame is the
inner structure data i.e. payload (including the data, indication bits, stuff bits,
pointers and management).
The STM-n frame is usually transmitted over an optical fiber. The frame is
transmitted row by row (first is transmitted the first row then the second and so
on). At the beginning of each frame, synchronization bytes A1, A2 are
transmitted .
The multiplexing method of 4 STM-1 streams into a STM-1x4 is an interleaving
of the STM-1 streams to produce the STM-4 stream.
SDH Frame Structure
PAYLOAD CONTAINER
POH
RSOH
POINTER
MSOH
1 9 10 270
1
3
4
9
PAYLOAD CONTAINER: 9 (Rows) * 260 (Columns) * 64Kbps = 149.76 Mbps
POH: 9 (Rows) * 1 (Column ) * 64 Kbps = 0.576 Mbps
RSOH: 3 (Rows) * 9 (Columns) * 64 Kbps = 1.728 Mbps
MSOH: 5 (Rows) * 9 (Columns) * 64 Kbps = 2.880 Mbps
SDH Frame Structure
How Is The Frame Composed ?
PDH Payload = Container (C)
Administrative Unit Group +
Section Overhead (SOH) = SDH Frame
more than 1 Administrative Unit = Administrative Unit Group
biggest Tributary Unit Group = Administrative Unit (AU)
Tributary Unit Group + AU Pointer = Administrative Unit (AU)
more than 1 Tributary Unit = Tributary Unit Group (TUG)
Container + Path Overhead (POH) = Virtual Container (VC)
Virtual Container + TU Pointer = Tributary Unit (TU)
C-12 VC-12 TU-12
C-3 VC-3 TU-3
C-4
TUG-2
TUG-3
VC-4
AU-4
STM-1
X 3
X7
X1
X 3
X1
POINTERS
MULTIFLEXING
ADDITION OF OVERHEADS
ALIGNMENT
SDH Hierarchy - TUG Structure
R PCM-30 ( 32 Bytes)
R
R PCM-30 ( 32 Bytes)
R
R PCM-30 ( 32 Bytes)
R R PCM-30 ( 32 Bytes)
R
125ms
125ms
125ms
125ms
1.07 Frame Alignment
125 sec 125 sec 125 sec
125 sec
35 Bytes
1.08 Mapping
1.09 Aligning of VC-12s With TU-12s
s
s
s
s
1.10 Pointers
New Data Flag
Normal value-0110 (in active)
1001 (active)
SS bits
TU-2 00+10 bit pointer value (0 to 427)
TU-12 10+10 bit pointer value (0 to 139)
TU-11 11+10 bit pointer value (0 to 103)
1.11 SDH
Multiplexing Structure
Frame Structure
Pointer
SDH Multiplexing Structure (1)
X1
AUG-64
Poi nt er pr ocessi ng
Multiplexing
Aligning
Mapping
6312 kb/s
2048 kb/s
1544 kb/s C-11
C-12
C-2
34368 kb/s
44736 kb/s
139264 kb/s
C-3
VC-3 TU-3
TU-2
x 3
VC-2
VC-12
TU-12
VC-11
x 4
TU-11
x 1
C-4
TUG-2
x 7 x 7
TUG-3
x 1
x 3
AU-4 VC-4
VC-3 AU-3
x 3
x 1
AUG-1
C-4-4c
VC-4-256c AU-4-256c
C-4-16c
C-4-64c
C-4-256c
AUG-4
X1
AUG-256 STM-256
STM-64
STM-16
X1
STM-4
X1
STM-1
X1
STM-0
X1
VC-4-16c AUG-16
x 4
x 4
x 4
x 4
x 1
x 1
x 1
x 1
VC-4-64c AU-4-64c
AU-4-16c
VC-4-4c AU-4-4c
SDH Multiplexing Structure (2)
X1
AUG-64
Poi nt er pr ocessi ng
Multiplexing
Aligning
Mapping
6312 kb/s
2048 kb/s
1544 kb/s C-11
C-12
C-2
34368 kb/s
44736 kb/s
139264 kb/s
C-3
VC-3 TU-3
TU-2
x 3
VC-2
VC-12
TU-12
VC-11
x 4
TU-11
x 1
C-4
TUG-2
x 7 x 7
TUG-3
x 1
x 3
AU-4 VC-4
VC-3 AU-3
x 3
x 1
AUG-1
C-4-4c
VC-4-256c AU-4-256c
C-4-16c
C-4-64c
C-4-256c
AUG-4
X1
AUG-256 STM-256
STM-64
STM-16
X1
STM-4
X1
STM-1
X1
STM-0
X1
VC-4-16c AUG-16
x 4
x 4
x 4
x 4
x 1
x 1
x 1
x 1
VC-4-64c AU-4-64c
AU-4-16c
VC-4-4c AU-4-4c
Multiplexing Process of SDH
Example: 2 Mb/s to STM-4
TUG-3 HO POH TUG-3 TUG-3
1 2 3
C-12 LO POH
S
AU-4 PTR
pointer offset value
TU-1 PTR
C-12
VC-12
TU-12
TUG-3
VC-4
AUG-1
2.048Mb/s
TU-1 PTR
TUG-2
TUG-2
PDH
SOH
AU-4 PTR
1
1
VC-12
VC-12
1
VC-4
AU-4
AUG-4
AUG-4
STM-4
pointer offset value
2.048Mb/s
AUG-1 AUG-1 AUG-1 AUG-1
TU-1 PTR
2
TU-1 PTR
3
1
2
VC-12 1
3
VC-12
1
TUG-2
7
1 2 3 4
VC-4
STM-1 Frame Structure
5
3
R-SOH: Regenerator Section Overhead
M-SOH: Multiplex Section Overhead
1 2 3 5 6 7 8 4
( 1) ( 2) ( 9)
270 bytes
125 s
8 bits = 1 byte
270 columns
9
rows
125 s
( 1)
( 2)
( 9)
9 261
Payload Capacity
R-SOH
1 AU PTR
M-SOH
Byte Interleaved Multiplex and Frame Structure STM-N
STM-1 (AU-4) STM-N
N CBA N
NNN
STM-1
STM-1
AU-4
AAA
STM-1
BBB
CCC
STM-N
byte interleaved multiplexing
R SOH
M SOH
N
N
9 x N 261 x N
9 rows
125 s
STM-1
AU-4
AU-4
AU-4
CBA
AU PTRs
ABC NABC N
Pointer Function
R SOH
STM-4
Example:
2 Mb/s to STM-4 via AU-4
AU PTR
M SOH
VC-4(3)
VC-4(2)
VC-4(1)
VC-4 (4)
VC-12 (63)
63
2
1
2 M signal
(
)
V
C
4
P
O
H
TU12 PTR
TU-3 PTR area
POH
VC-12
POH
VC-12
POH
VC-12
AU-4 Pointer and Pointer Offset Number
N N N N S S D D D D D I I I I I
10 bits
H1 H2
H1 * * H2 * * H3H3H3
782 # #
521 # #
86 # #
435 # #
696 # #
87 # #
522 # #
# same number for 3 consecutive bytes
0 0 0
VC-4
Pointer Configuration
1 1 1
TU-12 Pointer and Pointer Offset Numbering
105
0
35
70
139
34
69
104
VC-12
TU-12
N N N N S S D D D D D I I I I I
10 bits
V1 V2
V1
V2
V3
V4
35 bytes
125 s
36 bytes
500 s
V1
V2
V3
V4
Pointer Structure
J2
Z6
K4
V5
V5
500 s
125 s
20
*
*In this case, pointer offset value is set
20(0000010100)
Pointer Renewal
( )
B
( )
A
B
A
STM-1
STM-N
delay
input signal
frame aligned signal
multiplexed signal
A B
STM-1
STM-1
STM-1
delay
AU-4 Justification (1)
N N N N S S I I I I I D D D D D
H1 H2
pointer value
1
4
9
Negative justification opportunity
(3 bytes)
Positive justification opportunity
(3 byte)
Negative justification control
invert five D-bits accept majority vote
Positive justification control
invert five I-bits accept majority vote
I : Increment bit
D : Decrement bit
N : New data flag bit
0 0 0
AU-4 Justification (2)
- Positive Justification -
n+1 n+1 n n n n-1
H1 H2 H3 H3 H3 1 1 Y Y
H1 H2 H3 H3 H3 1 1 Y Y
start of VC-4
pointer value (n)
pointer value (I bits inverted)
positive justification
start of VC-4 (new)
pointer value (n+1)
H1 H2 H3 H3 H3 1 1 Y Y
H1 H2 H3 H3 H3 1 1 Y Y
n+1 n+1 n n n n-1
n+1 n+1 n n n n-1
n+1 n+1 n n n n-1
Frame 1
Frame 2
Frame 3
Frame 4
125 s
250 s
375 s
500 s
AU-4 Justification (3)
- Negative Justification -
n-2 n-1
n+1 n+1
H1 H2 H3 H3 H3 1 1 Y Y
H1 H2 H3 H3 H3 1 1 Y Y
start of VC-4
pointer value (n)
pointer value (D bits inverted)
negative justification
start of VC-4 (new)
pointer value (n-1)
H1 H2 1 1 Y Y
H1 H2 H3 H3 H3 1 1 Y Y
n+1 n+1 n n n n-1
n+1 n+1 n n n
n+1 n+1 n n n n-1
Frame 1
Frame 2
Frame 3
Frame 4
125 s
250 s
375 s
500 s
n-1
n-2 n-1 n-1 n-1
n-1 n-1 n-2
n n n n-1 n-1 n-1 n-2
Overhead
Mapping
1.12 STM-1
STM-1 Frame Structure and SOH
RSOH
MSOH
AU PTR
STM-1 PAYLOAD
261 bytes 9 bytes
Section Overhead
9
r
o
w
s
AU Pointer(s)
RSOH
MSOH
}
}
: bytes reserved for national use
A1
A1 A1
A2 A2 A2 J0
B1 E1 F1
D1 D2 D3
B2 B2 B2 K1 K2
D4 D5 D6
D7 D8 D9
D10
S1 Z1 Z1 Z2 Z2 M1 E2
D11 D12
Function of SOH (1)
RDI ; Remote Defect Indication
(formerly FERF, Far End Receive
Failure)
REI ; Remote Error Indication
(formerly FEBE, Far End Block Error)
MS ; Multiplex Section
DCC ; Data Communication Channel
Framing (A1, A2)
Regenerator section trace (J0) regenerator section connection
check
Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/s
Order wire (E1) accessible at regenerators
(E2) accessible at multiplexers
User channel (F1) 64 kb/s clear channel
Error monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24N
APS signaling (K1,2) automatic protection switching
(K2) also used as MS-AIS and MS-RDI
Synchronization status (S1) indication of quality level
Section status reporting (M1) REI (count of BIP-24N) A1 A1 A1
A2 A2 A2 J0
B1 E1 F1
D1 D2 D3
B2 B2 B2 K1 K2
D4 D5 D6
D7 D8 D9
D10
S1 Z1 Z1 Z2 Z2 M1 E2
D11 D12
AU Pointer(s)
RSOH
MSOH
}
}
: bytes reserved for national use
Function of SOH (2)
Framing (A1, A2)
Regenerator section trace (J0) regenerator section connection check
Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/s
Order wire (E1) accessible at regenerators
(E2) accessible at multiplexers
User channel (F1) 64 kb/s clear channel
Error monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24N
APS signaling (K1,2) automatic protection switching
(K2) also used as MS-RDI
Synchronization status (S1) indication of quality level
Section status reporting (M1) REI (count of BIP-24N)
RDI ; Remote Defect Indication
(formerly FERF, Far End Receive Failure)
REI ; Remote Error Indication
(formerly FEBE, Far End Block Error)
MS ; Multiplex Section
DCC ; Data Communication Channel
A1 A1 A1 A2 A2 A2 J0
B1 E1 F1
D1 D2 D3
B2 B2 B2 K1 K2
D4 D5 D6
D7 D8 D9
D10
S1 Z1 Z1 Z2 Z2 M1 E2
D11 D12
AU Pointer(s)
RSOH
MSOH
; bytes reserved for national use
}
}
Section and Path Trace Method
RST MST HPT LPT RST LPT HPT MST
RST
J0: Section trace
VC-4 POH (J1: Path trace)
VC-3 POH(J1: Path trace)
VC-12(J2: Path trace)
Node A
RST: Regenerator Section Termination MST: Multiplex Section Termination
HPT: High Order Path Termination LPT: Lower Order Path Termination
Node -A Node -B
Path Trace : Used
Transmit path trace : 123-565656
Path Trace expected value
: ABCDEGF
Received value : ABCDEFG
Path Trace : Used
Transmit path trace : ABCDEFG
Path Trace expected value
: 123-565656
Received value : 123-565656
Node B
Section Trace(J0)
R
S
T
R
S
T
Node A
Node B
R
S
T
R
S
T
R
S
T
R
S
T
Node C
RST: Regenerator Section Termination
Terminated Section of
Section Trace
Terminated Section of
Section Trace
a
c
a
c
b
d
b
d
Principle of BIP 8
1
n
K
i
=
even - - - - - K=0
odd - - - - - K=1
B1 byte
# n
Block
# n+1
Block
1
1
2
1
* * * K
1
* * * 8
1
1
2
2
2
* * * K
2
* * * 8
2
1
i
2
i
* * * K
i
* * * 8
i
1
n
2
n
* * * K
n
* * * 8
n
1 2* * * **K* * * *8
1
+
0
P
1
optical power received during one bit
P
0
power received during a 0 bit without any system impairment
Corresponding electrical currents are given by R P
1
and RP
2
1
and
0
denote the noise standard deviations during a bit and a 0 bit respectively.
Usually the required BER are of the order of 10
-9
to 10
-15
BER(Stability
Test)
9.11 Forward Error Correction Testing
FEC is a key element of the OTN. OmniBER OTN generates
structured OTN frames and can also generate frame errors (after
calculated FEC).
Useful in validating the FEC functionality in new designs.
Add
Errors
Check for
No Errors
10.71Gb/s OTN
with mapped
SDH/SONET
10.71 Gb/s OTN
with mapped
SDH/SONET
G.709
DUT
Forward Error Correction
Improves the BER performance of an existing link without adding
signal power.
Increases the maximum span of a link, optimizing span
engineering parameters.
Improves the overall quality of the link by diagnosing link
problems early
FEC Generation - A 5 Step Process
The FEC code is generated in one OTN Frame row at a time.
Step 1: To ensure low-latency, each Frame Row is demuxed
into 16 individual sub-rows before FEC is generated.
Step 2: Blank FEC bytes are added to each sub-row.
Step 3: 16 sub-rows are independently connected to 16 FEC
encoders, FEC calculated and populated in blank FEC
bytes.
Step 4: 16 sub-rows are remultiplexed to the original row with
the addition of the newly generated FEC values.
Step 5: 4 rows = OTN Frame
4 Rows
16 Bytes 3808 Bytes 256 Bytes
82 kHz
4080 Bytes
2
FEC Generation - Step 1 (Frame Row De-Mux)
1 2 3 4 18 17 16 3824 19 33
1
3
16
17 33 49
18 50 34
3809
3824
32 48 64
Overhead
Payload
Row 1
Sub
Row 1
Sub
Row 16
Each Frame Row
(Overhead + Payload) is
demuxed into
16 individual sub-rows
before
FEC is generated.
FEC Generation - Step 2 (Add blank FEC bytes)
16 bytes 239 bytes
Sub
Row 1
Sub
Row 16
Blank FEC bytes are added to each sub-row.
16 blank
FEC
bytes
added
per sub-
row
FEC Generation - Step 3 (FEC Calculated and Added)
FEC Encoder 16
FEC Encoder 15
FEC Encoder 14
FEC Encoder 13
FEC Encoder 12
FEC Encoder 11
FEC Encoder 10
FEC Encoder 9
FEC Encoder 8
FEC Encoder 7
FEC Encoder 6
FEC Encoder 5
FEC Encoder 4
FEC Encoder 3
FEC Encoder 2
FEC Encoder 1
LIVE FEC
16 sub-rows are independently connected to 16 FEC encoders,
FEC calculated and populated in blank FEC bytes.
FEC Generation - Step 4
(Reconstitute original Frame row + FEC)
3824
Valid
FEC
1 2 3 4 18 17 16 19
Payload
OTU Frame
Row
Overhead
382
5
4080
16 sub-rows are remultiplexed to the
original row with the addition of the
newly generated FEC values.
MUX
Portable Product Positioning
2.5G 10G
OmniBER
718/725
Jitter Binary I/F
ATM
P.O.S
Overhead Sequences
OmniBER OTN
Rich O/H testing
Rear Connector Option
All channel testing
Upgrade to jitter
Upgrade to 40G
J2126A OTN
Light Weight
Low Cost
Field Focussed
Feature Set
All channel testing
F
a
c
t
o
r
y
F
i
e
l
d
J2127A
Light Weight
Low Cost
Field Focussed
Feature Set
All channel testing
9.12 Agilent TMI for Transmission Testing
SONET
SDH
1310
1550
PDH & T-Carrier Testing
Synchronous Electrical
Interfaces (52/155Mb/s)
Synchronous Binary
Interfaces
ATM
POS
Jitter/Wander
Detailed Mapping
Bulk Mapping
Service Disruption
718
719 720 725
Comments
SONET framing structures
Detailed ATM payload generation & analysis
Detailed POS payload generation & analysis
Comprehensive Jitter and Wander generation
and analysis
Structured payloads down to 56/64Kb/s
Concatenated payloads (bulk-filled VCn-c)
Automatic Protection Switching time with
realistic payloads
Electrical transmitter & receiver at 52/155Mb/s
Comprehensive test capability for 2,8,34,140Mb/s
and DS1(1.5Mb/s) / DS3(45Mb/s)
1550nm optics
Electrical (differential & single-ended) and
optical interfaces to 2.5G
SDH framing structures
1310nm optics
Agilent TMI for Transmission Testing
Omni BER-718
The Front Panel
VGA
Output
SMART
TEST
Pop Up
Menu Keys
Bright
Alarm
LEDs
Printer
Control
Keys
Large Colour
Display with
Single or Multi-
Windows Mode
Transmit, Receive
Results, Graphics
Menu Driven
Soft Keys
Lid Printer
Output
Cursor
Navigation
Keys
Omni BER-718 Features
1 - Smart Test, Smart Setup
Fast identification of signal types.fast test equipment set up.
Capture all results in one test period.
2 - APS/Service Disruption Technique, Accuracy
Only independent verification tester for linear APS switch mechanism.Ensures
correct operation and interoperability in the network.
3 - ATM/POS (Jitter, OC48c, Channelized)
Stresses packet processing H/W.Simulates live traffic.Gives more realistic
performance results.Less failures in the Network.
Single box solution to measure and characterize the speed of protection
switching time.
OmniBER 718 Interfaces
Optical
Interface
Multirate
Analyzer
Clock I/F
Jitter Tx
Transmit
Receive
Jitter Rx
Remote
control
Floppy Disk
Power
OmniBER OTN 2.5G
OmniBER OTN 2.5G
Multi-rate up to 2.5G
Ethernet mappings into SONET/SDH
GFP
LAPS
Mixed mappings
Contiguous concatenations of STS-3c, AU-4-2c,
AU-4-3c, AU-4-4c, AU-4-8c and AU-4-16c as well
as non-contiguous AU-3
Future upgrade-ability to
Virtual concatenation, LCAS and GbE physical
interface
OTN (OTU-1)
Upgrade of all the above features at 10G rate
OTN
OTN
SONET
SDH
GFP
LAPS
Ethernet
Agilents Next Generation SONET/SDH Test Solution
Ethernet
GFP (G.7041)/ LAPS(X.86)
SONET/SDH &
OTN (G.709)
The ONLY tester that provides insight into all the layers of a structured
signal
Resulting in
Comprehensive debug & reduced test
times,
Which Ensures
Interoperability & standards compliance
saurabh.srivastava@vsnl.co.in