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Timingdiagram 1

Timing diagrams graphically represent the execution time of instructions. The 8085 microprocessor has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write cycles. Each cycle takes multiple clock periods called T-states. The opcode fetch cycle brings the instruction opcode from memory in 4 T-states. The memory read cycle reads data from memory in 3 T-states. The memory write cycle writes data to memory by placing the accumulator contents on the data bus during the last T-state.

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92 views14 pages

Timingdiagram 1

Timing diagrams graphically represent the execution time of instructions. The 8085 microprocessor has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write cycles. Each cycle takes multiple clock periods called T-states. The opcode fetch cycle brings the instruction opcode from memory in 4 T-states. The memory read cycle reads data from memory in 3 T-states. The memory write cycle writes data to memory by placing the accumulator contents on the data bus during the last T-state.

Uploaded by

Jit Jag
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Timing Diagram is a graphical representation.

It represents the execution time taken


by each instruction in a graphical format. The execution time is represented in T-
states.

Instruction Cycle:
The time required to execute an instruction is called instruction cycle.

Machine Cycle:
The time required to access the memory or input/output devices is called machine
cycle.

T-State:
•The machine cycle and instruction cycle takes multiple clock periods.
•A portion of an operation carried out in one system clock period is called as T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1.Opcode fetch cycle (4T)


2.Memory read cycle (3 T)
3.Memory write cycle (3 T)
4.I/O read cycle (3 T)
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5.I/O write cycle (3 T)
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Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch cycle.
– In this cycle, the microprocessor brings in the instruction’s
Opcode from memory.
• To differentiate this machine cycle from the very similar
“memory read” cycle, the control & status signals are set as
follows:
– IO/M=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in an
opcode fetch machine cycle.

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Memory Read Machine Cycle
• The memory read machine cycle is exactly
the same as the opcode fetch except:
– It only has 3 T-states
– The s0 signal is set to 0 instead.

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The Memory Read Machine Cycle
– To understand the memory read machine cycle, 2000H
let’s
3E
study the execution of the following instruction:
2001H 32
• MVI A, 32
– In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading
a byte into the accumulator (MVI A), the second byte
is the data to be loaded.
– The 8085 needs to read these two bytes from memory
before it can execute the instruction. Therefore, it will
need at least two machine cycles.
– The first machine cycle is the opcode fetch
discussed earlier.
– The second machine cycle is the Memory Read
Cycle. Tressa Michael
The Memory Read Machine Cycle
– To understand the memory read machine cycle, 2000H
let’s
3E
study the execution of the following instruction:
2001H 32
• MVI A, 32
– In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading
a byte into the accumulator (MVI A), the second byte
is the data to be loaded.
– The 8085 needs to read these two bytes from memory
before it can execute the instruction. Therefore, it will
need at least two machine cycles.
– The first machine cycle is the opcode fetch
discussed earlier.
– The second machine cycle is the Memory Read
Cycle. Tressa Michael
The Memory Write Operation
• In a memory write operation:
– The 8085 places the address on the address bus
– Identifies the operation as a ‘memory write’ (IO/M=0,
s1=0, s0=1).
– Places the contents of the accumulator on the data
bus and asserts the signal WR.
– During the last T-state, the contents of the data bus
are saved into the memory location.

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MVI B, data

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8085 timing diagram for Opcode fetch cycle for MOV C, A .

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8085 timing diagram for Opcode fetch cycle for MOV C, A .
INR M

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ADD M

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STA addr

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IN Byte

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