BENC 4453 :

COMPUTER
ARCHITECTURE
Electronic Memory
“ Computing is a wild dance
between central processing
unit (CPU) and memory.

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 Electronic Memory
● Instructions in memory are fetched and CPU executes
them.

● To execute instructions, CPU reads data from memory,

changes it and writes back

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“ To understand this dance
you need an understanding
of both the CPU and
Memory.

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 Electronic Memory
● Mistake to consider CPU as a star of the show.

● Then who is the star?

● Memory – is simpler and less diverse technology. Storing

data from CPU and hand it back upon request as quick as
possible makes the CPU the star.

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“ Rotating Magnetic Memory
– Loud and prone to
vibration

1955 – memory without

moving parts arrived.

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 Magnetic Core
Memory
● Magnetic core memory systems use tiny toroidal
(ring-shaped) magnetic beads called cores.

● The cores are made of an exotic iron oxide with

high remanance (the ability to retain a magnetic
field over time) and low coercitivity (the energy
required to change the magnetic field).

● One core is capable of storing 1 bit.

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Magnetic Core
Memory

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Magnetic Core
Memory
● The state of any given bit is represented not by the
presence or absence of a magnetic field but by its
orientation.

● A core’s magnetic field can exist in

two different orientations, which by convention are
called clockwise and counterclockwise

● The state of a bit is changed by “flipping” its core’s

magnetic field from clockwise to counterclockwise, or
vice versa.

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Magnetic Core
Memory
● The toroidal cores are woven into a rectangular
matrix of very fine wire supported by a sheet
of circuit board material.

Each assembly is called a plane. Four wires pass

through the centre
hole of every core.

■ An x wire, which provides one dimension to select a core from a

plane
■ A y wire, which provides the second dimension to select a core
from a plane
■ A sense wire, which allows the system to read the magnetic
state of a core
■ An inhibit wire, which allows the system to set the state of a
core
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Magnetic Core
Memory
● The x and y wires are used to select one core from the
grid of cores in a plane, just as x and y
values select one point in a Cartesian plane from
geometry.

● A current is passed through the

x and y wires that both pass through the core to be
selected.

● Each of the two wires carries

enough current to generate half of the magnetic field
required to flip the core.

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Magnetic Core
Memory
● Thus, the core
through which both wires pass is given enough of a
magnetic pulse to change its orientation.

● The direction of the current passing through the x and y

wires determines the orientation.

● Passing the current one way imposes a 0-state on the

core. Passing the current the other way
imposes a 1-state on the core.

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Static Random Access Memory
(SRAM)
● Intel’s TTL 64-bit 3101 chip and Intel’s 256-bit 1101 chip
were static random access memory (SRAM) devices.

● They were random access because a single bit could be

accessed “at random” without any need to wait on
sequential access or sift through other bits.

● They were static because bits written to the chips would

remain in their written state as long as the chips had
power—even if the computer’s clock
was slowed or stopped.

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Static Random Access Memory
(SRAM)
● The basic logic element in SRAM chips is the flip-flop.

● A flip-flop is a logic circuit with an

output that can be in one of two states, and that can be
switched from one state to the
other by a pulse or voltage change on an input.

● It will hold that state until another pulse

switches it to its opposite state, or until power is
removed from the circuit.

● Because it has
two states, and because binary digits have two possible
values, a flip-flop can “remember” a
single bit.
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Static Random Access Memory
(SRAM) ● A typical SRAM cell is made up of six
MOSFETs.

● Each bit in an SRAM is stored on

four transistors (M1, M2, M3, M4) that
form two cross-coupled inverters.

● This storage cell has two stable states

which are used to denote 0 and 1.

● Two additional access transistors
serve to control the access to a
storage cell during read and write
operations.
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Static Random Access Memory
(SRAM) ● Access to the cell is enabled by the
word line (WL in figure) which controls
the two access transistors M5 and
M6 which, in turn, control whether the
cell should be connected to the bit
lines: BL and BL.

● They are used to transfer data for both

read and write operations. 

● Although it is not strictly necessary to

have two bit lines, both the signal and
its inverse are typically provided in
order to improve noise margins. 
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SRAM - Operation
● An SRAM cell has three different states: standby (the circuit is
idle), reading (the data has been requested) or writing (updating the
contents).

● Standby
○ If the word line is not asserted, the access transistors M5 and
M6 disconnect the cell from the bit lines. The two cross-coupled
inverters formed by M1 – M4 will continue to reinforce each other as
long as they are connected to the supply.

● Reading
○ In theory, reading only requires asserting the word line WL and
reading the SRAM cell state by a single access transistor and bit line,
e.g. M6, BL. However, bit lines are relatively long and have large
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parasitic capacitance.
SRAM - Operation
● Reading
○ The read cycle is started by precharging both bit lines BL and BL*, i.e.,
driving the bit lines to a threshold voltage (midrange voltage between
logical 1 and 0) by an external module (not shown in the figures).

○ Then asserting the word line WL enables both the access transistors
M5 and M6, which causes the bit line BL voltage to either slightly drop
(bottom NMOS transistor M3 is ON and top PMOS transistor M4 is off) or
rise (top PMOS transistor M4 is on).

○ If the BL voltage rises, the BL* voltage drops, and vice versa.

○ Then the BL and BL* lines will have a small voltage difference between

them.
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SRAM - Operation
● Writing
○ The write cycle begins by applying the value to be written to the bit
lines.

○ If we wish to write a 0, we would apply a 0 to the bit lines, i.e.
setting BL to 1 and BL to 0.

○ A 1 is written by inverting the values of the bit lines.

○ WL is then asserted and the value that is to be stored is latched in. 

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Address Lines and Data Lines
● Address Lines
○ used to select
which memory location is to be read or
written to.

● Data Lines
○ carry data either out of the
system, when a value is read, or into the
system, when a value is written.

● Control Lines
○ These have various functions, the most
important of which is to specify whether a
selected memory location is to be read
from or
written to.
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Memory Chip Addresses Cell
● Each cell holds a single binary digit, which
may be either a 1 or a 0.
● A decoder is a logic element that accepts a
binary number as an input value and uses it
to select one, and only one, of several output
lines.
● Each decoder accepts a 3-bit binary number
and selects one of eight output lines.
● The state of the read/write control line
determines whether the selected cell will
be read from or written to.
● When the control line is set to 0, a read is
performed and whatever value is stored in
the selected cell is placed on the data line.
● When the control line is set to 1, a write is
performed and whatever value is on the data
line is written to the 21
“
1972 - Intel’s ground-breaking 8008
CPU - pulling an 8-bit byte out of a
memory chip

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Combining Memory Chips
into Memory Systems
● Each 2102 chip stores 1,024 bits.
● The 2102’s 10 address lines are
connected in parallel, so all 10
address lines connect to all eight
chips.
● An address placed on the address
lines will select the corresponding
bit in each chip.
● That bit will be delivered to each
chip’s data pin.

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Combining Memory Chips
into Memory Systems
● A full 8-bit byte will be available on
the row of 10 data pins with only
one read from memory.

● To access a single byte from among

the 1,024, the value placed on the
address bus must be able to
express values from 0 to 1,023 in
binary. 1,023 in binary is
1111111111.
● The eight data lines form the data
bus.
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Dynamic Random Access Memory
(DRAM) ● DRAM memory chips are based on two-
dimensional arrays of memory cells.
● Cells are addressed by x and y coordinates,
using address decoders (look back at
Figure 3-2).
● Each individual cell consists of a single
MOS transistor and a single capacitor, as
shown in Figure 3-4.
● The three connections to the transistor are
well known to electronics hobbyists: the
gate is an electrical switch toggle that
either connects the source to the drain or
insulates them from each other.
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Dynamic Random Access Memory
(DRAM) ● DRAM memory chips are based on two-
dimensional arrays of memory cells.
● Cells are addressed by x and y coordinates,
using address decoders (look back at
Figure 3-2).
● Cells are organized into rows and columns.
● A row (the horizontal dimension in Figure 3-
4) is linked by a common connection to all
cell transistor gates called a word line.
● The word line is used to select one row
from all rows in the memory chip.

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Dynamic Random Access Memory
(DRAM) ● It “flips the switch” of all the MOS
transistors in a row at once, causing them
to either conduct or not conduct.

● Cells in each column are linked by a

common connection to all transistor drain
leads, called a bit line.

● At the end of each column’s bit line is a

sense amplifier, which allows an almost
unimaginably
small unit of charge to be reliably
interpreted as a 1 or a 0.
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Dynamic Random Access Memory
(DRAM)
● An MOS transistor is a solid-state switch. When the transistor is
switched on, the capacitor is electrically connected to the bit line.

● When a cell’s transistor is switched off, the capacitor is isolated and

charge (or lack of charge) is retained inside the capacitor.

● The charge leaks away in a fraction of a second unless the cell is

refreshed.

● DRAM operation has a familiar resemblance to the operation of core

memory.
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Read from a DRAM cell
● The cell’s bit line must be given an initial voltage (a precharge) that places
it precisely halfway between a full charge on the capacitor and complete
discharge.

● When the precharge is complete, the precharge circuitry is disconnected

and the bit line is switched to the sense amplifier.

● The cell’s word line is selected. This turns on the MOS transistor of the
selected cell (as well as all the other cells in the row) and connects the
capacitor to the bit line.

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Read from a DRAM cell
● The capacitor’s charge state affects the voltage on the bit line. If the
capacitor has been charged, the bit line’s voltage goes up slightly. (Very
slightly!) If the capacitor has been discharged, the bit’s line’s voltage goes
down slightly. This change in voltage is exceptionally small and could
amount to the difference of only one million electrons.

● The sense amplifier converts this tiny change in voltage to a digital state of
either 1 or 0.

● The read operation destroys charge in the capacitor of the selected cell and
all the other cells in the row. The state that was read must then be
refreshed and written back to all cells in the row.

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Writing to a DRAM cell
● The cell’s bit line is given a voltage corresponding to the value to be written
to the cell. Typically, a 1-bit is represented by full voltage and a 0-bit by no
voltage.

● The cell’s word line is selected. This turns on the MOS transistor and allows
the voltage applied to the bit line to pass into the cell’s capacitor.

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“Note - DRAM cells are not accessed
one at a time.
Because they share a word line, an
entire row of cells is accessed at once.

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“Opening” a row
● Reading the values from an entire row of cells into temporary storage at the
edge of the SDRAM chip.

“Closing” a row
● Writing back any changes from the temporary storage to the cells
themselves.

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“ In modern computers, system
memory is almost always read and
written in chunks called cache lines,
which are maintained in fast memory
stores called cache .

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DRAM Refresh State
● A row is refreshed under two circumstances:

○ Any time a cell in that row is read

○ Every 5 to 50 milliseconds, to prevent electron leakage from

destroying cell data

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DRAM Refresh State
● Rows are refreshed simply by reading the state of the cells in the row and
then immediately writing it back to the cells.

● This reading and writing is not done through the CPU, or in fact with any
involvement of the CPU at all.

● A separate subsystem called a memory controller handles the refresh

operation and a great many other housekeeping details that allow the CPU
to access memory with as little delay as possible.

● Taken together, the memory controller and the DRAM chips that it manages
are called a memory system.

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DRAM Speed
● The speed with which data moves between memory systems and the CPU
can dominate the overall performance of the entire computer.

● Memory system performance is a complex business, with two different

metrics that are often in tension with one another:
○ Access time: The time it takes between the moment a memory
access is requested by the CPU and the time the access is completed.
○ Bandwidth: The amount of data transferred to or from memory per
unit time

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“
SDRAM – First Generation – Referred
as Single Data Rate

SDRAM – SDR vs DDR?

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DDR, DDR2 DDR3 and DDR4
SDRAM ● SDR SDRAM is called “single data rate”
because
it can transfer a single data word per clock
cycle.

● SDR technology, a memory transfer happens

on the rising edge of each clock cycle.

● DDR SDRAM, two memory transfers occur for

each clock cycle.

● In DDR, memory transfers happen on both the

rising edge and the falling edge of each clock
cycle, essentially doubling the rate at which 39
DDR, DDR2 DDR3 and DDR4
SDRAM
● Why DDR and it successors DDR2 and DDR3?

● Is to require that memory accesses occur as short bursts running from a

starting address to some number of adjacent addresses.

● After the internal logic in the SDRAM has read the first column,
subsequent columns from the same row are available for “free” without
requiring another time-consuming access to the array.

● This process is called prefetching. (See Figure 3-7.)

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DDR, DDR2 DDR3 and DDR4
SDRAM ● With 32-bit SDR memory you could
efficiently read a single 32-bit word,
followed by another 32-bit word from
another location in memory, but DDR
forces you to take two adjacent 32-bit
words, one on the rising edge and one
on the falling edge of the clock cycle.

● DDR2 doubles this requirement to four

adjacent words and supports data
rates up to 800MHz.

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DDR, DDR2 DDR3 and DDR4
SDRAM ● DDR3 doubles the requirement again
to eight words and supports data
rates of 1.6GHz or higher.

● DDR generation has included

changes to the physical signaling
scheme aimed at increasing transfer
speeds and a reduction in operating
voltage, which reduces power draw
and waste heat.

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DDR, DDR2 DDR3 and DDR4
SDRAM ● The improvement is significant: DDR3
memory uses 30 percent less power
than DDR2 memory.

● DDR4. The operating voltage has

been reduced to 1.2V (as compared to
1.5V for DDR3) enabling higher-
density modules with greater transfer
speeds.

● The range of operating frequencies

increased, to 800 to 1600MHz,
compared to 400 to 1067MHz for
DDR3.
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Error-Correcting Code (ECC)
Memory ● If you look at modern DIMMs, particularly
those intended for use in servers or other
high reliability applications, you may
notice that there are sometimes nine
chips on each side.

● Even if there are only eight chips, there

will probably be an empty space with
printed circuit pads for a ninth chip.

● The ninth chip has an optional but very

useful function: error correction.

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Error-Correcting Code (ECC)
Memory ● Error-Correcting Code (ECC) memory was
developed to prevent memory corruption
from background radiation.

● The mechanism used in modern

computer memory, called a Hamming
code, was developed in 1950 by Richard
Hamming.

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Thanks!
Any questions?

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