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Direct Memory Access (Dma)

Direct memory access (DMA) allows data to be transferred between computer resources like I/O devices and memory without involvement of the CPU. A DMA controller handles the data transfer by requesting and gaining control of system buses from the CPU. It then uses address/data buses and read/write signals to move data between memory and I/O devices or between memory locations. DMA improves system performance by freeing the CPU while transferring data in the background.

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316 views14 pages

Direct Memory Access (Dma)

Direct memory access (DMA) allows data to be transferred between computer resources like I/O devices and memory without involvement of the CPU. A DMA controller handles the data transfer by requesting and gaining control of system buses from the CPU. It then uses address/data buses and read/write signals to move data between memory and I/O devices or between memory locations. DMA improves system performance by freeing the CPU while transferring data in the background.

Uploaded by

Hyma Prasad Gelli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIRECT MEMORY

ACCESS (DMA)
DMA
• A direct memory access (DMA) is an operation in which
data is copied(transported) from one resource to
another resource in a computer system without the
involvement of the CPU.
• The task of a DMA-controller (DMAC) is to execute the
copy operation of data from one resource location to
another. The copy of data can be performed from:
• - I/O-device to memory
• - memory to I/O-device
• - memory to memory
• - I/O-device to I/O-device
I/O Data Transfer
CPU bus signals for DMA transfer

ABUS
BG
DBUS

CPU High-Impedance
(disable) when
BG is enabled
RD
BR
WR

BG  BUS GRANT ABUS  ADDRESS BUS RD  READ

BR  BUS REQUEST DBUS  DATA BUS WR  WRITE


What these symbols indicates...
BUS REQUEST (BR)  The bus request input is used by the DMA controller
to
request the CPU to relinquish the control of the memory buses.

BUS GRANT (BG)  The CPU activates the bus grant output to inform the
external DMA and the buses are in the high-impedance state.

DATA BUS (DBUS)  It is used to store the data or information in the CPU
from peripheral devices through DMA.

ADDRESS BUS (ABUS)  It is used to store the base address of the data
to be sent to the CPU through DMA.

READ (RD)  It is used to read the data stored in the Source or from the
Destination file.

WRITE (WR)  It is used to write the data stored in the Source or to the
Destination file.
DMA in Computer System
 A DMA controller implements direct memory access
in a computer system.

 It connects directly to the I/O device at one end and


to the system buses at the other end. It also interacts
with the CPU and I/O both via the system buses and
two new direct connections.

 It is sometimes referred to as a channel. In an


alternate configuration, the DMA controller may be
incorporated directly into the I/O device.
Data Transfer using DMA Controller

 To transfer data from an I/O device to memory, the


DMA controller first sends a Bus Request to the CPU
by setting BR to 1. When it is ready to grant this
request, the CPU sets it’s Bus grant signal, BG to 1.

 The CPU also tri-state it’s address, data, and control


lines thus truly granting control of the system buses
to the DMA controller.

The CPU will continue to tri-state it’s outputs as long


as BR is asserted.
Internal Configuration of DMA
Controller
 The DMA controller includes several registers :-

 The DMA Address Register contains the memory address to be used in


the data transfer. The CPU treats this signal as one or more output ports.

 The DMA Count Register, also called Word Count Register, contains the
number of bytes of data to be transferred. Like the DMA address register,
it too is treated as an O/P port (with a different address) by the CPU.

 The DMA Control Register accepts commands from the CPU. It is also
treated as an O/P port by the CPU.

 The DMA Data Register are used to store intermediate data values and
result when any arithmetic operation is performed.
Internal Configuration
Process of DMA Transfer
 To initiate a DMA transfer, the CPU loads the
address of the first memory location of the
memory block (to be read or written from) into the
DMA address register.

 It then writes the number of bytes to be


transferred into the DMA count register in the
same manner.

 Finally, it writes one or more commands to the


DMA control register.
BASIC DMA TERMINOLOGY

DMA channel: system pathway used by a


device to transfer information directly to and
from memory. There are usually 8 in a
computer system
DMA controller: dedicated hardware used for
controlling the DMA operation
Single-cycle mode: DMA data transfer is done
one byte at a time
Burst-mode: DMA transfer is finished when
all data has been moved
SUMMARY
• Advantages of DMA:
– Computer system performance is improved
by direct data transfer between memory and
I/O devices, bypassing the CPU.
– CPU is free to perform operations that do not
use system buses.

• Disadvantages of DMA:
– In case of Burst Mode data transfer, the CPU
is rendered inactive for relatively long
periods of time.
– It takes more power, more money and has
less speed as compared to CPU Cost of
• Used in disk controllers, video/sound cards etc, or
between memory locations
THANK YOU

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