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D2A1-1-3-DV VCD Based Power Signoff

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Raj Shekhar Reddy
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238 views17 pages

D2A1-1-3-DV VCD Based Power Signoff

hi

Uploaded by

Raj Shekhar Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Value Change Dump (VCD) based

Power Signoff Methodology

Poornima K Prahlada, Raghavendra HD,


Manikandan P
NXP Semiconductors India

© Accellera Systems Initiative 1


Agenda
• Introduction - Representative SoC & Traditional
power signoff methodology
• Power Dip Issue
• IR Drop Improvement
• VCD Dump
• VCD based dynamic analysis flow
• Recommendations
• Conclusions

© Accellera Systems Initiative 2


Representative SoC & Traditional
power signoff methodology

© Accellera Systems Initiative 3


Power Dip Issue
• During bring up validation, Killer application crash
was observed while running the system at set target
speed

© Accellera Systems Initiative 4


Power Dip Issue (contd..)
Cycle with worst power -
0.85106 W

© Accellera Systems Initiative 5


Choosing the right VCD
(switching instances highlighted in Yellow color)
Real Use case VCD
VCD before tapeout Total Total (unknown, identified post tapeout)
power power
375mW 851mW

Clock Clock
DSP1 DSP1
256Mhz only only 256Mhz
80mW power power 404mW

151mW 227mW
Memories
Memories 43mW
28mW Worst IR
drop 122 mV
CORE + DSP2
256Mhz 263mW CORE + DSP2
256Mhz 346mW

Worst IR
drop 70 mV

© Accellera Systems Initiative 6 6


IR Drop Improvement – Use Case 1
VCD (Typical Corner)
Improved result

IR drop numbers IR drop numbers After List of implementation changes


before design improvements
improvements
122 mV 77.2 mV Additional power pad
Additional AP stripes(horizontal & Vertical)
Additional M2 & M5 in the channel area
Additional M5, M6 & M7 in the notch area

© Accellera Systems Initiative 7


IR Drop Improvement – Use Case 2
VCD Improved
(Slowresult
Corner)

IR drop IR drop numbers List of implementation changes


numbers before After design
improvements improvements

159 mV 134 mV Power pad addition


Power grid improvement near
the new pads

© Accellera Systems Initiative 8


VCD dump
•Use case selection alignment from system team to I&V team
─Define clear use case content
─Define pass/fail criteria for use case
─Execution of use case on the FPGA/tested

•Full data path use case simulation with back annotated netlist
─Realistic algorithm on processors
─Extensive memory accesses and IO operations exercised
─All sub-system/IP’s active

•Max application frequency targeted (for example, 256 MHz for


DSP2/DSP1)

•Choose appropriate corners (WC, BC, TYP) for simulation

© Accellera Systems Initiative 9


VCD dump (contd…)
• Limitations
– One-to-one use case match (simulation environment)
– Pseudo worst case simulation infrastructure
– 100% power signoff guarantee from use case
– Power analysis tool for handling larger activity dumps

• Recommendations
– Extrapolating the RTL VCD information to SDF Netlist
– FPGA based power estimation (to be explored)

© Accellera Systems Initiative 10


VCD based Dynamic Power
Analysis Methodology
Dynamic
Analysis

VCD Based Vectorless

RTL VCD Gate level VCD

Cycle Selection
© Accellera Systems Initiative 11
VCD based Dynamic Power
Analysis Methodology (contd..)
Design setup

Perform cycle selection


(Worst power cycle)

Perform power calculation

Perform PG extraction

Perform Analysis (with VCD)

© Accellera Systems Initiative 12


Redhawk Data Preparation
Physical data Redhawk Specific
Redhawk Tech File
DEF & SPEF
APL model files
GDS File
GSR file
SDC file

VCD file

Pkg File
REDHAWK

REPORTS
Power
IR Drop
DECAP

13
Power Reduction using Calypto
• 70 mW power reduction of which 54 mW reduction in DSP1
• Increase in 7K instances (clock gating cells) with Calypto
• Switching activity 10%

Calypto

Non-
Calypto
Calypto Non Calypto

Total Power 690.6 759.6


40% average power
DSP1 Power 82.54 136.3 reduction
Instance count 1577678 1570795

© Accellera Systems Initiative 14


Power Artiste RTL average power
details using VCD

RTL average power is ~305mW for entire VCD duration

© Accellera Systems Initiative 15


CONCLUSIONS
• Generate multiple high activity VCD
– Early identification of high activity use cases aligning with
system and application
• Power analysis is insufficient at typical corner
• Run dynamic power analysis with all VCDs in Slow and Typical
corners (considering Worst temperature)
• Perform early power analysis based on VCD
– Create power grid based on the results
– Design changes
• VCD based analysis as signoff along with static analysis signoff
• Use of RTL power estimation and power improvement tools
like Power Artiste and Calypto

© Accellera Systems Initiative 16


Questions

© Accellera Systems Initiative 17

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