Designing For Low Power

Why Power Matters

 Packaging costs
 Chip and system cooling costs
 System reliability
 Battery life (in portable systems)
 Environmental concerns
 Office equipment accounted for 17% of total US commercial
energy usage
Why worry about power? -- Power Dissipation

Lead microprocessors power continues to increase

100

P6
Pentium ®
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

Source: Borkar, De Intel
 Why worry about power? -- Chip Power Density

Sun’s
10000 Surface
Rocket
Power Density (W/cm2)

1000 Nozzle
Nuclear …chips might become hot…

100 Reactor

8086 Hot Plate

10 4004 P6
8008 8085 386 Pentium®
286 486
8080
1
1970 1980 1990 2000 2010
Year
Source: Borkar, De Intel
Chip Power Density Distribution
Al-SiC+ Epoxy Die Attach
Power
WillametteMap
Power Distribution
On-Die Temperature
250 110

100
200
200-250

Temperature (C)
Heat Flux (W/cm2)
90
150-200
150 100-150 80
50-100
70
100 0-50

60
50
50

0 40

 Power density is not uniformly distributed across the chip

 Silicon is not a good heat conductor
 Max junction temperature is determined by hot-spots
 Impact on packaging, w.r.t. cooling
Why worry about power ? -- Battery Size/Weight
50
Rechargable Lithium

Nominal Capacity (W-hr/lb)

40

Ni-Metal Hydride
30

20
Nickel-Cadmium
Battery
(40+ lbs) 10

0
65 70 75 80 85 90 95

Year

Expected battery lifetime increase

over the next 5 years: 30 to 40% From Rabaey, 1995
Why worry about power? -- Standby Power
Year 2002 2005 2008 2011 2014
Power supply Vdd (V) 1.5 1.2 0.9 0.7 0.6
Threshold VT (V) 0.4 0.4 0.35 0.3 0.25

 Drain leakage will increase as VT decreases to maintain noise

margins and meet frequency demands, leading to excessive
battery draining standby power consumption.
50%
8KW
…and phones leaky!
40% 1.7KW
Standby Power

30% 400W

20%
88W
12W
10%

0%

2000 2002 2004 2006 2008 Source: Borkar, De Intel

Power and Energy Figures of Merit
 Power consumption in Watts
 determines battery life in hours

 Peak power
 determines power ground wiring designs
 sets packaging limits
 impacts reliability

 Energy efficiency in Joules

 rate at which power is consumed over time

 Energy = power * delay

 Joules = Watts * seconds
 lower energy number means less power to perform a
computation at the same frequency
Power versus Energy

Power is height of curve

Watts Lower power design could simply be slower
Approach 1

Approach 2

time
Energy is area under curve
Watts Two approaches require the same energy
Approach 1

Approach 2

time
PDP and EDP
 Power-delay product (PDP) = Pav * tp = (CLVDD2)/2
 PDP is the average energy consumed per switching event
(Watts * sec = Joule)
 lower power design could simply be a slower design
 Energy-delay product (EDP) = PDP * tp = Pav * tp2
15
 EDP is the average energy

Energy-Delay (normalized)
consumed multiplied by the energy-delay
computation time required
10
 takes into account that one
can trade increased delay
for lower energy/operation energy
(e.g., via supply voltage 5
scaling that increases delay,
but decreases energy delay
consumption)
0
0.5 1 1.5 2 2.5
 allows one to understand tradeoffs better Vdd (V)
CMOS Energy & Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD

Ileakage

f01 = P01 * fclock

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic Short-circuit Leakage
power power power
Dynamic Power Consumption
Vdd

Vin Vout

CL

f01
Energy/transition = CL * VDD2 * P01

Pdyn = Energy/transition * f = CL * VDD2 * P01 * f

Pdyn = CEFF * VDD2 * f where CEFF = P01 CL

Data dependent - a function of switching activity!

Lowering Dynamic Power

Capacitance: Supply Voltage:

Function of fan-out, Has been dropping
wire length, transistor with successive
sizes generations

Pdyn = CL VDD2 P01 f

Activity factor: Clock frequency:

How often, on average, Increasing…
do wires switch?
Dynamic Power as a Function of VDD
 Decreasing the VDD 5.5
decreases dynamic 5
energy consumption 4.5
(quadratically) 4
3.5
 But, increases gate 3
delay (decreases 2.5
performance) 2
1.5
1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
VDD (V)
 Determine the critical path(s) at design time and use high
VDD for the transistors on those paths for speed. Use a
lower VDD on the other gates, especially those that drive
large capacitances (as this yields the largest energy
benefits).
Short Circuit Power Consumption

Vin Isc Vout

CL

Finite slope of the input signal causes a direct

current path between VDD and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Leakage (Static) Power Consumption

VDD Ileakage

Vout
Drain junction
leakage

Gate leakage Sub-threshold current

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

Leakage as a Function of VT
 Continued scaling of supply voltage and the subsequent
scaling of threshold voltage will make subthreshold
conduction a dominant component of power dissipation.

10-2
 An 90mV/decade VT
roll-off - so each
255mV increase in
VT gives 3 orders of
ID (A)

10-7 magnitude reduction

in leakage (but
VT=0.4V
adversely affects
VT=0.1V
performance)
10-12
0 0.2 0.4 0.6 0.8 1
VGS (V)
Exponential Increase in Leakage Currents

10000

1000
0.25
Ileakage(nA/m)

0.18
100
0.13
0.1
10

1
30 40 50 60 70 80 90 100 110
Temp(C)

From De,1999
Leakage as a function of VT

 Reducing VT increases
the sub-threshold
leakage current

ID (A)
(exponentially)
 But, reducing VT
VT=0.4V
decreases gate delay VT=0.1V

 Leakage is reduced by 0 0.2 0.4 0.6 0.8 1

negative VGS VGS (V)
 Determine the critical path(s) at design time and use low
VT devices on the transistors on those paths for speed.
Use a high VT on the other logic for leakage control.
Review: Energy & Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD

Ileakage

f01 = P01 * fclock

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic power Short-circuit Leakage power
(~50% today and power (~50% today
decreasing Negligible) and increasing)
relatively)
Dynamic Power as a Function of Device Size
 Device sizing affects dynamic energy consumption
 gain is largest for networks with large overall effective fan-outs (F
= CL/Cg,1)
 The optimal gate sizing factor 1.5
(f) for dynamic energy is
smaller than the one for F=1

normalized energy
performance, especially for F=2
1
large F’s
 e.g., for F=20, F=5
fopt(energy) = 3.53 while
fopt(performance) = 4 0.5
F=10
 If energy is a concern avoid F=20
oversizing beyond the
0
optimal 1 2 3 4 5 6 7
f

From Nikolic, UCB