Data and Computer

Communications

Tenth Edition
by William Stallings

Data and Computer Communications, Tenth

Edition by William Stallings, (c) Pearson
Education - Prentice Hall, 2013
 CHAPTER 6

Error Detection and Correction

 “Redundancy is a property of languages, codes
and sign systems which arises from a superfluity of
rules, and which facilitates communication in spite of
all the uncertainty acting against it.
Redundancy may be said to be due to an
additional set of rules, whereby it becomes
increasingly difficult to make an undetectable
mistake.”
—On Human Communication,
Colin Cherry
 Types of Errors
 An error occurs when a bit is altered between
transmission and reception
 Binary 1 is transmitted and binary 0 is received
 Binary 0 is transmitted and binary 1 is received
 Sent
0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 0 1
bits corrupted by error

0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1
Received single-b it
bursterror of
length B =10 erro r

Figure 6.1 Burst and Single-Bit Errors

 Error Detection
 Regardless of design you will have errors, resulting in the change of one or more bits in a
transmitted frame

 Frames
 Data transmitted as one or more contiguous sequences of bits

 The probability that a frame arrives with no bit errors decreases when the probability of a single bit
error increases

 The probability that a frame arrives with no bit errors decreases with increasing frame length
 The longer the frame, the more bits it has and the higher the probability that one of these is in
error
 k bits

data data'

E = f(d a ta ) E' =f(data') COMPARE

Receiver
data

n – k bits E , E ' = er r o r -d etec tin g c o d es

f = er r o r -d etec tin g c o d e fu n c tio n
n bits

Transmitter

Figure6.2 Error Detection Process

 Parity Check
 The simplest error detecting scheme is to
append a parity bit to the end of a block of
data

 If
any even number of bits are inverted
due to error, an undetected error occurs
 row
parity
b1,1 b1,j r1

b2,1 b2,j r2

bi,1 bi,j ri
column
parity c1 cj p

(a) Parity calculation

0 1 1 1 0 1 0 1 1 1 0 1
row parity
0 1 1 1 0 1 0 0 1 1 0 1 error
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 1 1 0 1 0 1 1 1
0 0 0 1 1 0 0 0 0 1 1 0
column
parity error

(b) No errors (c) Correctable single-bit error

0 1 1 1 1 1 0 1
0 0 1 1 0 1 1 0
0 0 1 1 0 0 1 1
0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0
1 1 0 0 0 1 1 0
(d) Uncorrectable error pattern

Figure6.3 A Two-Dimensional Even Parity Scheme

 The Internet Checksum
 Errordetecting code used in many Internet
standard protocols, including IP, TCP, and UDP
 Ones-complement operation
 Replace 0 digits with 1 digits and 1 digits with 0
digits
 Ones-complement addition
 The two numbers are treated as unsigned binary
integers and added
 If there is a carry out of the leftmost bit, add 1 to the
sum (end-around carry)
 0001 0001
Partial sum F203 Partial sum F203
F204 F204
F204 F204
Partial sum F4F5 Partial sum F4F5
1E6F9 1E6F9
E6F9 E6F9
Carry 1 Carry 1
E6FA E6FA
E6FA E6FA
Partial sum F6F7 Partial sum F6F7
1DDF1 1DDF1
DDF1 DDF1
Carry 1 Carry 1
DDF2 DDF2
220D DDF2
Ones complement of the result Partial sum 220D
FFFF

(a) Checksum calculation by sender (b) Checksum verification by receiver

Figure6.4 Exampleof Internet Checksum

 Cyclic Redundancy Check
(CRC)
 One of the most common and powerful error-
detecting codes
 Given a k bit block of bits, the transmitter
generates an (n – k) bit frame check
sequence (FCS) which is exactly divisible by
some predetermined number
 Receiver divides the incoming frame by that
number
 If there is no remainder, assume there is no error
 CRC Process
 Modulo 2 arithmetic  Digital logic
 Uses binary addition with no  Dividing circuit consisting of XOR
carries gates and a shift register
 An example is shown on page 194  Shift register is a string of 1-bit
in the textbook storage devices
 Polynomials  Each device has an output line,
 Express all values as polynomials which indicates the value currently
in a dummy variable X, with binary stored, and an input line
coefficients  At discrete time instants, known
 Coefficients correspond to the bits as clock times, the value in the
in the binary number storage device is replaced by the
 An example is shown on page 197 value indicated by its input line
in the textbook  The entire register is clocked
simultaneously, causing a 1-bit
shift along the entire register
 An example is referenced on page
199 in the textbook
 X9 +X8 +X6 +X4 +X2 +X Q(X)
P(X) X5 +X4 +X2 +1 X14 X12 X8 +X7 + X5 X5D(X)
X14+X13+ X11+ X9
X13+X12+X11+ X9 +X8
X13+X12+ X10+ X8
X11+X10+X9+ X7
X11+X10+ X8 + X6
X9+X8 +X7 +X6 +X5
X9+X8 + X6 + X4
X7 + X5 +X4
X7+X6 + X4 + X2
X6 +X5 + X2
X6+X5 + X3 + X
X3 +X2 + X R(X)

Figure6.5 Exampleof Polynomial Division

 Forward Error Correction
 Correction of detected errors usually requires data blocks to be
retransmitted
 Not appropriate for wireless applications:
 The bit error rate (BER) on a wireless link can be quite high, which would
result in a large number of retransmissions
 Propagation delay is very long compared to the transmission time of a
single frame
 Need to correct errors on basis of bits received
 k bits
codeword
data

FEC
FEC decoder

detectablebut not
encoder

correctableerror
correctable
no error or
error
codeword

n bits
data

Transmitter Receiver

Figure6.8 Error Correction Process

 Block Code Principles
 Hamming distance
 d(v1, v2) between two n –bit binary sequences v1 and v2 is
the number of bits in which v1 and v2 disagree
 See example on page 203 in the textbook
 Redundancy of the code
 The ratio of redundant bits to data bits (n-k)/k
 Code rate
 The ratio of data bits to total bits k/n
 Is a measure of how much additional bandwidth is required
to carry data at the same data rate as without the code
 See example on page 205 in the textbook
 1

10–1
Without
coding
Probability of bit error (BER)

10–2
Rate1/2
coding

10–3

10–4

10–5 Region of
codinggain

10–6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 dB 2.77 dB
(Eb/N0) (dB)

Figure6.9 How Coding Improves System Performance

 Summary
 Types of errors
 Internet checksum
 Error detection
 Cyclic redundancy
check
 Parity check  Modulo 2 arithmetic
 Parity bit  Polynomials
 Two-dimensional parity  Digital logic
check
 Forward error
correction
 Block code principles