Embedded Systems

A computer is a system that has the following or more components.

1. A microprocessor
2. A large memory comprising the following two kinds:
(a) Primary memory (semiconductor memories - RAM, ROM
and fast accessible caches)
(b) Secondary memory (magnetic memory located in hard
disks, diskettes and cartridge tapes
and optical memory in CD-ROM)
3. Input units like keyboard, mouse, digitizer, scanner, etc.
4. Output units like video monitor, printer, etc.
5. Networking units like Ethernet card, front-end processor-based
drivers, etc.
6. I/O units like a modem, fax cum modem, etc.
An embedded system is one that has computer
hardware with software embedded in it as one
of its most important component.
It is a dedicated computer-based system for an
application(s) or product.
1.It has hardware. Figure 1.1 shows the units in the hardware of an
embedded system.
2. It has main application software. The application software may
perform concurrently the series
of tasks or multiple tasks.
3. It has a real time operating system (RTOS) that supervises the
application software and provides
a mechanism to let the processor run a process as per scheduling and
do the context-switch
between the various processes (tasks).
Classifications of embedded systems
1. Small Scale Embedded Systems:
• These systems are designed with a single 8- or 16-bit
• microcontroller; they have little hardware and software
complexities and involve board-level design.
• They may even be battery operated. When developing
embedded software for these, an editor, assembler and cross
assembler, specific to the microcontroller or processor used, are
the main programming tools. Usually, ‘C’ is used for developing
these systems.
• ‘C’ program compilation is done into the assembly, and
executable codes are then appropriately located in
• the system memory. The software has to fit within the memory
available and keep in view the need to limit power dissipation
when system is running continuously.
2. Medium Scale Embedded Systems:
• These systems are usually designed with a single or few
• 16- or 32-bit microcontrollers or DSPs or Reduced Instruction
Set Computers (RISCs).
• These have both hardware and software complexities. For
complex software design, there are the following programming
tools: RTOS,
 Source code engineering tool, Simulator,
 Debugger and Integrated Development Environment (IDE).

Software tools also provide the solutions to the hardware

complexities.
An assembler is of little use as a programming tool.
3. Sophisticated Embedded Systems:
• Sophisticated embedded systems have enormous hardware and
software complexities and may need scalable processors or
configurable processors and programmable logic arrays. They are
used for cutting edge applications that need hardware and
software co-design and integration in the final system; however,
they are constrained by the processing speeds available in their
hardware units.
• Certain software functions such as encryption and deciphering
algorithms, discrete cosine transformation and inverse
transformation algorithms, TCP/IP protocol stacking and network
driver functions are implemented in the hardware to obtain
additional speeds by saving time.
Skills required for an embedded systems designer
Skills for Small Scale Embedded System Designer:
Full understanding of microcontrollers with a basic knowledge of computer
architecture, digital electronic design, software engineering, data
communication, control engineering, motors and actuators, sensors and
measurements, analog electronic design and IC design and manufacture”.
Specific skills will be needed in specific situations.
(i) Computer architecture and organization.
(ii) Memories.
(iii) Memory allocation.
(iv) Interfacing the memories.
(v) Burning (a term used for porting) the executable machine codes
in PROM or ROM (Section 2.3.1).
(vi) Use of decoders and demultiplexers.
(vii) Direct memory accesses.
(viii) Ports.
(ix) Device drivers in assembly.
(x) Simple and sophisticated buses.
(xi) Timers.
(xii) Interrupt servicing mechanism.
(xiii) C programming elements.
(xiv) Memory optimization.
(xv) Selection of hardware and microcontroller.
(xvi) Use of ICE (In-Circuit-Emulators), cross- assemblers and testing equipment.
(xvii) Debugging the software and hardware bugs by using test vectors. Basic
knowledge in the other areas—data communication,
 Embedded Systems

BY
M.V.GANESWARA RAO

TO
M.TECH
(VLSI DESIGN)

Class No : 03 Date:3-11-2009
 1.3 OTHER HARDWARE UNITS

• Power Source and Managing the Power Dissipation and

Consumption
• Clock Oscillator Circuit and Clocking Unit (s)
• Real Time Clock (RTC) and Timers for Various Timing and
Counting Needs of the System
• Reset Circuit, Power-up Reset and Watchdog-Timer Reset
• Memories
• Input, Output and I/O Ports, IO Buses and IO Interfaces
• Interrupts Handler
• DAC (Using a PWM) and ADC
• LCD and LED Displays
• Keypad /Keyboard

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.3.1.Power Source and Managing the Power
Dissipation and Consumption
• Most systems have a power supply of their own. The supply has a
specific operation range or a range of voltages. Various units in an
embedded system operate in one of the following four operation
ranges:
(i) 5.0V ± 0.25V
(ii) 3.3V ± 0.3V
(iii) 2.0 ± 0.2V
(iv) 1.5V ± 0.2V
Additionally :
12V ± 0.2V supply is needed for a flash ,EEPROM when present in the
microcontroller of an embedded system and for RS232C serial Interfaces .

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

The following points have to be taken care of while
connecting the supply rails (lines):
• A processor may have more than two pins of V DD and
V ss. This distributes the power in all the sections and
reduces interference between sections. There should be
a separate radio frequency interference bypassing
capacitor as close as possible to each pair of V DD and
V ss pins in the system processor as well as in other
units.
• Supply should separately power the (a) external I/O
driving ports (b) timers and (c) clock and reset circuits.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

The following are the typical values in six states of the
processor.
• (i) 50 mA when only the processor is running: that is, the
processor is executing instructions.
• (ii) 75 mA when the processor plus the external memories
and chips are in running: state: that is, fetching and
execution are both in progress.
• (iii) 15mA when only the processor is in stop state: that is,
fetching and execution have both stopped and the clock
has been disabled from all structural units of the
processor.
• (iV)15 mA when only the processor is in waiting state: that
is, fetching and execution have both stopped but the clock
has not been disabled from the structural units of the
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
processor, such as timers.
(v) 5 mA when only the processor is in waiting state: that is,
fetching and execution have both stopped but the clock has
not been disabled from the structural units of the processor,
such as timers.
(vi) 10 mA when the processor, the external memories and
the chips are in waiting state. Waiting state now means that
fetching and execution have both stopped; but the clock has
not been disabled from the structural units of the processor
and the external 10 units and dynamic RAMs refreshing also
has not stopped.
Note:An embedded system has to perform tasks continuously from
power-up and may also be left in power-ON state; therefore, power
saving during execution is important

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.3.2.Clock Oscillator Circuit and Clocking
Unit (s)
• processor needs a clock oscillator circuit. The clock
controls the various clocking requirements of the
CPU, of the system timers and the CPU machine
cycles.
• The clock controls the time for executing an
instruction.
• The clock circuit uses either a crystal or a ceramic
resonator (internally associated with the processor)
or an external oscillator IC attached to the
processor.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • The clock controls the time for executing an instruction.

• (a) The crystal resonator gives the highest stability in

frequency with temperature and drift in the circuit.
• (b) The internal ceramic resonator, if available in a
processor, saves the use of the external crystal and gives
a reasonable though not very highly stable frequency.
• (c) The external IC-based clock oscillator has a
significantly higher power dissipation compared to the
internal processor-resonator. However, it provides a
higher driving capability

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.3.3 Real Time Clock (RTC) and Timers for Various Timing and
Counting Needs of the System
• A timer circuit suitably configured is the system-clock, also
called real-time clock (RTC).
• An RTC is used by the schedulers and for real-time
programming.
• An RTC is designed as follows:
Assume a processor generates a clock output every 0.5 Ils.
When a system timer is configured by a software instruction
to issue timeout after 200 inputs from the processor clock
outputs, then there are 10000 interrupts (ticks) each second.
The RTC ticking rate is then 10 kHz and it interrupts every
100 Ils.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.3.4 Reset Circuit, Power-up Reset and Watchdog-Timer Reset

• Reset means that the processor starts the processing of

instructions from a starting address. That address is one
that is set by default in the processor program counter on
a power-up.
• Reset can be activated by one of the following:
• An external reset circuit that activates on the power-up, on
switching-on reset ofthe system or on detection of a low
voltage .
• By (a) software instruction or
(b) time-out by a programmed timer known as watchdog
timer
(c) a clock monitor detecting a slowdown below certain
threshold frequencies due to a fault.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.3.5 Memories

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • (i) Internal RAM of 256 or 512 bytes in a microcontroller
for registers, temporary data and stack.
• (ii) Internal ROM/PROM/EPROM for about 4 kB to 16 kB
of program (in the case of micro controllers).
• (iii) External RAM for the temporary data and stack .
• (iv) Internal caches
• (v) EEPROM or flash
• (vi) External ROM or PROM for embedding software
• (vii) RAM Memory buffers at the ports.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.3.6 Input, Output and I/O Ports

• The system gets inputs from physical devices (such as, for
example, the key-buttons, sensors and transducer circuits)
through the input ports.
• The system gets the inputs by read operation at the port
addresses.
• The system has output ports through which it sends output
bytes to the real world. An output may be to an LED (Light
Emitting diode) or LCD (Liquid Crystal Display) pane1.
• The system sends the output by a write operation to the
port address

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.3.7 Interrupts Handler

• A system may possess a number of devices and the system processor

has to control and handle the requirements of each device by running
an appropriate Interrupt Service Routine (ISR) for each. An interrupts-
handling mechanism must exist in each system to handle interrupts
from various proc­esses in the system.
Important points regarding the interrupts and their handling by
programming are as follows:
1. There can be a number of interrupt sources and groups of interrupt
sources in a processor.
2. zero result or an overflow or underflow during an ALU operation. An
interrupt can also arise through a software timer. A software interrupt
may arise in an exceptional condition that may have developed while
running a program.
3. The system may prioritize the sources and service them accordingly .

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

5.Certain sources are not maskable and cannot be disabled.
Some are defined to the highest priority during processing.
6.The processor's current program has to divert to a service
routine to complete that task on the occurrence of the
interrupt.
7.There is a programmable unit on-chip for the interrupt
handling mechanism in a microcontroller.
8.The application program or scheduler is expected to
schedule and control the running of routines for the interrupts
in a particular application.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 04 Date:6-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 1.4. SOFTWARE EMBEDDED INTO A SYSTEM

• The software Is the most important aspect, the brain

of the embedded system.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.4.1 Final Machine Implementable Software for a Product

• An embedded system processor and the system

need software that is specific to a given application
of that system.
• The processor of the system processes the
instruction codes and data.
• In the final stage, these are placed in the memory
(ROM) for all the tasks that have to be executed.
The final stage software is also called ROM image.
• A machine implement-able software file is therefore
like a table of address and bytes at each address of
the system memory.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Dept. of ECE SVECW M.V.G.Rao 2-11-2009
1.4.2 Coding of Software in Machine Codes
• During coding in this format, the programmer defines
the addresses and the corresponding bytes or bits at
each address.
• For example, in a transceiver, placing certain
machine code and bits can configure it to transmit .
• However, coding in machine implement-able codes
is done only in specific situations.
• it is time consuming because the programmer must
first understand the processor instructions set and
then memorize the instructions and their machine
codes.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.4.3 Software in Processor Specific Assembly
Language
• When a programmer understands the processor and
its instruction set thoroughly, a program or a small
specific part can be coded in the assembly
language.
• An exemplary assembly language program in ARM
processor instruction set .
• To do all the coding in assembly language may,
however, be very time consuming.
• Full coding in assembly may be done only for a few
simple, small-scale systems, such as toys,
automatic chocolate vending machine, robot or data
acquisition system.
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 • Figure 1.6 shows the process of converting an assembly language
program into the machine imple­ment-able software file and then finally
obtaining a ROM image file.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • An assembler translates the assembly software into the
machine codes using a step called assembling.
• In the next step, called linking, a linker links these codes
with the other required assembled codes. Linking is
necessary because of the number of codes to be linked
for the final binary file.
• In the next step, the loader program performs the task of
reallocating the codes after finding the physical RAM
addresses available at a given instant.
• The final step of the system design process is locating the
codes as a ROM image and permanently placing them at
the actually available addresses in the ROM.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.4.4 Software in High Level Language

• To do'all the coding in assembly language may be very

time consuming in most cases.
• Software is therefore developed in a high-level language,
'C' or 'C++' or 'Java'. Most of the times, 'c' is the preferred
language.
• For coding, there is little need to understand assembly
language instructions and the programmer does not have
to know the machine code for any instruction at all.
• The programmer needs to understand only the hardware
organization.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

An exemplary C language program for all the processors

• Add 127,29 and 40 and print the square root.

# include <stdio.h>
# include <math.h>
void main (void)
{
int il, i2, i3, a;
float result;
il = 127;
i2 = 29;
i3 = 40;
a = il + i2 + i3;
result = sqrt (a);
printf (result);
}.

Dept. of ECE SVECW M.V.G.Rao

2-11-2009
Different program layers in enbedded software

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Processing of converting a C program into ROM File

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 1.4.5 Software for the Device Drivers and Device Management using
an Operating System

• In an embedded system, there are a number of physical devices.

Exemplary physical devices are keyboard, display, disk, parallel port
and network-card.
• An innovative concept is use of virtual devices during programming.
• A virtual device example is a file
• A device for the purpose of control, handling, reading and writing
actions can be taken as consist­ing of three components.
(i) Control Register or Word - It stores the bits that, on setting or resetting
by a device driver, control the device actions.
(ii) Status Register or Word - It provides the flags (bits) to show the device
status.
(iii) Device Mechanism that controls the device actions. There may be input
data buffers and output data buffers at a device.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • A device driver is software for controlling, receiving and sending a byte
or a stream of bytes from or to a device.
• In case of physical devices, a driver uses the hardware status flags and
control register bits that are in set and reset states.
• In case of virtual devices also, a driver uses the status and control
words and the bits that exist in set and reset states.
• Driver controls three functions
(i) Initializing that is activated by placing appropriate bits at the control
register or word.
(ii) Calling an ISR on interrupt.
(iii) Resetting the status flag after interrupt service.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Device Management software modules provide codes for
detecting the presence of devices, for initializing these and
for testing the devices that are present.
• The modules may also include software for allocating and
registering port.
• It ensures that any device accesses to one task at any
given instant.
• It takes into account that virtual devices may have
addresses that can be relocated by a locator (for PROM).

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.4.7 Software Tools in Designing of an Embedded System

• Editor
• Interpreter
• Compiler
• Assembler
• Cross Assembler
• Simulator
• Integrated Development Environment
• Locator

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.5 EXEMPLARY EMBEDDED SYSTEMS

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

A few examples of small scale embedded system

• applications are as follows:

• Automatic Chocolate Vending Machine
• Stepper motor controllers for a robotics system
• Washing or cooking system
• Multitasking Toys
• Microcontroller-based single or multi-display digital panel meter for voltage, current,
resistance
• and frequency
• Keyboard controller
• Serial port cards
• Computer Mouse
• CD drive or Hard Disk drive controller
• The peripheral controllers of a computer, for example, a CRT display controller, a
keyboard controller, a DRAM controller, a DMA controller, a printer-controller, a laser
printer-controller, a LAN 'Controller, a disk drive controller
• Fax or photocopy or printer or scanner machine

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Digital diary
• Remote (controller) of TV
• Telephone with memory, display and other sophisticated features
• Motor controls Systems - for example, an accurate control of speed and
position of d.c. motor, robot, and CNC machine; automotive applications such
as a close loop engine control, a dynamic ride control, and an anti-lock braking
system monitor
• Electronic data acquisition and supervisory control system
• Electronic instruments, such as an industrial process controller
• Electronic smart weight display system and an industrial moisture recorder
cum controller
• Digital storage system for a signal wave form or Electric or Water Meter
Readings
• Spectrum analyzer
• Biomedical systems such as an ECG LCD display-cum-recorder, a blood- cell
recorder cum analyzer, and a patient monitor system

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

some examples of medium scale embedded systems

• Computer networking systems

• For Internet appliances
• Entertainment systems - such as a video game and a music system
• Banking systems for example, Bank A TM and Credit card transactions
• Signal Tracking Systems for example, an automatic signal tracker and a
target tracker
• Communication systems such as a mobile
• Image Filtering, Image Processing, Pattern Recognizer, Speech
Processing and Video Processing
• A system that connects a pocket PC or PDA (Personal Digital
Assistant)
• DNA Sequence and pattern storage card and DNA pattern recognizer

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Examples of sophisticated embedded systems

• Embedded systems for wireless LAN and for convergent

technology devices
• Embedded systems for real time video and speech or
multimedia processing systems
• Embedded Interface and Networking systems using high
speed (400 MHz plus), ultra high speed (10 Gbps) and
large bandwidth.
• Security products and High-speed Network security.
Gigabit rate encryption rate products
• Embedded sophisticated system for space lifeboat
(NASA's X-38 project) under development.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 05 Date:10-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 1.6 EMBEDDED SYSTEM-ON-CHIP (SOC) AND IN VLSI
CIRCUIT

• embedded systems are being designed on a single

silicon chip, called System on chip (So C).
• SoC is a new design innovation for embedded
systems.
• An embedded processor is a part of the SoC fLSI
circuit.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • A SoC may be embedded with the following
components:
• multiple processors
• Memories
• IP Cores
• Analog units.
• Network protocol embedded into it.
• Encryption function unit.
• It can embed discrete cosine transforms for signal
processing applications. It nay embed FPGA (Field
Programmable Gate Array) cores [Section 1.6.5].

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • For a number of applications, the GPP
(microcontrollers, microprocessors or DSPs) cores
may not ,suffice.
• For security applications, killer applications, smart
card, video game, cell phone, mobile-Internet, hand-
held embedded systems, Gbps transceivers,
Gigabits per second LAN systems and satellite or
missile systems
• we need special processing units in a VLSI designed
circuit to function as a processor. These special
units are called ASIP.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.6.1 Exemplary SoC for Cell-Phone

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Figure 1.10 shows an SoC that integrates two
internal ASICs, two internal processors (ASIPs),
shared memories and peripheral interfaces on a
common bus.
• Besides a processor and memories and digital
circuits with embedded software for specific
application (s),
• the SoC may possess analog circuits as well].
• An exemplary application of such an ASIC
embedded SoC is the cell-phone.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • ASIP in it is configured to process encoding and an
other does the voice compression.
• One ASIC dials, modulates, demodulates, interfaces
the keyboard and multiple line LCD matrix displays,
stores data input and recalls data from memory.
• ASICs are designed using the VLSI design tools with
proc­essor GPP or ASIP and analog circuits
embedded into the design.
• The designing is done using the Electronic Design
Automation (EDA) tool.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.6.2 ASIP

• Using VLSI tools, a processor itself can be designed. A

system specific processor (ASIP) is the one that does not
use the GPP (standard available CISC or RISC
microprocessor or microcontroller or signal processor).
• The processor on chip incorporates a section of the CISC
or RISC instruction set.
• This specific processor may have especially configurable
instruction-set for an application.
• An ASIP can also be configurable. Using appropriate
tools, an ASIP can be designed and configured for the
instructions needed in the following exemplary functions:
DSP functions, controller signals, processing function.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.6.3 IP Core

• On a VLSI chip, there may be high-level components.

These are components that possess gate-level
sophistication in circuits above that of the counter,
register, multiplier, floating point operation unit and ALU.
• A standard source solution for synthesizing a higher-level
component by configuring FPGA core or a core of VLSI
chip may be available as an Intellectual Property, called
(IP).
• The copyright for the synthesized design of a higher-level
component for gate-level implementation of an IP is held
by the designer or designing company. One has to pay
royalty for every chip shipped.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • An embedded system may incorporate an IP(s) .
• An IP may provide hardwired implement-able design of a
transform or of an encryption algorithm.
• An IP may provide a design for adaptive filtering of a
signal.
• An IP may provide full design for implementing Hyper Text
Transfer Protocol (HTTP) or File Transfer Protocol (FTP)
to transmit a web page or a file on the Internet.
• An IP may be designed for the PCI or USB bus controller.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.6.4 Embedding a GPP

• A General Purpose Processor (GPP) can be embedded

on a VSLI chip.
• Recently, exemplary GPPs, called ARM 7 and ARM 9,
which embed onto a VLSI chip.
• An ARM-processor VLSI-architecture is available either as
a CPU chip or for integrat­ing it into VLSI or SoC.
• ARM provides CISC functionality with RISC architecture at
the core.
• Exemplary ARM 9 applications are setup boxes, cable
modems, and wireless devices such as mobile handsets.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • ARM9 has a single cycle 16 x 32 multiply
accumulate unit. It operates at 200 MHz.
• It uses 0.15 nm CMOSs.
• It has a five-stage pipeline. It incorporates RISC.
• It integrates with a DSP when designing an ASIC
solution having multiprocessors'architecture Section
• An example is its integration with DSP with
TMS320C55x.
• A lower capability but very popular version of ARM9
is ARM7.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

1.6.5 FPGA Core with a Single or Multiple Processor

• A new innovation is Field Programmable Gate Arrays

(FPGA) core with a single or multiple process units on
chip.
• One example is Xilinx Virtex-II Pro FPGA XC2VPI25.
• An FPGA consists of a large number of programmable
gates on a VLSI chip.
• There is a set of gates in each FPGA cell, called 'macro
cell'.
• Each cell has several inputs and outputs. All cells
interconnect like an array (matrix).
• Each interconnection is detachable using a FPGA
programming tool.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 06 Date:11-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 2.Processor and Memory Organization
• 2.1 STRUCTURAL UNITS IN A PROCESSOR

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Structural Unit Functions

MAR Memory Address Register It holds the address of the byte or word to be
fetched from external memories.
MDR Memory Data Register It holds the byte or word fetched from external
memory or I/O address.
Internal Bus It internally connects all the structural units inside the
processor. Its width can be of 8, 18, 32, or 64 bits.

Address Bus It is an external bus that carries the address from the
MAR to the memory as well as to the I/O devices .

Data bus
Control bus
BIU Bus interfacing

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Structural Unit Functions
IR instruction Reg.
ID Instruction Decoder
CU Control unit
ARS Application Reg. set
ALU
PC
SRS Systems Reg. set
SP
IQ instruction queue
PFCU pre fetch control unit
I Cache
D-Cache
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
Structural Unit Functions
BT-Cache, Branch Target cache
MMU
FLPU Floating point Processing unit
FRS Floating Point Reg. Set
Advanced Processing Units
AOU Atomic Operation un its
Two hard ware units used to Increase the Processor
performance:
• Pipelining
• Superscalar

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 •How do pipeline and superscalar units give such higher
performance?
Step 1 : Let us assume that the processor instruction cycle time is
0.02 ms (at 50 MHz operation) and that the processor
executes an instruction in one clock cycle. The processor
performance expected without advanced processing units
will be 50 MIPS.
Step 2 : Assume there is a three-stage pipeline as in ARM? Let us,
for
the moment, ignore the effect of branching (called branch
penalty). Three instructions will process in one clock cycle.
The maximum expected performance of the processor
without superscalar but with pipeline will be 150 MIPS.
Step 3: Assume there is a two-line superscalar. Let us ignore the
effects of unaligned data (data dependency penalty). Six
instiUctions can process in single clock cycle with the
three­stage pipeline and two superscalar units. The
maximum performance will now be six times the processor
cycle time, 300 MIPS.
2-11-2009 Dept. of ECE SVECW M.V.G.Rao
 Essential characteristics of a processor structure

• Instruction Cycle Time: This is the time taken by a processor to execute

a simple instruction, which is -1 I-1S for the 8051 processor operating at
-12 MHz.
• Internal Bus Width: The ALU gets inputs through the buses. Bits in a
single operand to ALU are equal to the bus width.
• CISC or RISC Architecture: CISC or RISC architecture may affect the
system design. CISC has the ability to process complex instructions
and complex data sets with fewer registers. RISC executes simpler
instructions and in a single cycle per instruction.
• Program-Counter (PC) bits and its reset value: The number of PC bits
decides the maximum possible size of the physical memory that can be
accessed by the processor. The reset value tells the designer where
the initial program that runs on system reset or power up should store.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Essential characteristics of a processor structure(Cont…)

• Stack-Pointer bits and its initial reset value: Stack pointer values must
point to addresses of the words stored at the stack.
• Pipelined and Superscalar Units: High processor performance is
required in many cases.
• On-chip Memories as RAM and/or Register files, windows, Caches and
ROM:
• External Interrupts: There are a number of pins in the processor where
the external circuits can send the interrupt signals.
• Interrupt Controller: A processor may possess an internal interrupt
controller to program the service routine priorities and to allocate vector
addresses. An internal interrupt controller is of great help in most
applications.
• Bit Manipulation Instructions: These instructions help in easy
manipulation of bits at the ports and memory addresses.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Essential characteristics of a processor structure(Cont…)

• Floating Point Processor: A processor possessing the FLPU and FRS

units performs the floating-point operations fast.
• Direct Memory Access (DMA) Controller with multiple channels: When
there are number of I/O devices and an I/O device needs to access a
multi byte data set fast, the system memory on­chip DMA controller is of
great help.
• On-Chip MMU: It is needed when using caches.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 07 Date:12-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 2.2 PROCESSOR SELECTION FOR AN EMBEDDED SYSTEM

• The processor selection process can be understood by considering four

representative cases
• A processor having the required structural units and capable of giving the
desired processor performance in a system is then chosen.
Case 1: Systems in which processor instruction cycle time ~ 1 us and on-
chip devices and memory can suffice. Examples are Automatic Chocolate
Vending Machine, 56 kbps Modem, robots, Data Acquisition System like an
ECG recorder or weather recorder or multipoint temperature and pressure
recorder and Real time Robotic Controller.
Case 2: Systems in which processor instruction cycle time ~ 10 to 40 ns
suffice, on-chip devices and memory do not suffice and medium processor
performance is required. Examples are 2 Mbps router, image processing,
Voice- data acquisition, Voice compression, Video decompression,
Adaptive Cruise Control- System with String Stability and Network
Gateway.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Case 3: Systems in which instruction cycle times of 5 ns to
10 ns are required and high MIPS prformance is needed.
Examples are Multi-port 100 Mbps Network Transceiver, Fast
100 Mbps Switches, Routers, Multi channel Fast Encryption
and Decryption System.
Case 4: Systems in which instruction cycle time of even I ns
does not suffice and very high processor performance is
required along with use of the floating point and MAC units.
Examples are Voice Processor, Video processing, Real time
audio or video processing and Mobile Phone Systems.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Example :Case Study of a Real Time Robot Control System

• A robotic system motor needs signaling at the rate above

50 to 100 ms. Hence there is enough time available for
signaling and real time control of multiple motors at the
robot when we use a processor with instruction cycle time
– 1 us.
• The processor speed need not be very high and
performance needed is much below 1 MIPS.
• So no caches and advanced processing units like pipeline
and superscalar processing are required.
• Four-coil stepper motor needs only 4-bit input and a dc
motor needs one bit pulse width modulated output.
Therefore, 8-bit processor suffices.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Frequent accesses and bit manipulations at I/O
ports are needed. CISC architecture there­fore
suffices.
• Program can fit in 4 kB or 8 kB of internal ROM on-
chip and stack sizes needed in the program are
small that can be stacked in on-chip 256 or 512 Byte
RAM. Microcontroller is thus needed. No floating-
point unit is needed.
• Microcontrollers that are appropriate for the above
case are 8051, 68HCII or 68HC12 or 68HC 16 or
80196

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Work out Case studies

• Case study of Voice data compression

• Case study of fast network switching Systems
• Real time video processing

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 08 Date:17-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
2.3 MEMORY DEVICES

Memory 1. Masked ROM

(a) ROM 2. PROM
(b) RAM 3. EPROM
4. EEPROM
5. OTP ROM

1. SRAM
2. DRAM
3. NVRAM
4. EDO RAM
5. SDRAM
6. RDRAM
7. Parameterized Distributed RAM
8. Parameterized Block RAM

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

(i) Masked ROM

• A masked ROM is built from a circuit, which has r inputs (Ao to Ar_l)
and 8 outputs (Do to D7).
• Appropriate masking gives a desired set of outputs at each
combinational circuit. Certain links fuse and others that are masked
do not fuse.
• The embedded software designer provides to a manufactur­ing
foundry a file having a table of desired output bits for the various
combinations of the input address bits. The manufacturer prepares
the programming masks and then programs the ROM at a foundry.
• The ROM is a cost effective solution to a bulk user of ROMs for the
manufacture of embedded systems.
• Masked ROMs are never written at the system manufacturer level.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

(ii) An EPROM, an E2PROM and an OTP ROM

• Special versions of ROM can be programmed at the designer or

manufacturer site for an embedded system with the help of a device
programmer.
• One version is EPROM. It is an ultraviolet rays Erasable and device
programmer Programmable Read Only Memory device.
• Erasing the device means restoring 1 at each bit in the cell arrays at
each ROM address.
• Another version is E2pROM (EEPROM). It is an Electrically Erasable
and Programmable Read Only Memory device.
• EEPROM erasing during an application-program run is done by sending
all eight data bus bits as Is for the write in the presence of a high
voltage (+5V or 12V) and a short duration write pulse.
• number of times an EEPROM can be written is 1 Million times plus.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Flash memory is a recent 5V form of EEPROM in which a
sector of bytes can be erased in a flash (very short duration
corresponding to a single clock cycle).
• The advantage over EEPROM is that the erasing of many
bytes simultaneously saves time in each erase cycle that
precedes a write cycle.
• The disadvantage is that once a sector is erased, each byte
writes into it again one by one, and that takes too long a
time. A new version of flash is boot block flash.
• A sector is reserved to store once only at the time of first
boot. Later on it is protected from any further erase.
• In other words, it has an OTP sector also that can be used
to store ROM image like in a ROM.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Uses of ROM or EPROM

what a ROM embeds:

1.Program codes for various tasks,
2.Interrupt service routines,
3.OS kernel, initialization
4.The standard data or table or constant strings.
The ROM is not only used for program and data
storage, but also used for
• obtaining the prepro­grammed logic outputs and
output sequences for the given sets and
sequences of inputs.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Uses of EEPROM, Flash and OTP

• An EEPROM is usable by erase over 1 million times. It

can be erased during run-time itself.
• Three examples of EEPROM memory device
applications .
1. Storing current date and time in a machine.
2. Storing port statuses.
3. Storing driving, malfunctions and failure history in an
automobile for use by mechanics later on.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • Flash memory is usable about 10000 times for
repeated erasing followed by programming during
the run­time.
• Three examples of flash memory device applications
are as follows.
1.Storing the photographs in a digital camera.
2.Storing voice compressed form in a voice recorder.
3.Storing messages in a mobile phone.

Dept. of ECE SVECW 2-11-2009

 • Examples of uses of an OTP ROM are as follows.
1.Smart card identity number and user's personal
information.
2.Storing boot programs and initial data like a
pictogram displaying a seal or monogram.
3.A TM card or credit card or identity card. Once the
various details written at the bank and handed over
to the account holder, there is no modification
possible in the embedded PROM at the card. Just
as a paper holds information permanently once
written or printed, so also does a PROM.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

2.3.2 RAM Devices

• RAMs are made from cells consisting of MOSFETS

• RAM is volatile
• Two types of RAMS are
• Static RAM(SRAM)
• Dynamic RAM(DRAM)
RAM can be loaded with a very large no of bytes of
program and data
A RAM can be written infinite times

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Static RAM(SRAM)

• There are total 4 MOSFETs pre cell in SRAM

• Static means that once processor write a bit in a cell,
it unchanged until it is modified in processor cycle or
until power switched off.
• An advantage of SRAM is that a write to it is static
as long as power is ON
• It has two Disadvantages
1.It has four times less memory density per chip
2.The speed of operation in a CMOS pair is less when
compared to an n-channel MOSFET

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Dynamic RAM(DRAM)

• In DRAM cells are made by n-channel MOSFET

• When channel does not conduct in logic state ‘1’,it
has the gate and channel capacitance through which
current leak.
• Each cell of DRAM should be read and write again
with in 4 ms or less, to retain a bit in any of its cell
this process is called “Refreshing”
• It has two advantages
1.operation quicker than SRAM
2.cell density greatly increased

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

EDO RAM

• A zero wait states RAM essential in high speed processor

• Zero wait states means that between a demand for bit by
processor and the placement of the bits on the bus, there
is no wait states
• There is DRAM version called EDO RAM(Extended Data
Out RAM)
• While processor reads the first bit(s) for fetching into the
cache , the internally works out the next bit(s) so that just
after first bits is transferred to the cache, the second is
immediately available
• How ever EDO RAM does not act fast when processor
speed increases above 100MHz

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

SDRAM(Synchronous DRAM)

• Improved version of EDO RAM is called SDRAM

• Each cell is organized in row and columns
• Instead of next working on the next bit when first bit
is being read , it works on the next row while the
previous row and columns are being read
• Now next row become readily available
• The SDRAM Does not act fast when processor
speed increases to 1GHz

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 RDRAM(Rambus RAM)

• Currently SDRAM is low cost option and therefore a

chip set may still work with it even when processor
works at 1 GHz plus.
• RDRAM uses 16 bit bus technology in place of 32 or 64
bits to improve bus bandwidth
• A wider bus reduce the bus band width, which is
according to the rate that bits are accessed from
SDRAM
• The improvement in in bus bandwidth in RDRAM occurs
due to compensation provided by the four successive
fetches incase of Rambus compared to a single fetch in
the case of SDRAM

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Parameterized Distributed RAM

• The slices of RAM in a system may be distributed

and allotted statically or dynamically into the
different units or subunits
• A distributed RAM in typical system hold 8 kb
to256KB.there can be 1 k to 16k slice in a typical
system
• The size ,row and columns can be configured
• A distributed RAM for use as I/O buffer can shared
between I/O processor and System processor

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Parameterized Block RAM

• A block of the memory may be associated with a

specific hardware block of the embedded system.
• An example of block memory is memory block for
16*32 multiplier unit for MAC operations in DSP
processor
• There can be 4 to 169 blocks in typical systems
• A block can hold 4 kb to 32kb in typical systems
• The block size may also be configured in certain
systems

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

Uses of RAM

• the RAM is for storing the variables during program run and
storing the stack. It stores input and output buffers, for example,
of speech or image.
• It can also store the application program and data when the ROM
image is stored in a compressed format in an embedded system
and decompression is done before the actual run of the system.
• SRAM is used most commonly.
• DRAM is used mostly in computers or high memory density
systems.
• EDO RAM is used in systems with buses to the devices when
operating with clock rates up to 100 MHz, a zero-wait state is
needed between two fetches, and there is single cycle read or
write.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 • SDRAM synchronises the read operations and keeps the
next word ready while the previous one is being fetched.
This device is used when buses can fetch to the processor
up speed of to 1 GHz.
• RDRAM accesses in burst, four successive words in a single
fetch and thus gives above I GHZ
• In Parameterised Distributed RAM, the RAM distributes in
various system subunits. 10 buffers and transceiver subunits
can have a slice of RAM each and system stack can be at
another slice. devices.
• Parameterised Block RAM is used when a specific block of
the RAM is dedicated for use by a subunit only, for example,
a MAC unit. A parameterised block

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Embedded Systems Concepts
By
M.V.Ganeswara Rao

To
M.Tech
(VLSI Design)

Class No : 09 Date:24-11-2009
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
 2.4 MEMORY SELECTION FOR AN EMBEDDED SYSTEM

• Once software designer coding is over and the ROM

image file is ready, a hardware designer of a system
is faced with the questions of what type of memory
devices and what size of each, should be used.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Table 2.5
Required Memory Devices in Four Exemplary Sets of Systems
Memory Required Case 1: Case 2: Data Case 3: Case 4: Voice Case 5: Digita
Automatic Acquisition Multi-port Processor, Camera or
Chocolate System Network Video Voice
Vending Transceiver, processmg Recorder
Machine, Fast Switches, and Mobile System,
System, Routers, Multi Phone
Real time channel Fast Systems
Robotic Control Encryptions
and decryptions
Processor Used Micro- Micro- Multi- Micro- Micro-
controller controller processor processor +DSP processor
System based Multi-
processor System
Internal ROM 4to8kB 8 kB
or EPROM
Internal EEPROM 256 B to 256 B to
512 B 512 B
Internal RAM 256 B to 256 B to
512 B 512 B
ROM or EPROM No No 64kB 64kB 64kB
device
EEPROM or No 64kB 512 B 32 kB 256 kB to
Flash$ device to 126 kB 16 MB
RAM Device No 4 kB to 8 kB 64kB 1 MB 1 MB
Parameterised No No Yes for 10 buffers.
Distributed RAM 4 kB per channel
Parameterised No No Yes for MAC
Block RAMof ECE SVECW M.V.G.Rao
Dept. unit, Dialing 2-11-2009
10 unit
 12.5 ALLOCATION OF MEMORY TO PROGRAM SEGMENTS AND BLOCKS
AND MEMORY MAP OF A SYSTEM

2.5.1 Functions, Processes, Data and Stacks at the Various Segments of

Memory
• Program routines and processes can have different segments.
• For example, a program code can segmented and each segment
stored at a different memory block.
• A pointer address points to the start of the memory block storing a
segment and an offset value is used to retrieve for a memory
address within that segment.
• The data can also be segmented with each segment at different
blocks. A segment can have partitions of fixed sizes called pages.
• A processor, for example an 80x86, may have segment registers
and offset registers.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Fixed size
4 kb
A segment pages
of length
16B to 4GB

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Pages frame address

An offset
reg.

A0-A31
Code segment
Reg. Segment base

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 2.5.2 Memory Blocks for Elements of the Different Data Structures and
Data-sets

• The software design approach is to use data sets

and data structures in a program.
• There can be different sets and different structures
of data at the memory.
• Following are the data· structures and data sets that
are commonly used during processing in a system
and that are stored a the different memory blocks in
a system.
• Stack • Circular Queue • List
• Array • Table
• Queue • Hash table

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

•stack

• A data structure, called stack is a special program element.

• A stack means an allotted memory block from which a data
element is always read in a LIFO (Last In First Out) way by the
processor.
• Various stack structures may be created during processing.
1. A call can be made for another routine during running of a routine.
In order that on completion of the called routine, the processor
returns only to the one calling, the instruction address for return
must be saved on the stack. There can also be nesting. It means
one routine calling another, and that calling another and return
from the called routine is always to the calling routine. Therefore,
at the memory a block of memory address is allocated to the
stack that saves the return addresses of the nested calls.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

2) There may be at the beginning an input data saved as a stack at
RAM in order to be retrieved later in LIFO mode. An application may
create the run-time stack structures. There can be multiple data
stacks at the different memory blocks, each having a separate
pointer address
3)Each task in a multitasking software design have its own stack
where its context is saved. The context is saved on the processor
switching to another task The context includes the return address for
the program counter, retrieval on switching back to the task. There
can be multiple stacks at the memory f. different contexts at the
different memory blocks, each having a separate pointer ad,
Application programs and supervisory programs (OS) have separate
stacks at separate me blocks

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 2 Byte
Address that PC Acquires
Stack
Holding Return
Addresses on Nested
calls

A Memory Block with Start

and End
Stack
Holding Data
Retrievable in LIFO
Mode

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Stack I
Holding Data
Retrievable - Set 1 Saved
Contents Contexts
of the
Tasks as
the Stacks

Stack N
Holding
Retrievable - Set
N Contents

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

•Array

• 0ne-dimensional array is a special data structure at the

memory.
• It has a pointer address that always points to the first
element of the array. From the first element pointer and
index of that element, an address is constructed from
which the processor can access one of array elements.
• Index is an integer that stars from O. Data word can be
retrieved from any element address in the block that is
allocated to the array.
• A processor register may also be used for storing the
index and another register for array base pointer.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Vector (One Dimensional Array)

Marks [i] at a Memory Block Base Address

Marks [0]
Index i

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

•Queue

• A queue is a data structure with an allotted memory block (buffer) from

which a data element is always retrieved in FIFO mode.
• It has two pointers, one for its head and the other for its tail.
• Any deletion is made from the head address and any insertion is made
at the tail address.
• An exception (an error indication) must be thrown whenever the pointer
increments beyond the block end boundary so that appropriate action
can be taken.

Start Front Back pointer

pointer Deleted pointer for for adding
from queue deleting into queue
from queue
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
•Circular Queue

• A queue is called a circular queue when a pointer on

reaching a limit, returns to its starting value.
• A circular queue means a bounded memory block
allotted to a queue such that its pointer on incrementing
never exceeds the set limit.
• From a circular queue also, the data element is always
retrieved in FIFO way mode and no exception is thrown
on exceeding the limit of the memory block allocated.
• Figure shows a memory block with a circular queue with
its two pointers needed for insertions and deletions.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Start End

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

•Table

• A table is a two-dimensional array (matrix) and is an

important data set that is allocated a memo block.
• There is always a base pointer for a table. It points to
its first element at the first column first row.
• There are two indices, one for a column and other for
a row. Like an array, any element can be retrieved
from three address table base, column index and row
index.
• When instead of a pointer, value is used in an
instruction that value is called displacement.
Displacement can be for a column or row.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 Base Column index
pointer

Row

An element at
a memory
address

columns
Dept. of ECE SVECW M.V.G.Rao 2-11-2009
•Hash table

• A hash table is a data set that is a collection of pairs

of a key and a corresponding value.
• A hash table has a key or name in one column. The
corresponding value or object is at the second
column. The keys may be at non-consecutive
memory addresses.
• Look-up tables store like a hash. If the first column
of a table is used as a key (pointer to the value) and
the second column as a value, we call that table as
look-up table.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

 a memory block with the pointers for a hash.

Name marks

Values or
Name objects
or keys

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

•List

• A list is a data structure with number of memory

blocks, one for each element. A list has a top (head)
pointer for the memory address from where it starts.
• Each list-element at the memory also stores the
pointer to the next element.
• The last element points to null. A list is for non-
consecutively located objects at the memory.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

The memory blocks with the pointers for a list.

Object or
value Next top pointer for next
list element
List top

Dept. of ECE SVECW M.V.G.Rao 2-11-2009

2.5.3 The Memory Maps

• Vectors and pointers, variables, program segments

and memory blocks for data and stack, have
different addresses in the program in Princeton
memory architecture.
• Program segments and memory blocks for data and
stacks have separate sets of address in Harvard
architecture.
• Control signals and read-write instructions are also
separate.

Dept. of ECE SVECW M.V.G.Rao 2-11-2009