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William Stallings Computer Organization and Architecture 6 Edition Reduced Instruction Set Computers

This chapter discusses Reduced Instruction Set Computers (RISC). It describes the key features of RISC including large general purpose registers, limited and simple instruction sets, and optimizing the instruction pipeline. The chapter contrasts RISC with Complex Instruction Set Computers (CISC) and explains how RISC aims to have one instruction complete per cycle through register-to-register operations, few addressing modes, and fixed instruction formats to optimize pipelining. Delayed branching is also described as a technique to optimize pipelining in RISC designs.

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216 views14 pages

William Stallings Computer Organization and Architecture 6 Edition Reduced Instruction Set Computers

This chapter discusses Reduced Instruction Set Computers (RISC). It describes the key features of RISC including large general purpose registers, limited and simple instruction sets, and optimizing the instruction pipeline. The chapter contrasts RISC with Complex Instruction Set Computers (CISC) and explains how RISC aims to have one instruction complete per cycle through register-to-register operations, few addressing modes, and fixed instruction formats to optimize pipelining. Delayed branching is also described as a technique to optimize pipelining in RISC designs.

Uploaded by

nancy_01
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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William Stallings

Computer Organization
and Architecture
6th Edition

Chapter 13
Reduced Instruction
Set Computers
The Next Step - RISC
• Reduced Instruction Set Computer

• Key features
—Large number of general purpose registers
—or use of compiler technology to optimize register
use
—Limited and simple instruction set
—Emphasis on optimising the instruction pipeline
Driving force for CISC
• Software costs far exceed hardware costs
• Increasingly complex high level languages
• Semantic gap
• Leads to:
—Large instruction sets
—More addressing modes
—Hardware implementations of HLL statements
– e.g. CASE (switch) on VAX
Intention of CISC
• Ease compiler writing
• Improve execution efficiency
—Complex operations in microcode
• Support more complex HLLs
Execution Characteristics
• Operations performed
• Operands used
• Execution sequencing
• Studies have been done based on programs
written in HLLs
• Dynamic studies are measured during the
execution of the program
Operations
• Assignments
—Movement of data
• Conditional statements (IF, LOOP)
—Sequence control
• Procedure call-return is very time consuming
• Some HLL instruction lead to many machine
code operations
Why CISC (1)?
• Compiler simplification?
—Disputed…
—Complex machine instructions harder to exploit
—Optimization more difficult
• Smaller programs?
—Program takes up less memory but…
—Memory is now cheap
—May not occupy less bits, just look shorter in
symbolic form
– More instructions require longer op-codes
– Register references require fewer bits
Why CISC (2)?
• Faster programs?
—Bias towards use of simpler instructions
—More complex control unit
—Microprogram control store larger
—thus simple instructions take longer to execute

• It is far from clear that CISC is the appropriate


solution
RISC Characteristics
• One instruction per cycle
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired design (no microcode)
• Fixed instruction format
• More compile time/effort
RISC Pipelining
• Most instructions are register to register
• Two phases of execution
—I: Instruction fetch
—E: Execute
– ALU operation with register input and output
• For load and store
—I: Instruction fetch
—E: Execute
– Calculate memory address
—D: Memory
– Register to memory or memory to register operation
Effects of Pipelining
Optimization of Pipelining
• Delayed branch
—Does not take effect until after execution of following
instruction
—This following instruction is the delay slot
Normal and Delayed Branch
Address Normal Delayed Optimized
100 LOAD X,A LOAD X,A LOAD X,A
101 ADD 1,A ADD 1,A JUMP 105
102 JUMP 105 JUMP 105 ADD 1,A
103 ADD A,B NOOP ADD A,B
104 SUB C,B ADD A,B SUB C,B
105 STORE A,Z SUB C,B STORE A,Z
106 STORE A,Z
Use of Delayed
Branch

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